1 /* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
3 Written 1997-2001 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
22 [link no longer provides useful info -jgarzik]
26 #define DRV_NAME "yellowfin"
27 #define DRV_VERSION "2.0"
28 #define DRV_RELDATE "Jun 27, 2006"
30 #define PFX DRV_NAME ": "
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37 static int max_interrupt_work = 20;
39 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40 /* System-wide count of bogus-rx frames. */
42 static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43 static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44 #elif defined(YF_NEW) /* A future perfect board :->. */
45 static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46 static int fifo_cfg = 0x0028;
48 static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49 static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
52 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54 static int rx_copybreak;
56 /* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
60 #define MAX_UNITS 8 /* More are supported, limit only on options */
61 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
64 /* Do ugly workaround for GX server chipset errata. */
67 /* Operational parameters that are set at compile time. */
69 /* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73 #define TX_RING_SIZE 16
74 #define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75 #define RX_RING_SIZE 64
76 #define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77 #define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
80 /* Operational parameters that usually are not changed. */
81 /* Time in jiffies before concluding the transmitter is hung. */
82 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
85 #define yellowfin_debug debug
87 #include <linux/module.h>
88 #include <linux/kernel.h>
89 #include <linux/string.h>
90 #include <linux/timer.h>
91 #include <linux/errno.h>
92 #include <linux/ioport.h>
93 #include <linux/slab.h>
94 #include <linux/interrupt.h>
95 #include <linux/pci.h>
96 #include <linux/init.h>
97 #include <linux/mii.h>
98 #include <linux/netdevice.h>
99 #include <linux/etherdevice.h>
100 #include <linux/skbuff.h>
101 #include <linux/ethtool.h>
102 #include <linux/crc32.h>
103 #include <linux/bitops.h>
104 #include <asm/uaccess.h>
105 #include <asm/processor.h> /* Processor type for cache alignment. */
106 #include <asm/unaligned.h>
109 /* These identify the driver base version and may not be removed. */
110 static char version[] __devinitdata =
111 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
112 KERN_INFO " http://www.scyld.com/network/yellowfin.html\n"
113 KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
115 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
116 MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
117 MODULE_LICENSE("GPL");
119 module_param(max_interrupt_work, int, 0);
120 module_param(mtu, int, 0);
121 module_param(debug, int, 0);
122 module_param(rx_copybreak, int, 0);
123 module_param_array(options, int, NULL, 0);
124 module_param_array(full_duplex, int, NULL, 0);
125 module_param(gx_fix, int, 0);
126 MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
127 MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
128 MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
129 MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
130 MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
131 MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
132 MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
137 I. Board Compatibility
139 This device driver is designed for the Packet Engines "Yellowfin" Gigabit
140 Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
141 Symbios 53C885E dual function chip.
143 II. Board-specific settings
145 PCI bus devices are configured by the system at boot time, so no jumpers
146 need to be set on the board. The system BIOS preferably should assign the
147 PCI INTA signal to an otherwise unused system IRQ line.
148 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
151 III. Driver operation
155 The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
156 This is a descriptor list scheme similar to that used by the EEPro100 and
157 Tulip. This driver uses two statically allocated fixed-size descriptor lists
158 formed into rings by a branch from the final descriptor to the beginning of
159 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
161 The driver allocates full frame size skbuffs for the Rx ring buffers at
162 open() time and passes the skb->data field to the Yellowfin as receive data
163 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
164 a fresh skbuff is allocated and the frame is copied to the new skbuff.
165 When the incoming frame is larger, the skbuff is passed directly up the
166 protocol stack and replaced by a newly allocated skbuff.
168 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
169 using a full-sized skbuff for small frames vs. the copying costs of larger
170 frames. For small frames the copying cost is negligible (esp. considering
171 that we are pre-loading the cache with immediately useful header
172 information). For large frames the copying cost is non-trivial, and the
173 larger copy might flush the cache of useful data.
175 IIIC. Synchronization
177 The driver runs as two independent, single-threaded flows of control. One
178 is the send-packet routine, which enforces single-threaded use by the
179 dev->tbusy flag. The other thread is the interrupt handler, which is single
180 threaded by the hardware and other software.
182 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
183 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
184 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
185 the 'yp->tx_full' flag.
187 The interrupt handler has exclusive control over the Rx ring and records stats
188 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
189 empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
190 clears both the tx_full and tbusy flags.
194 Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
195 Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
196 and an AlphaStation to verifty the Alpha port!
200 Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
201 Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
203 http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
204 http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
208 See Packet Engines confidential appendix (prototype chips only).
213 enum capability_flags {
214 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
215 HasMACAddrBug=32, /* Only on early revs. */
216 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
218 /* The PCI I/O space extent. */
219 #define YELLOWFIN_SIZE 0x100
224 int pci, pci_mask, subsystem, subsystem_mask;
225 int revision, revision_mask; /* Only 8 bits. */
227 int io_size; /* Needed for I/O region check or ioremap(). */
228 int drv_flags; /* Driver use, intended as capability flags. */
231 static const struct pci_id_info pci_id_tbl[] = {
232 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
234 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
235 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
236 YELLOWFIN_SIZE, HasMII | DontUseEeprom },
240 static const struct pci_device_id yellowfin_pci_tbl[] = {
241 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
242 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
245 MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
248 /* Offsets to the Yellowfin registers. Various sizes and alignments. */
249 enum yellowfin_offsets {
250 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
251 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
252 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
253 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
254 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
255 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
256 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
257 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
259 RxDepth=0xB8, FlowCtrl=0xBC,
260 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
261 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
265 /* The Yellowfin Rx and Tx buffer descriptors.
266 Elements are written as 32 bit for endian portability. */
267 struct yellowfin_desc {
274 struct tx_status_words {
280 #else /* Little endian chips. */
285 #endif /* __BIG_ENDIAN */
288 /* Bits in yellowfin_desc.cmd */
290 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
291 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
292 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
293 BRANCH_IFTRUE=0x040000,
296 /* Bits in yellowfin_desc.status */
297 enum desc_status_bits { RX_EOP=0x0040, };
299 /* Bits in the interrupt status/mask registers. */
300 enum intr_status_bits {
301 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
302 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
303 IntrEarlyRx=0x100, IntrWakeup=0x200, };
305 #define PRIV_ALIGN 31 /* Required alignment mask */
307 struct yellowfin_private {
308 /* Descriptor rings first for alignment.
309 Tx requires a second descriptor for status. */
310 struct yellowfin_desc *rx_ring;
311 struct yellowfin_desc *tx_ring;
312 struct sk_buff* rx_skbuff[RX_RING_SIZE];
313 struct sk_buff* tx_skbuff[TX_RING_SIZE];
314 dma_addr_t rx_ring_dma;
315 dma_addr_t tx_ring_dma;
317 struct tx_status_words *tx_status;
318 dma_addr_t tx_status_dma;
320 struct timer_list timer; /* Media selection timer. */
321 struct net_device_stats stats;
322 /* Frequently used and paired value: keep adjacent for cache effect. */
323 int chip_id, drv_flags;
324 struct pci_dev *pci_dev;
325 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
326 unsigned int rx_buf_sz; /* Based on MTU+slack. */
327 struct tx_status_words *tx_tail_desc;
328 unsigned int cur_tx, dirty_tx;
330 unsigned int tx_full:1; /* The Tx queue is full. */
331 unsigned int full_duplex:1; /* Full-duplex operation requested. */
332 unsigned int duplex_lock:1;
333 unsigned int medialock:1; /* Do not sense media. */
334 unsigned int default_port:4; /* Last dev->if_port value. */
335 /* MII transceiver section. */
336 int mii_cnt; /* MII device addresses. */
337 u16 advertising; /* NWay media advertisement */
338 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
343 static int read_eeprom(void __iomem *ioaddr, int location);
344 static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
345 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
346 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
347 static int yellowfin_open(struct net_device *dev);
348 static void yellowfin_timer(unsigned long data);
349 static void yellowfin_tx_timeout(struct net_device *dev);
350 static void yellowfin_init_ring(struct net_device *dev);
351 static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
352 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
353 static int yellowfin_rx(struct net_device *dev);
354 static void yellowfin_error(struct net_device *dev, int intr_status);
355 static int yellowfin_close(struct net_device *dev);
356 static struct net_device_stats *yellowfin_get_stats(struct net_device *dev);
357 static void set_rx_mode(struct net_device *dev);
358 static struct ethtool_ops ethtool_ops;
361 static int __devinit yellowfin_init_one(struct pci_dev *pdev,
362 const struct pci_device_id *ent)
364 struct net_device *dev;
365 struct yellowfin_private *np;
367 int chip_idx = ent->driver_data;
369 void __iomem *ioaddr;
370 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
371 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
380 /* when built into the kernel, we only print version if device is found */
382 static int printed_version;
383 if (!printed_version++)
387 i = pci_enable_device(pdev);
390 dev = alloc_etherdev(sizeof(*np));
392 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
395 SET_MODULE_OWNER(dev);
396 SET_NETDEV_DEV(dev, &pdev->dev);
398 np = netdev_priv(dev);
400 if (pci_request_regions(pdev, DRV_NAME))
401 goto err_out_free_netdev;
403 pci_set_master (pdev);
405 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
407 goto err_out_free_res;
411 if (drv_flags & DontUseEeprom)
412 for (i = 0; i < 6; i++)
413 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
415 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
416 for (i = 0; i < 6; i++)
417 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
420 /* Reset the chip. */
421 iowrite32(0x80000000, ioaddr + DMACtrl);
423 dev->base_addr = (unsigned long)ioaddr;
426 pci_set_drvdata(pdev, dev);
427 spin_lock_init(&np->lock);
430 np->chip_id = chip_idx;
431 np->drv_flags = drv_flags;
434 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
436 goto err_out_cleardev;
437 np->tx_ring = (struct yellowfin_desc *)ring_space;
438 np->tx_ring_dma = ring_dma;
440 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
442 goto err_out_unmap_tx;
443 np->rx_ring = (struct yellowfin_desc *)ring_space;
444 np->rx_ring_dma = ring_dma;
446 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
448 goto err_out_unmap_rx;
449 np->tx_status = (struct tx_status_words *)ring_space;
450 np->tx_status_dma = ring_dma;
453 option = dev->mem_start;
455 /* The lower four bits are the media type. */
459 np->default_port = option & 15;
460 if (np->default_port)
463 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
469 /* The Yellowfin-specific entries in the device structure. */
470 dev->open = &yellowfin_open;
471 dev->hard_start_xmit = &yellowfin_start_xmit;
472 dev->stop = &yellowfin_close;
473 dev->get_stats = &yellowfin_get_stats;
474 dev->set_multicast_list = &set_rx_mode;
475 dev->do_ioctl = &netdev_ioctl;
476 SET_ETHTOOL_OPS(dev, ðtool_ops);
477 dev->tx_timeout = yellowfin_tx_timeout;
478 dev->watchdog_timeo = TX_TIMEOUT;
483 i = register_netdev(dev);
485 goto err_out_unmap_status;
487 printk(KERN_INFO "%s: %s type %8x at %p, ",
488 dev->name, pci_id_tbl[chip_idx].name,
489 ioread32(ioaddr + ChipRev), ioaddr);
490 for (i = 0; i < 5; i++)
491 printk("%2.2x:", dev->dev_addr[i]);
492 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
494 if (np->drv_flags & HasMII) {
495 int phy, phy_idx = 0;
496 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
497 int mii_status = mdio_read(ioaddr, phy, 1);
498 if (mii_status != 0xffff && mii_status != 0x0000) {
499 np->phys[phy_idx++] = phy;
500 np->advertising = mdio_read(ioaddr, phy, 4);
501 printk(KERN_INFO "%s: MII PHY found at address %d, status "
502 "0x%4.4x advertising %4.4x.\n",
503 dev->name, phy, mii_status, np->advertising);
506 np->mii_cnt = phy_idx;
513 err_out_unmap_status:
514 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
517 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
519 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
521 pci_set_drvdata(pdev, NULL);
522 pci_iounmap(pdev, ioaddr);
524 pci_release_regions(pdev);
530 static int __devinit read_eeprom(void __iomem *ioaddr, int location)
532 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
534 iowrite8(location, ioaddr + EEAddr);
535 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
536 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
538 return ioread8(ioaddr + EERead);
541 /* MII Managemen Data I/O accesses.
542 These routines assume the MDIO controller is idle, and do not exit until
543 the command is finished. */
545 static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
549 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
550 iowrite16(1, ioaddr + MII_Cmd);
551 for (i = 10000; i >= 0; i--)
552 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
554 return ioread16(ioaddr + MII_Rd_Data);
557 static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
561 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
562 iowrite16(value, ioaddr + MII_Wr_Data);
564 /* Wait for the command to finish. */
565 for (i = 10000; i >= 0; i--)
566 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
572 static int yellowfin_open(struct net_device *dev)
574 struct yellowfin_private *yp = netdev_priv(dev);
575 void __iomem *ioaddr = yp->base;
578 /* Reset the chip. */
579 iowrite32(0x80000000, ioaddr + DMACtrl);
581 i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
584 if (yellowfin_debug > 1)
585 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
586 dev->name, dev->irq);
588 yellowfin_init_ring(dev);
590 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
591 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
593 for (i = 0; i < 6; i++)
594 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
596 /* Set up various condition 'select' registers.
597 There are no options here. */
598 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
599 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
600 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
601 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
602 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
603 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
605 /* Initialize other registers: with so many this eventually this will
606 converted to an offset/value list. */
607 iowrite32(dma_ctrl, ioaddr + DMACtrl);
608 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
609 /* Enable automatic generation of flow control frames, period 0xffff. */
610 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
612 yp->tx_threshold = 32;
613 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
615 if (dev->if_port == 0)
616 dev->if_port = yp->default_port;
618 netif_start_queue(dev);
620 /* Setting the Rx mode will start the Rx process. */
621 if (yp->drv_flags & IsGigabit) {
622 /* We are always in full-duplex mode with gigabit! */
624 iowrite16(0x01CF, ioaddr + Cnfg);
626 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
627 iowrite16(0x1018, ioaddr + FrameGap1);
628 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
632 /* Enable interrupts by setting the interrupt mask. */
633 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
634 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
635 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
636 iowrite32(0x80008000, ioaddr + TxCtrl);
638 if (yellowfin_debug > 2) {
639 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
643 /* Set the timer to check for link beat. */
644 init_timer(&yp->timer);
645 yp->timer.expires = jiffies + 3*HZ;
646 yp->timer.data = (unsigned long)dev;
647 yp->timer.function = &yellowfin_timer; /* timer handler */
648 add_timer(&yp->timer);
653 static void yellowfin_timer(unsigned long data)
655 struct net_device *dev = (struct net_device *)data;
656 struct yellowfin_private *yp = netdev_priv(dev);
657 void __iomem *ioaddr = yp->base;
658 int next_tick = 60*HZ;
660 if (yellowfin_debug > 3) {
661 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
662 dev->name, ioread16(ioaddr + IntrStatus));
666 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
667 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
668 int negotiated = lpa & yp->advertising;
669 if (yellowfin_debug > 1)
670 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
671 "link partner capability %4.4x.\n",
672 dev->name, yp->phys[0], bmsr, lpa);
674 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
676 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
678 if (bmsr & BMSR_LSTATUS)
684 yp->timer.expires = jiffies + next_tick;
685 add_timer(&yp->timer);
688 static void yellowfin_tx_timeout(struct net_device *dev)
690 struct yellowfin_private *yp = netdev_priv(dev);
691 void __iomem *ioaddr = yp->base;
693 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
694 "status %4.4x, Rx status %4.4x, resetting...\n",
695 dev->name, yp->cur_tx, yp->dirty_tx,
696 ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
698 /* Note: these should be KERN_DEBUG. */
699 if (yellowfin_debug) {
701 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
702 for (i = 0; i < RX_RING_SIZE; i++)
703 printk(" %8.8x", yp->rx_ring[i].result_status);
704 printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring);
705 for (i = 0; i < TX_RING_SIZE; i++)
706 printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
707 yp->tx_ring[i].result_status);
711 /* If the hardware is found to hang regularly, we will update the code
712 to reinitialize the chip here. */
715 /* Wake the potentially-idle transmit channel. */
716 iowrite32(0x10001000, yp->base + TxCtrl);
717 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
718 netif_wake_queue (dev); /* Typical path */
720 dev->trans_start = jiffies;
721 yp->stats.tx_errors++;
724 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
725 static void yellowfin_init_ring(struct net_device *dev)
727 struct yellowfin_private *yp = netdev_priv(dev);
731 yp->cur_rx = yp->cur_tx = 0;
734 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
736 for (i = 0; i < RX_RING_SIZE; i++) {
737 yp->rx_ring[i].dbdma_cmd =
738 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
739 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
740 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
743 for (i = 0; i < RX_RING_SIZE; i++) {
744 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
745 yp->rx_skbuff[i] = skb;
748 skb->dev = dev; /* Mark as being used by this device. */
749 skb_reserve(skb, 2); /* 16 byte align the IP header. */
750 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
751 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
753 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
754 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
758 /* In this mode the Tx ring needs only a single descriptor. */
759 for (i = 0; i < TX_RING_SIZE; i++) {
760 yp->tx_skbuff[i] = NULL;
761 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
762 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
763 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
766 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
771 /* Tx ring needs a pair of descriptors, the second for the status. */
772 for (i = 0; i < TX_RING_SIZE; i++) {
774 yp->tx_skbuff[i] = 0;
775 /* Branch on Tx error. */
776 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
777 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
778 (j+1)*sizeof(struct yellowfin_desc);
780 if (yp->flags & FullTxStatus) {
781 yp->tx_ring[j].dbdma_cmd =
782 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
783 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
784 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
785 i*sizeof(struct tx_status_words);
787 /* Symbios chips write only tx_errs word. */
788 yp->tx_ring[j].dbdma_cmd =
789 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
790 yp->tx_ring[j].request_cnt = 2;
791 /* Om pade ummmmm... */
792 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
793 i*sizeof(struct tx_status_words) +
794 &(yp->tx_status[0].tx_errs) -
795 &(yp->tx_status[0]));
797 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
798 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
801 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
804 yp->tx_tail_desc = &yp->tx_status[0];
808 static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
810 struct yellowfin_private *yp = netdev_priv(dev);
814 netif_stop_queue (dev);
816 /* Note: Ordering is important here, set the field with the
817 "ownership" bit last, and only then increment cur_tx. */
819 /* Calculate the next Tx descriptor entry. */
820 entry = yp->cur_tx % TX_RING_SIZE;
822 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
823 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
824 /* Fix GX chipset errata. */
825 if (cacheline_end > 24 || cacheline_end == 0) {
826 len = skb->len + 32 - cacheline_end + 1;
827 if (skb_padto(skb, len)) {
828 yp->tx_skbuff[entry] = NULL;
829 netif_wake_queue(dev);
834 yp->tx_skbuff[entry] = skb;
837 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
838 skb->data, len, PCI_DMA_TODEVICE));
839 yp->tx_ring[entry].result_status = 0;
840 if (entry >= TX_RING_SIZE-1) {
841 /* New stop command. */
842 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
843 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
844 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
846 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
847 yp->tx_ring[entry].dbdma_cmd =
848 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
852 yp->tx_ring[entry<<1].request_cnt = len;
853 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
854 skb->data, len, PCI_DMA_TODEVICE));
855 /* The input_last (status-write) command is constant, but we must
856 rewrite the subsequent 'stop' command. */
860 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
861 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
863 /* Final step -- overwrite the old 'stop' command. */
865 yp->tx_ring[entry<<1].dbdma_cmd =
866 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
867 CMD_TX_PKT | BRANCH_IFTRUE) | len);
870 /* Non-x86 Todo: explicitly flush cache lines here. */
872 /* Wake the potentially-idle transmit channel. */
873 iowrite32(0x10001000, yp->base + TxCtrl);
875 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
876 netif_start_queue (dev); /* Typical path */
879 dev->trans_start = jiffies;
881 if (yellowfin_debug > 4) {
882 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
883 dev->name, yp->cur_tx, entry);
888 /* The interrupt handler does all of the Rx thread work and cleans up
889 after the Tx thread. */
890 static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
892 struct net_device *dev = dev_instance;
893 struct yellowfin_private *yp;
894 void __iomem *ioaddr;
895 int boguscnt = max_interrupt_work;
896 unsigned int handled = 0;
898 #ifndef final_version /* Can never occur. */
900 printk (KERN_ERR "yellowfin_interrupt(): irq %d for unknown device.\n", irq);
905 yp = netdev_priv(dev);
908 spin_lock (&yp->lock);
911 u16 intr_status = ioread16(ioaddr + IntrClear);
913 if (yellowfin_debug > 4)
914 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
915 dev->name, intr_status);
917 if (intr_status == 0)
921 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
923 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
927 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
928 int entry = yp->dirty_tx % TX_RING_SIZE;
931 if (yp->tx_ring[entry].result_status == 0)
933 skb = yp->tx_skbuff[entry];
934 yp->stats.tx_packets++;
935 yp->stats.tx_bytes += skb->len;
936 /* Free the original skb. */
937 pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr,
938 skb->len, PCI_DMA_TODEVICE);
939 dev_kfree_skb_irq(skb);
940 yp->tx_skbuff[entry] = NULL;
943 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
944 /* The ring is no longer full, clear tbusy. */
946 netif_wake_queue(dev);
949 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
950 unsigned dirty_tx = yp->dirty_tx;
952 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
954 /* Todo: optimize this. */
955 int entry = dirty_tx % TX_RING_SIZE;
956 u16 tx_errs = yp->tx_status[entry].tx_errs;
959 #ifndef final_version
960 if (yellowfin_debug > 5)
961 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
962 "%4.4x %4.4x %4.4x %4.4x.\n",
964 yp->tx_status[entry].tx_cnt,
965 yp->tx_status[entry].tx_errs,
966 yp->tx_status[entry].total_tx_cnt,
967 yp->tx_status[entry].paused);
970 break; /* It still hasn't been Txed */
971 skb = yp->tx_skbuff[entry];
972 if (tx_errs & 0xF810) {
973 /* There was an major error, log it. */
974 #ifndef final_version
975 if (yellowfin_debug > 1)
976 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
979 yp->stats.tx_errors++;
980 if (tx_errs & 0xF800) yp->stats.tx_aborted_errors++;
981 if (tx_errs & 0x0800) yp->stats.tx_carrier_errors++;
982 if (tx_errs & 0x2000) yp->stats.tx_window_errors++;
983 if (tx_errs & 0x8000) yp->stats.tx_fifo_errors++;
985 #ifndef final_version
986 if (yellowfin_debug > 4)
987 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
990 yp->stats.tx_bytes += skb->len;
991 yp->stats.collisions += tx_errs & 15;
992 yp->stats.tx_packets++;
994 /* Free the original skb. */
995 pci_unmap_single(yp->pci_dev,
996 yp->tx_ring[entry<<1].addr, skb->len,
998 dev_kfree_skb_irq(skb);
999 yp->tx_skbuff[entry] = 0;
1000 /* Mark status as empty. */
1001 yp->tx_status[entry].tx_errs = 0;
1004 #ifndef final_version
1005 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1006 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1007 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1008 dirty_tx += TX_RING_SIZE;
1013 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1014 /* The ring is no longer full, clear tbusy. */
1016 netif_wake_queue(dev);
1019 yp->dirty_tx = dirty_tx;
1020 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1024 /* Log errors and other uncommon events. */
1025 if (intr_status & 0x2ee) /* Abnormal error summary. */
1026 yellowfin_error(dev, intr_status);
1028 if (--boguscnt < 0) {
1029 printk(KERN_WARNING "%s: Too much work at interrupt, "
1030 "status=0x%4.4x.\n",
1031 dev->name, intr_status);
1036 if (yellowfin_debug > 3)
1037 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1038 dev->name, ioread16(ioaddr + IntrStatus));
1040 spin_unlock (&yp->lock);
1041 return IRQ_RETVAL(handled);
1044 /* This routine is logically part of the interrupt handler, but separated
1045 for clarity and better register allocation. */
1046 static int yellowfin_rx(struct net_device *dev)
1048 struct yellowfin_private *yp = netdev_priv(dev);
1049 int entry = yp->cur_rx % RX_RING_SIZE;
1050 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1052 if (yellowfin_debug > 4) {
1053 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1054 entry, yp->rx_ring[entry].result_status);
1055 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1056 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1057 yp->rx_ring[entry].result_status);
1060 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1062 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1063 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1069 if(!desc->result_status)
1071 pci_dma_sync_single_for_cpu(yp->pci_dev, desc->addr,
1072 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1073 desc_status = le32_to_cpu(desc->result_status) >> 16;
1074 buf_addr = rx_skb->data;
1075 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1076 le32_to_cpu(desc->result_status)) & 0xffff;
1077 frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2])));
1078 if (yellowfin_debug > 4)
1079 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1083 if ( ! (desc_status & RX_EOP)) {
1085 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1086 " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1087 yp->stats.rx_length_errors++;
1088 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1089 /* There was a error. */
1090 if (yellowfin_debug > 3)
1091 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1093 yp->stats.rx_errors++;
1094 if (frame_status & 0x0060) yp->stats.rx_length_errors++;
1095 if (frame_status & 0x0008) yp->stats.rx_frame_errors++;
1096 if (frame_status & 0x0010) yp->stats.rx_crc_errors++;
1097 if (frame_status < 0) yp->stats.rx_dropped++;
1098 } else if ( !(yp->drv_flags & IsGigabit) &&
1099 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1100 u8 status1 = buf_addr[data_size-2];
1101 u8 status2 = buf_addr[data_size-1];
1102 yp->stats.rx_errors++;
1103 if (status1 & 0xC0) yp->stats.rx_length_errors++;
1104 if (status2 & 0x03) yp->stats.rx_frame_errors++;
1105 if (status2 & 0x04) yp->stats.rx_crc_errors++;
1106 if (status2 & 0x80) yp->stats.rx_dropped++;
1107 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1108 } else if ((yp->flags & HasMACAddrBug) &&
1109 memcmp(le32_to_cpu(yp->rx_ring_dma +
1110 entry*sizeof(struct yellowfin_desc)),
1111 dev->dev_addr, 6) != 0 &&
1112 memcmp(le32_to_cpu(yp->rx_ring_dma +
1113 entry*sizeof(struct yellowfin_desc)),
1114 "\377\377\377\377\377\377", 6) != 0) {
1115 if (bogus_rx++ == 0)
1116 printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:"
1118 dev->name, buf_addr[0], buf_addr[1], buf_addr[2],
1119 buf_addr[3], buf_addr[4], buf_addr[5]);
1122 struct sk_buff *skb;
1123 int pkt_len = data_size -
1124 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1125 /* To verify: Yellowfin Length should omit the CRC! */
1127 #ifndef final_version
1128 if (yellowfin_debug > 4)
1129 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1130 " of %d, bogus_cnt %d.\n",
1131 pkt_len, data_size, boguscnt);
1133 /* Check if the packet is long enough to just pass up the skbuff
1134 without copying to a properly sized skbuff. */
1135 if (pkt_len > rx_copybreak) {
1136 skb_put(skb = rx_skb, pkt_len);
1137 pci_unmap_single(yp->pci_dev,
1138 yp->rx_ring[entry].addr,
1140 PCI_DMA_FROMDEVICE);
1141 yp->rx_skbuff[entry] = NULL;
1143 skb = dev_alloc_skb(pkt_len + 2);
1147 skb_reserve(skb, 2); /* 16 byte align the IP header */
1148 eth_copy_and_sum(skb, rx_skb->data, pkt_len, 0);
1149 skb_put(skb, pkt_len);
1150 pci_dma_sync_single_for_device(yp->pci_dev, desc->addr,
1152 PCI_DMA_FROMDEVICE);
1154 skb->protocol = eth_type_trans(skb, dev);
1156 dev->last_rx = jiffies;
1157 yp->stats.rx_packets++;
1158 yp->stats.rx_bytes += pkt_len;
1160 entry = (++yp->cur_rx) % RX_RING_SIZE;
1163 /* Refill the Rx ring buffers. */
1164 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1165 entry = yp->dirty_rx % RX_RING_SIZE;
1166 if (yp->rx_skbuff[entry] == NULL) {
1167 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1169 break; /* Better luck next round. */
1170 yp->rx_skbuff[entry] = skb;
1171 skb->dev = dev; /* Mark as being used by this device. */
1172 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1173 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1174 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1176 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1177 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1179 yp->rx_ring[entry - 1].dbdma_cmd =
1180 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1182 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1183 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1190 static void yellowfin_error(struct net_device *dev, int intr_status)
1192 struct yellowfin_private *yp = netdev_priv(dev);
1194 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1195 dev->name, intr_status);
1196 /* Hmmmmm, it's not clear what to do here. */
1197 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1198 yp->stats.tx_errors++;
1199 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1200 yp->stats.rx_errors++;
1203 static int yellowfin_close(struct net_device *dev)
1205 struct yellowfin_private *yp = netdev_priv(dev);
1206 void __iomem *ioaddr = yp->base;
1209 netif_stop_queue (dev);
1211 if (yellowfin_debug > 1) {
1212 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1213 "Rx %4.4x Int %2.2x.\n",
1214 dev->name, ioread16(ioaddr + TxStatus),
1215 ioread16(ioaddr + RxStatus),
1216 ioread16(ioaddr + IntrStatus));
1217 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1218 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1221 /* Disable interrupts by clearing the interrupt mask. */
1222 iowrite16(0x0000, ioaddr + IntrEnb);
1224 /* Stop the chip's Tx and Rx processes. */
1225 iowrite32(0x80000000, ioaddr + RxCtrl);
1226 iowrite32(0x80000000, ioaddr + TxCtrl);
1228 del_timer(&yp->timer);
1230 #if defined(__i386__)
1231 if (yellowfin_debug > 2) {
1232 printk("\n"KERN_DEBUG" Tx ring at %8.8llx:\n",
1233 (unsigned long long)yp->tx_ring_dma);
1234 for (i = 0; i < TX_RING_SIZE*2; i++)
1235 printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1236 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1237 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1238 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1239 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1240 for (i = 0; i < TX_RING_SIZE; i++)
1241 printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1242 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1243 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1245 printk("\n"KERN_DEBUG " Rx ring %8.8llx:\n",
1246 (unsigned long long)yp->rx_ring_dma);
1247 for (i = 0; i < RX_RING_SIZE; i++) {
1248 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1249 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1250 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1251 yp->rx_ring[i].result_status);
1252 if (yellowfin_debug > 6) {
1253 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1255 for (j = 0; j < 0x50; j++)
1257 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1263 #endif /* __i386__ debugging only */
1265 free_irq(dev->irq, dev);
1267 /* Free all the skbuffs in the Rx queue. */
1268 for (i = 0; i < RX_RING_SIZE; i++) {
1269 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1270 yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1271 if (yp->rx_skbuff[i]) {
1272 dev_kfree_skb(yp->rx_skbuff[i]);
1274 yp->rx_skbuff[i] = NULL;
1276 for (i = 0; i < TX_RING_SIZE; i++) {
1277 if (yp->tx_skbuff[i])
1278 dev_kfree_skb(yp->tx_skbuff[i]);
1279 yp->tx_skbuff[i] = NULL;
1282 #ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1283 if (yellowfin_debug > 0) {
1284 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1285 dev->name, bogus_rx);
1292 static struct net_device_stats *yellowfin_get_stats(struct net_device *dev)
1294 struct yellowfin_private *yp = netdev_priv(dev);
1298 /* Set or clear the multicast filter for this adaptor. */
1300 static void set_rx_mode(struct net_device *dev)
1302 struct yellowfin_private *yp = netdev_priv(dev);
1303 void __iomem *ioaddr = yp->base;
1304 u16 cfg_value = ioread16(ioaddr + Cnfg);
1306 /* Stop the Rx process to change any value. */
1307 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1308 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1309 /* Unconditionally log net taps. */
1310 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1311 iowrite16(0x000F, ioaddr + AddrMode);
1312 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1313 /* Too many to filter well, or accept all multicasts. */
1314 iowrite16(0x000B, ioaddr + AddrMode);
1315 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1316 struct dev_mc_list *mclist;
1319 memset(hash_table, 0, sizeof(hash_table));
1320 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1321 i++, mclist = mclist->next) {
1324 /* Due to a bug in the early chip versions, multiple filter
1325 slots must be set for each address. */
1326 if (yp->drv_flags & HasMulticastBug) {
1327 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1328 hash_table[bit >> 4] |= (1 << bit);
1329 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1330 hash_table[bit >> 4] |= (1 << bit);
1331 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1332 hash_table[bit >> 4] |= (1 << bit);
1334 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1335 hash_table[bit >> 4] |= (1 << bit);
1337 /* Copy the hash table to the chip. */
1338 for (i = 0; i < 4; i++)
1339 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1340 iowrite16(0x0003, ioaddr + AddrMode);
1341 } else { /* Normal, unicast/broadcast-only mode. */
1342 iowrite16(0x0001, ioaddr + AddrMode);
1344 /* Restart the Rx process. */
1345 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1348 static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1350 struct yellowfin_private *np = netdev_priv(dev);
1351 strcpy(info->driver, DRV_NAME);
1352 strcpy(info->version, DRV_VERSION);
1353 strcpy(info->bus_info, pci_name(np->pci_dev));
1356 static struct ethtool_ops ethtool_ops = {
1357 .get_drvinfo = yellowfin_get_drvinfo
1360 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1362 struct yellowfin_private *np = netdev_priv(dev);
1363 void __iomem *ioaddr = np->base;
1364 struct mii_ioctl_data *data = if_mii(rq);
1367 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1368 data->phy_id = np->phys[0] & 0x1f;
1371 case SIOCGMIIREG: /* Read MII PHY register. */
1372 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1375 case SIOCSMIIREG: /* Write MII PHY register. */
1376 if (!capable(CAP_NET_ADMIN))
1378 if (data->phy_id == np->phys[0]) {
1379 u16 value = data->val_in;
1380 switch (data->reg_num) {
1382 /* Check for autonegotiation on or reset. */
1383 np->medialock = (value & 0x9000) ? 0 : 1;
1385 np->full_duplex = (value & 0x0100) ? 1 : 0;
1387 case 4: np->advertising = value; break;
1389 /* Perhaps check_duplex(dev), depending on chip semantics. */
1391 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1399 static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1401 struct net_device *dev = pci_get_drvdata(pdev);
1402 struct yellowfin_private *np;
1405 np = netdev_priv(dev);
1407 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1409 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1410 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1411 unregister_netdev (dev);
1413 pci_iounmap(pdev, np->base);
1415 pci_release_regions (pdev);
1418 pci_set_drvdata(pdev, NULL);
1422 static struct pci_driver yellowfin_driver = {
1424 .id_table = yellowfin_pci_tbl,
1425 .probe = yellowfin_init_one,
1426 .remove = __devexit_p(yellowfin_remove_one),
1430 static int __init yellowfin_init (void)
1432 /* when a module, this is printed whether or not devices are found in probe */
1436 return pci_module_init (&yellowfin_driver);
1440 static void __exit yellowfin_cleanup (void)
1442 pci_unregister_driver (&yellowfin_driver);
1446 module_init(yellowfin_init);
1447 module_exit(yellowfin_cleanup);
1451 * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1452 * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1453 * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"