2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/config.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/interrupt.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <asm/system.h>
44 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
45 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
46 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
47 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
48 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
49 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
50 /* Redefine this flagword to set debug level */
51 #define DEBUG_LEVEL DBG_K_STANDARD
53 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
55 #define DBG_PRINT( dbg_flags, args... ) \
57 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
60 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
61 __FILE__, __LINE__, __FUNCTION__ ); \
62 sprintf( __dbg_str_buf + len, args ); \
63 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
67 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
68 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
70 #define DEFINE_DBG_BUFFER
71 #define DBG_ENTER_ROUTINE
72 #define DBG_LEAVE_ROUTINE
91 } __attribute__ ((packed));
93 /* offsets to the controller registers based on the above structure layout */
95 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
96 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
97 CAPREG = offsetof(struct ctrl_reg, cap_reg),
98 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
99 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
100 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
101 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
102 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
103 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
104 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
105 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
106 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
107 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
108 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
110 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
112 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
113 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
114 #define CAP_REG(cb) ( cb + CAPREG )
115 #define DEV_CAP(cb) ( cb + DEVCAP )
116 #define DEV_CTRL(cb) ( cb + DEVCTRL )
117 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
118 #define LNK_CAP(cb) ( cb + LNKCAP )
119 #define LNK_CTRL(cb) ( cb + LNKCTRL )
120 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
121 #define SLOT_CAP(cb) ( cb + SLOTCAP )
122 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
123 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
124 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
125 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
127 #define hp_register_read_word(pdev, reg , value) \
128 pci_read_config_word(pdev, reg, &value)
130 #define hp_register_read_dword(pdev, reg , value) \
131 pci_read_config_dword(pdev, reg, &value)
133 #define hp_register_write_word(pdev, reg , value) \
134 pci_write_config_word(pdev, reg, value)
136 #define hp_register_dwrite_word(pdev, reg , value) \
137 pci_write_config_dword(pdev, reg, value)
139 /* Field definitions in PCI Express Capabilities Register */
140 #define CAP_VER 0x000F
141 #define DEV_PORT_TYPE 0x00F0
142 #define SLOT_IMPL 0x0100
143 #define MSG_NUM 0x3E00
145 /* Device or Port Type */
146 #define NAT_ENDPT 0x00
147 #define LEG_ENDPT 0x01
148 #define ROOT_PORT 0x04
149 #define UP_STREAM 0x05
150 #define DN_STREAM 0x06
151 #define PCIE_PCI_BRDG 0x07
152 #define PCI_PCIE_BRDG 0x10
154 /* Field definitions in Device Capabilities Register */
155 #define DATTN_BUTTN_PRSN 0x1000
156 #define DATTN_LED_PRSN 0x2000
157 #define DPWR_LED_PRSN 0x4000
159 /* Field definitions in Link Capabilities Register */
160 #define MAX_LNK_SPEED 0x000F
161 #define MAX_LNK_WIDTH 0x03F0
163 /* Link Width Encoding */
172 /*Field definitions of Link Status Register */
173 #define LNK_SPEED 0x000F
174 #define NEG_LINK_WD 0x03F0
175 #define LNK_TRN_ERR 0x0400
176 #define LNK_TRN 0x0800
177 #define SLOT_CLK_CONF 0x1000
179 /* Field definitions in Slot Capabilities Register */
180 #define ATTN_BUTTN_PRSN 0x00000001
181 #define PWR_CTRL_PRSN 0x00000002
182 #define MRL_SENS_PRSN 0x00000004
183 #define ATTN_LED_PRSN 0x00000008
184 #define PWR_LED_PRSN 0x00000010
185 #define HP_SUPR_RM_SUP 0x00000020
186 #define HP_CAP 0x00000040
187 #define SLOT_PWR_VALUE 0x000003F8
188 #define SLOT_PWR_LIMIT 0x00000C00
189 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
191 /* Field definitions in Slot Control Register */
192 #define ATTN_BUTTN_ENABLE 0x0001
193 #define PWR_FAULT_DETECT_ENABLE 0x0002
194 #define MRL_DETECT_ENABLE 0x0004
195 #define PRSN_DETECT_ENABLE 0x0008
196 #define CMD_CMPL_INTR_ENABLE 0x0010
197 #define HP_INTR_ENABLE 0x0020
198 #define ATTN_LED_CTRL 0x00C0
199 #define PWR_LED_CTRL 0x0300
200 #define PWR_CTRL 0x0400
202 /* Attention indicator and Power indicator states */
204 #define LED_BLINK 0x10
207 /* Power Control Command */
209 #define POWER_OFF 0x0400
211 /* Field definitions in Slot Status Register */
212 #define ATTN_BUTTN_PRESSED 0x0001
213 #define PWR_FAULT_DETECTED 0x0002
214 #define MRL_SENS_CHANGED 0x0004
215 #define PRSN_DETECT_CHANGED 0x0008
216 #define CMD_COMPLETED 0x0010
217 #define MRL_STATE 0x0020
218 #define PRSN_STATE 0x0040
220 struct php_ctlr_state_s {
221 struct php_ctlr_state_s *pnext;
222 struct pci_dev *pci_dev;
224 unsigned long flags; /* spinlock's */
225 u32 slot_device_offset;
227 struct timer_list int_poll_timer; /* Added for poll event */
228 php_intr_callback_t attention_button_callback;
229 php_intr_callback_t switch_change_callback;
230 php_intr_callback_t presence_change_callback;
231 php_intr_callback_t power_fault_callback;
232 void *callback_instance_id;
233 struct ctrl_reg *creg; /* Ptr to controller register space */
237 static spinlock_t hpc_event_lock;
239 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
240 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
241 static int ctlr_seq_num = 0; /* Controller sequence # */
242 static spinlock_t list_lock;
244 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
246 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
248 /* This is the interrupt polling timeout function. */
249 static void int_poll_timeout(unsigned long lphp_ctlr)
251 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
256 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
260 /* Poll for interrupt events. regs == NULL => polling */
261 pcie_isr( 0, (void *)php_ctlr, NULL );
263 init_timer(&php_ctlr->int_poll_timer);
265 if (!pciehp_poll_time)
266 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
268 start_int_poll_timer(php_ctlr, pciehp_poll_time);
273 /* This function starts the interrupt polling timer. */
274 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
277 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
281 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
282 seconds = 2; /* Clamp to sane value */
284 php_ctlr->int_poll_timer.function = &int_poll_timeout;
285 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
286 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
287 add_timer(&php_ctlr->int_poll_timer);
292 static int pcie_write_cmd(struct slot *slot, u16 cmd)
294 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
300 dbg("%s : Enter\n", __FUNCTION__);
302 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
306 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
308 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
311 dbg("%s : hp_register_read_word SLOT_STATUS %x\n", __FUNCTION__, slot_status);
313 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
314 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
315 the next command according to spec. Just print out the error message */
316 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
319 dbg("%s: Before hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd);
320 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
322 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
325 dbg("%s : hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, cmd | CMD_CMPL_INTR_ENABLE);
326 dbg("%s : Exit\n", __FUNCTION__);
332 static int hpc_check_lnk_status(struct controller *ctrl)
334 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
341 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
345 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
348 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
352 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
353 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
354 !(lnk_status & NEG_LINK_WD)) {
355 err("%s : Link Training Error occurs \n", __FUNCTION__);
365 static int hpc_get_attention_status(struct slot *slot, u8 *status)
367 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
375 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
379 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
382 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
386 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
388 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
390 switch (atten_led_state) {
392 *status = 0xFF; /* Reserved */
395 *status = 1; /* On */
398 *status = 2; /* Blink */
401 *status = 0; /* Off */
412 static int hpc_get_power_status(struct slot * slot, u8 *status)
414 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
422 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
426 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
429 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
432 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
434 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
453 static int hpc_get_latch_status(struct slot *slot, u8 *status)
455 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
462 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
466 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
469 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
473 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
479 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
481 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
489 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
493 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
496 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
499 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
500 *status = (card_state == 1) ? 1 : 0;
506 static int hpc_query_power_fault(struct slot * slot)
508 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
517 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
521 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
524 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
527 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
528 status = (pwr_fault != 1) ? 1 : 0;
531 /* Note: Logic 0 => fault */
535 static int hpc_set_attention_status(struct slot *slot, u8 value)
537 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
542 dbg("%s: \n", __FUNCTION__);
544 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
548 if (slot->hp_slot >= php_ctlr->num_slots) {
549 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
552 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
555 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
558 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
561 case 0 : /* turn off */
562 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
564 case 1: /* turn on */
565 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
567 case 2: /* turn blink */
568 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
573 if (!pciehp_poll_mode)
574 slot_cmd = slot_cmd | HP_INTR_ENABLE;
576 pcie_write_cmd(slot, slot_cmd);
577 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
583 static void hpc_set_green_led_on(struct slot *slot)
585 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
590 dbg("%s: \n", __FUNCTION__);
592 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
596 if (slot->hp_slot >= php_ctlr->num_slots) {
597 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
601 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
604 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
607 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
608 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
609 if (!pciehp_poll_mode)
610 slot_cmd = slot_cmd | HP_INTR_ENABLE;
612 pcie_write_cmd(slot, slot_cmd);
614 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
618 static void hpc_set_green_led_off(struct slot *slot)
620 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
625 dbg("%s: \n", __FUNCTION__);
627 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
631 if (slot->hp_slot >= php_ctlr->num_slots) {
632 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
636 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
639 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
642 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
644 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
646 if (!pciehp_poll_mode)
647 slot_cmd = slot_cmd | HP_INTR_ENABLE;
648 pcie_write_cmd(slot, slot_cmd);
649 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
654 static void hpc_set_green_led_blink(struct slot *slot)
656 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
661 dbg("%s: \n", __FUNCTION__);
663 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
667 if (slot->hp_slot >= php_ctlr->num_slots) {
668 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
672 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
675 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
678 dbg("%s : hp_register_read_word SLOT_CTRL %x\n", __FUNCTION__, slot_ctrl);
680 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
682 if (!pciehp_poll_mode)
683 slot_cmd = slot_cmd | HP_INTR_ENABLE;
684 pcie_write_cmd(slot, slot_cmd);
686 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
690 int pcie_get_ctlr_slot_config(struct controller *ctrl,
691 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
692 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
693 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
696 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
703 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
707 *first_device_num = 0;
710 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
713 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
717 *physical_slot_num = slot_cap >> 19;
718 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
720 *ctrlcap = slot_cap & 0x0000007f;
726 static void hpc_release_ctlr(struct controller *ctrl)
728 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
729 struct php_ctlr_state_s *p, *p_prev;
734 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
738 if (pciehp_poll_mode) {
739 del_timer(&php_ctlr->int_poll_timer);
742 free_irq(php_ctlr->irq, ctrl);
745 pci_disable_msi(php_ctlr->pci_dev);
748 if (php_ctlr->pci_dev)
749 php_ctlr->pci_dev = NULL;
751 spin_lock(&list_lock);
752 p = php_ctlr_list_head;
757 p_prev->pnext = p->pnext;
759 php_ctlr_list_head = p->pnext;
766 spin_unlock(&list_lock);
774 static int hpc_power_on_slot(struct slot * slot)
776 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
783 dbg("%s: \n", __FUNCTION__);
786 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
790 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
791 if (slot->hp_slot >= php_ctlr->num_slots) {
792 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
796 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
799 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
802 dbg("%s: SLOT_CTRL %x, value read %xn", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base),
805 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
807 if (!pciehp_poll_mode)
808 slot_cmd = slot_cmd | HP_INTR_ENABLE;
810 retval = pcie_write_cmd(slot, slot_cmd);
813 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
816 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
823 static int hpc_power_off_slot(struct slot * slot)
825 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
832 dbg("%s: \n", __FUNCTION__);
835 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
839 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
841 if (slot->hp_slot >= php_ctlr->num_slots) {
842 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
845 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
848 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
851 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base),
854 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
856 if (!pciehp_poll_mode)
857 slot_cmd = slot_cmd | HP_INTR_ENABLE;
859 retval = pcie_write_cmd(slot, slot_cmd);
862 err("%s: Write command failed!\n", __FUNCTION__);
865 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
872 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
874 struct controller *ctrl = NULL;
875 struct php_ctlr_state_s *php_ctlr;
876 u8 schedule_flag = 0;
877 u16 slot_status, intr_detect, intr_loc;
879 int hp_slot = 0; /* only 1 slot per PCI Express port */
885 if (!pciehp_poll_mode) {
887 php_ctlr = ctrl->hpc_ctlr_handle;
890 ctrl = (struct controller *)php_ctlr->callback_instance_id;
894 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
899 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
903 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
905 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
909 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
910 PRSN_DETECT_CHANGED | CMD_COMPLETED );
912 intr_loc = slot_status & intr_detect;
914 /* Check to see if it was our interrupt */
918 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
919 /* Mask Hot-plug Interrupt Enable */
920 if (!pciehp_poll_mode) {
921 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
923 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
927 dbg("%s: Set Mask Hot-plug Interrupt Enable\n", __FUNCTION__);
928 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
929 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
931 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
933 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
936 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
938 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
940 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
943 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
945 /* Clear command complete interrupt caused by this write */
947 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
949 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
952 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
955 if (intr_loc & CMD_COMPLETED) {
957 * Command Complete Interrupt Pending
959 dbg("%s: In Command Complete Interrupt Pending\n", __FUNCTION__);
960 wake_up_interruptible(&ctrl->queue);
963 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
964 schedule_flag += php_ctlr->switch_change_callback(
965 hp_slot, php_ctlr->callback_instance_id);
966 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
967 schedule_flag += php_ctlr->attention_button_callback(
968 hp_slot, php_ctlr->callback_instance_id);
969 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
970 schedule_flag += php_ctlr->presence_change_callback(
971 hp_slot , php_ctlr->callback_instance_id);
972 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
973 schedule_flag += php_ctlr->power_fault_callback(
974 hp_slot, php_ctlr->callback_instance_id);
976 /* Clear all events after serving them */
978 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
980 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
983 /* Unmask Hot-plug Interrupt Enable */
984 if (!pciehp_poll_mode) {
985 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
987 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
991 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
992 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
993 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
995 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
997 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1000 dbg("%s: hp_register_write_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
1002 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1004 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1007 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
1009 /* Clear command complete interrupt caused by this write */
1011 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1013 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1016 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
1022 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1024 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1025 enum pcie_link_speed lnk_speed;
1032 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1036 if (slot->hp_slot >= php_ctlr->num_slots) {
1037 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1041 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1044 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1048 switch (lnk_cap & 0x000F) {
1050 lnk_speed = PCIE_2PT5GB;
1053 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1058 dbg("Max link speed = %d\n", lnk_speed);
1063 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1065 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1066 enum pcie_link_width lnk_wdth;
1073 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1077 if (slot->hp_slot >= php_ctlr->num_slots) {
1078 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1082 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1085 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1089 switch ((lnk_cap & 0x03F0) >> 4){
1091 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1094 lnk_wdth = PCIE_LNK_X1;
1097 lnk_wdth = PCIE_LNK_X2;
1100 lnk_wdth = PCIE_LNK_X4;
1103 lnk_wdth = PCIE_LNK_X8;
1106 lnk_wdth = PCIE_LNK_X12;
1109 lnk_wdth = PCIE_LNK_X16;
1112 lnk_wdth = PCIE_LNK_X32;
1115 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1120 dbg("Max link width = %d\n", lnk_wdth);
1125 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1127 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1128 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1135 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1139 if (slot->hp_slot >= php_ctlr->num_slots) {
1140 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1144 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1147 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1151 switch (lnk_status & 0x0F) {
1153 lnk_speed = PCIE_2PT5GB;
1156 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1161 dbg("Current link speed = %d\n", lnk_speed);
1166 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1168 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1169 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1176 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1180 if (slot->hp_slot >= php_ctlr->num_slots) {
1181 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1185 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1188 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1192 switch ((lnk_status & 0x03F0) >> 4){
1194 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1197 lnk_wdth = PCIE_LNK_X1;
1200 lnk_wdth = PCIE_LNK_X2;
1203 lnk_wdth = PCIE_LNK_X4;
1206 lnk_wdth = PCIE_LNK_X8;
1209 lnk_wdth = PCIE_LNK_X12;
1212 lnk_wdth = PCIE_LNK_X16;
1215 lnk_wdth = PCIE_LNK_X32;
1218 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1223 dbg("Current link width = %d\n", lnk_wdth);
1228 static struct hpc_ops pciehp_hpc_ops = {
1229 .power_on_slot = hpc_power_on_slot,
1230 .power_off_slot = hpc_power_off_slot,
1231 .set_attention_status = hpc_set_attention_status,
1232 .get_power_status = hpc_get_power_status,
1233 .get_attention_status = hpc_get_attention_status,
1234 .get_latch_status = hpc_get_latch_status,
1235 .get_adapter_status = hpc_get_adapter_status,
1237 .get_max_bus_speed = hpc_get_max_lnk_speed,
1238 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1239 .get_max_lnk_width = hpc_get_max_lnk_width,
1240 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1242 .query_power_fault = hpc_query_power_fault,
1243 .green_led_on = hpc_set_green_led_on,
1244 .green_led_off = hpc_set_green_led_off,
1245 .green_led_blink = hpc_set_green_led_blink,
1247 .release_ctlr = hpc_release_ctlr,
1248 .check_lnk_status = hpc_check_lnk_status,
1251 int pcie_init(struct controller * ctrl,
1252 struct pcie_device *dev,
1253 php_intr_callback_t attention_button_callback,
1254 php_intr_callback_t switch_change_callback,
1255 php_intr_callback_t presence_change_callback,
1256 php_intr_callback_t power_fault_callback)
1258 struct php_ctlr_state_s *php_ctlr, *p;
1259 void *instance_id = ctrl;
1261 static int first = 1;
1264 u16 intr_enable = 0;
1266 int cap_base, saved_cap_base;
1267 u16 slot_status, slot_ctrl;
1268 struct pci_dev *pdev;
1272 spin_lock_init(&list_lock);
1273 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1275 if (!php_ctlr) { /* allocate controller state data */
1276 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1280 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1283 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1285 dbg("%s: pdev->vendor %x pdev->device %x\n", __FUNCTION__,
1286 pdev->vendor, pdev->device);
1288 saved_cap_base = pcie_cap_base;
1290 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1291 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1292 goto abort_free_ctlr;
1295 ctrl->cap_base = cap_base;
1297 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1299 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1301 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1302 goto abort_free_ctlr;
1304 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1306 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1307 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1308 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1309 goto abort_free_ctlr;
1312 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1314 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1315 goto abort_free_ctlr;
1317 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1319 if (!(slot_cap & HP_CAP)) {
1320 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1321 goto abort_free_ctlr;
1323 /* For debugging purpose */
1324 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1326 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1327 goto abort_free_ctlr;
1329 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1331 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1333 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1334 goto abort_free_ctlr;
1336 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1339 spin_lock_init(&hpc_event_lock);
1343 dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number,
1344 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1345 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1346 if (pci_resource_len(pdev, rc) > 0)
1347 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1348 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1350 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1351 pdev->subsystem_vendor, pdev->subsystem_device);
1353 if (pci_enable_device(pdev))
1354 goto abort_free_ctlr;
1356 init_MUTEX(&ctrl->crit_sect);
1357 /* setup wait queue */
1358 init_waitqueue_head(&ctrl->queue);
1361 php_ctlr->irq = dev->irq;
1362 dbg("HPC interrupt = %d\n", php_ctlr->irq);
1364 /* Save interrupt callback info */
1365 php_ctlr->attention_button_callback = attention_button_callback;
1366 php_ctlr->switch_change_callback = switch_change_callback;
1367 php_ctlr->presence_change_callback = presence_change_callback;
1368 php_ctlr->power_fault_callback = power_fault_callback;
1369 php_ctlr->callback_instance_id = instance_id;
1371 /* return PCI Controller Info */
1372 php_ctlr->slot_device_offset = 0;
1373 php_ctlr->num_slots = 1;
1375 /* Mask Hot-plug Interrupt Enable */
1376 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1378 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1379 goto abort_free_ctlr;
1382 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1383 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1385 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1387 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1388 goto abort_free_ctlr;
1390 dbg("%s : Mask HPIE hp_register_write_word SLOT_CTRL %x\n", __FUNCTION__, temp_word);
1392 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1394 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1395 goto abort_free_ctlr;
1397 dbg("%s: Mask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base)
1400 temp_word = 0x1F; /* Clear all events */
1401 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1403 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1404 goto abort_free_ctlr;
1406 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), temp_word);
1408 if (pciehp_poll_mode) {/* Install interrupt polling code */
1409 /* Install and start the interrupt polling timer */
1410 init_timer(&php_ctlr->int_poll_timer);
1411 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1413 /* Installs the interrupt handler */
1414 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1415 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1417 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1418 goto abort_free_ctlr;
1422 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1424 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1425 goto abort_free_ctlr;
1427 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1428 dbg("%s: slot_cap %x\n", __FUNCTION__, slot_cap);
1430 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1432 if (ATTN_BUTTN(slot_cap))
1433 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1435 if (POWER_CTRL(slot_cap))
1436 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1438 if (MRL_SENS(slot_cap))
1439 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1441 temp_word = (temp_word & ~intr_enable) | intr_enable;
1443 if (pciehp_poll_mode) {
1444 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1446 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1448 dbg("%s: temp_word %x\n", __FUNCTION__, temp_word);
1450 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1451 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1453 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1454 goto abort_free_ctlr;
1456 dbg("%s : Unmask HPIE hp_register_write_word SLOT_CTRL with %x\n", __FUNCTION__, temp_word);
1457 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1459 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1460 goto abort_free_ctlr;
1462 dbg("%s: Unmask HPIE SLOT_STATUS offset %x reads slot_status %x\n", __FUNCTION__,
1463 SLOT_STATUS(ctrl->cap_base), slot_status);
1465 temp_word = 0x1F; /* Clear all events */
1466 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1468 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1469 goto abort_free_ctlr;
1471 dbg("%s: SLOT_STATUS offset %x writes slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), temp_word);
1473 rc = get_hp_hw_control_from_firmware(ctrl->pci_dev);
1475 goto abort_free_ctlr;
1477 /* Add this HPC instance into the HPC list */
1478 spin_lock(&list_lock);
1479 if (php_ctlr_list_head == 0) {
1480 php_ctlr_list_head = php_ctlr;
1481 p = php_ctlr_list_head;
1484 p = php_ctlr_list_head;
1489 p->pnext = php_ctlr;
1491 spin_unlock(&list_lock);
1494 ctrl->hpc_ctlr_handle = php_ctlr;
1495 ctrl->hpc_ops = &pciehp_hpc_ops;
1500 /* We end up here for the many possible ways to fail this API. */
1502 pcie_cap_base = saved_cap_base;