2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
38 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
39 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
40 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
41 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
42 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
43 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
44 /* Redefine this flagword to set debug level */
45 #define DEBUG_LEVEL DBG_K_STANDARD
47 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49 #define DBG_PRINT( dbg_flags, args... ) \
51 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
54 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
55 __FILE__, __LINE__, __FUNCTION__ ); \
56 sprintf( __dbg_str_buf + len, args ); \
57 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
61 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
62 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #define DEFINE_DBG_BUFFER
65 #define DBG_ENTER_ROUTINE
66 #define DBG_LEAVE_ROUTINE
85 } __attribute__ ((packed));
87 /* offsets to the controller registers based on the above structure layout */
89 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
90 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
91 CAPREG = offsetof(struct ctrl_reg, cap_reg),
92 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
93 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
94 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
95 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
96 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
97 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
98 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
99 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
100 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
101 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
102 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
104 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
106 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
107 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
108 #define CAP_REG(cb) ( cb + CAPREG )
109 #define DEV_CAP(cb) ( cb + DEVCAP )
110 #define DEV_CTRL(cb) ( cb + DEVCTRL )
111 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
112 #define LNK_CAP(cb) ( cb + LNKCAP )
113 #define LNK_CTRL(cb) ( cb + LNKCTRL )
114 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
115 #define SLOT_CAP(cb) ( cb + SLOTCAP )
116 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
117 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
118 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
119 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
121 #define hp_register_read_word(pdev, reg , value) \
122 pci_read_config_word(pdev, reg, &value)
124 #define hp_register_read_dword(pdev, reg , value) \
125 pci_read_config_dword(pdev, reg, &value)
127 #define hp_register_write_word(pdev, reg , value) \
128 pci_write_config_word(pdev, reg, value)
130 #define hp_register_dwrite_word(pdev, reg , value) \
131 pci_write_config_dword(pdev, reg, value)
133 /* Field definitions in PCI Express Capabilities Register */
134 #define CAP_VER 0x000F
135 #define DEV_PORT_TYPE 0x00F0
136 #define SLOT_IMPL 0x0100
137 #define MSG_NUM 0x3E00
139 /* Device or Port Type */
140 #define NAT_ENDPT 0x00
141 #define LEG_ENDPT 0x01
142 #define ROOT_PORT 0x04
143 #define UP_STREAM 0x05
144 #define DN_STREAM 0x06
145 #define PCIE_PCI_BRDG 0x07
146 #define PCI_PCIE_BRDG 0x10
148 /* Field definitions in Device Capabilities Register */
149 #define DATTN_BUTTN_PRSN 0x1000
150 #define DATTN_LED_PRSN 0x2000
151 #define DPWR_LED_PRSN 0x4000
153 /* Field definitions in Link Capabilities Register */
154 #define MAX_LNK_SPEED 0x000F
155 #define MAX_LNK_WIDTH 0x03F0
157 /* Link Width Encoding */
166 /*Field definitions of Link Status Register */
167 #define LNK_SPEED 0x000F
168 #define NEG_LINK_WD 0x03F0
169 #define LNK_TRN_ERR 0x0400
170 #define LNK_TRN 0x0800
171 #define SLOT_CLK_CONF 0x1000
173 /* Field definitions in Slot Capabilities Register */
174 #define ATTN_BUTTN_PRSN 0x00000001
175 #define PWR_CTRL_PRSN 0x00000002
176 #define MRL_SENS_PRSN 0x00000004
177 #define ATTN_LED_PRSN 0x00000008
178 #define PWR_LED_PRSN 0x00000010
179 #define HP_SUPR_RM_SUP 0x00000020
180 #define HP_CAP 0x00000040
181 #define SLOT_PWR_VALUE 0x000003F8
182 #define SLOT_PWR_LIMIT 0x00000C00
183 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
185 /* Field definitions in Slot Control Register */
186 #define ATTN_BUTTN_ENABLE 0x0001
187 #define PWR_FAULT_DETECT_ENABLE 0x0002
188 #define MRL_DETECT_ENABLE 0x0004
189 #define PRSN_DETECT_ENABLE 0x0008
190 #define CMD_CMPL_INTR_ENABLE 0x0010
191 #define HP_INTR_ENABLE 0x0020
192 #define ATTN_LED_CTRL 0x00C0
193 #define PWR_LED_CTRL 0x0300
194 #define PWR_CTRL 0x0400
196 /* Attention indicator and Power indicator states */
198 #define LED_BLINK 0x10
201 /* Power Control Command */
203 #define POWER_OFF 0x0400
205 /* Field definitions in Slot Status Register */
206 #define ATTN_BUTTN_PRESSED 0x0001
207 #define PWR_FAULT_DETECTED 0x0002
208 #define MRL_SENS_CHANGED 0x0004
209 #define PRSN_DETECT_CHANGED 0x0008
210 #define CMD_COMPLETED 0x0010
211 #define MRL_STATE 0x0020
212 #define PRSN_STATE 0x0040
214 static spinlock_t hpc_event_lock;
216 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
217 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
218 static int ctlr_seq_num = 0; /* Controller sequence # */
219 static spinlock_t list_lock;
221 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs);
223 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
225 /* This is the interrupt polling timeout function. */
226 static void int_poll_timeout(unsigned long lphp_ctlr)
228 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
233 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
237 /* Poll for interrupt events. regs == NULL => polling */
238 pcie_isr( 0, (void *)php_ctlr, NULL );
240 init_timer(&php_ctlr->int_poll_timer);
242 if (!pciehp_poll_time)
243 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
245 start_int_poll_timer(php_ctlr, pciehp_poll_time);
250 /* This function starts the interrupt polling timer. */
251 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
254 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
258 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
259 seconds = 2; /* Clamp to sane value */
261 php_ctlr->int_poll_timer.function = &int_poll_timeout;
262 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
263 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
264 add_timer(&php_ctlr->int_poll_timer);
269 static int pcie_write_cmd(struct slot *slot, u16 cmd)
271 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
278 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
282 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
284 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
288 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
289 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
290 the next command according to spec. Just print out the error message */
291 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
294 retval = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
296 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
304 static int hpc_check_lnk_status(struct controller *ctrl)
306 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
313 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
317 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
320 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
324 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
325 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
326 !(lnk_status & NEG_LINK_WD)) {
327 err("%s : Link Training Error occurs \n", __FUNCTION__);
337 static int hpc_get_attention_status(struct slot *slot, u8 *status)
339 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
347 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
351 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
354 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
358 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
360 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
362 switch (atten_led_state) {
364 *status = 0xFF; /* Reserved */
367 *status = 1; /* On */
370 *status = 2; /* Blink */
373 *status = 0; /* Off */
384 static int hpc_get_power_status(struct slot * slot, u8 *status)
386 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
394 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
398 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
401 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
404 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
406 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
425 static int hpc_get_latch_status(struct slot *slot, u8 *status)
427 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
434 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
438 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
441 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
445 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
451 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
453 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
461 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
465 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
468 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
471 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
472 *status = (card_state == 1) ? 1 : 0;
478 static int hpc_query_power_fault(struct slot * slot)
480 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
489 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
493 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(slot->ctrl->cap_base), slot_status);
496 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
499 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
500 status = (pwr_fault != 1) ? 1 : 0;
503 /* Note: Logic 0 => fault */
507 static int hpc_set_attention_status(struct slot *slot, u8 value)
509 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
517 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
521 if (slot->hp_slot >= php_ctlr->num_slots) {
522 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
525 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
528 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
533 case 0 : /* turn off */
534 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
536 case 1: /* turn on */
537 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
539 case 2: /* turn blink */
540 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
545 if (!pciehp_poll_mode)
546 slot_cmd = slot_cmd | HP_INTR_ENABLE;
548 pcie_write_cmd(slot, slot_cmd);
549 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
556 static void hpc_set_green_led_on(struct slot *slot)
558 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
566 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
570 if (slot->hp_slot >= php_ctlr->num_slots) {
571 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
575 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
578 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
581 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
582 if (!pciehp_poll_mode)
583 slot_cmd = slot_cmd | HP_INTR_ENABLE;
585 pcie_write_cmd(slot, slot_cmd);
587 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
592 static void hpc_set_green_led_off(struct slot *slot)
594 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
602 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
606 if (slot->hp_slot >= php_ctlr->num_slots) {
607 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
611 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
614 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
618 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
620 if (!pciehp_poll_mode)
621 slot_cmd = slot_cmd | HP_INTR_ENABLE;
622 pcie_write_cmd(slot, slot_cmd);
623 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
629 static void hpc_set_green_led_blink(struct slot *slot)
631 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
639 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
643 if (slot->hp_slot >= php_ctlr->num_slots) {
644 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
648 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
651 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
655 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
657 if (!pciehp_poll_mode)
658 slot_cmd = slot_cmd | HP_INTR_ENABLE;
659 pcie_write_cmd(slot, slot_cmd);
661 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
666 int pcie_get_ctlr_slot_config(struct controller *ctrl,
667 int *num_ctlr_slots, /* number of slots in this HPC; only 1 in PCIE */
668 int *first_device_num, /* PCI dev num of the first slot in this PCIE */
669 int *physical_slot_num, /* phy slot num of the first slot in this PCIE */
672 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
679 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
683 *first_device_num = 0;
686 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
689 err("%s : hp_register_read_dword SLOT_CAP failed\n", __FUNCTION__);
693 *physical_slot_num = slot_cap >> 19;
694 dbg("%s: PSN %d \n", __FUNCTION__, *physical_slot_num);
696 *ctrlcap = slot_cap & 0x0000007f;
702 static void hpc_release_ctlr(struct controller *ctrl)
704 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
705 struct php_ctlr_state_s *p, *p_prev;
710 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
714 if (pciehp_poll_mode) {
715 del_timer(&php_ctlr->int_poll_timer);
718 free_irq(php_ctlr->irq, ctrl);
721 pci_disable_msi(php_ctlr->pci_dev);
724 if (php_ctlr->pci_dev)
725 php_ctlr->pci_dev = NULL;
727 spin_lock(&list_lock);
728 p = php_ctlr_list_head;
733 p_prev->pnext = p->pnext;
735 php_ctlr_list_head = p->pnext;
742 spin_unlock(&list_lock);
750 static int hpc_power_on_slot(struct slot * slot)
752 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
761 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
765 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
766 if (slot->hp_slot >= php_ctlr->num_slots) {
767 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
771 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
774 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
778 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
780 if (!pciehp_poll_mode)
781 slot_cmd = slot_cmd | HP_INTR_ENABLE;
783 retval = pcie_write_cmd(slot, slot_cmd);
786 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
789 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
796 static int hpc_power_off_slot(struct slot * slot)
798 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
807 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
811 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
813 if (slot->hp_slot >= php_ctlr->num_slots) {
814 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
817 retval = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
820 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
824 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
826 if (!pciehp_poll_mode)
827 slot_cmd = slot_cmd | HP_INTR_ENABLE;
829 retval = pcie_write_cmd(slot, slot_cmd);
832 err("%s: Write command failed!\n", __FUNCTION__);
835 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
842 static irqreturn_t pcie_isr(int IRQ, void *dev_id, struct pt_regs *regs)
844 struct controller *ctrl = NULL;
845 struct php_ctlr_state_s *php_ctlr;
846 u8 schedule_flag = 0;
847 u16 slot_status, intr_detect, intr_loc;
849 int hp_slot = 0; /* only 1 slot per PCI Express port */
855 if (!pciehp_poll_mode) {
857 php_ctlr = ctrl->hpc_ctlr_handle;
860 ctrl = (struct controller *)php_ctlr->callback_instance_id;
864 dbg("%s: dev_id %p ctlr == NULL\n", __FUNCTION__, (void*) dev_id);
869 dbg("%s: php_ctlr == NULL\n", __FUNCTION__);
873 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
875 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
879 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
880 PRSN_DETECT_CHANGED | CMD_COMPLETED );
882 intr_loc = slot_status & intr_detect;
884 /* Check to see if it was our interrupt */
888 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
889 /* Mask Hot-plug Interrupt Enable */
890 if (!pciehp_poll_mode) {
891 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
893 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
897 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
898 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
900 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
902 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
906 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
908 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
911 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
913 /* Clear command complete interrupt caused by this write */
915 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
917 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
922 if (intr_loc & CMD_COMPLETED) {
924 * Command Complete Interrupt Pending
926 wake_up_interruptible(&ctrl->queue);
929 if ((php_ctlr->switch_change_callback) && (intr_loc & MRL_SENS_CHANGED))
930 schedule_flag += php_ctlr->switch_change_callback(
931 hp_slot, php_ctlr->callback_instance_id);
932 if ((php_ctlr->attention_button_callback) && (intr_loc & ATTN_BUTTN_PRESSED))
933 schedule_flag += php_ctlr->attention_button_callback(
934 hp_slot, php_ctlr->callback_instance_id);
935 if ((php_ctlr->presence_change_callback) && (intr_loc & PRSN_DETECT_CHANGED))
936 schedule_flag += php_ctlr->presence_change_callback(
937 hp_slot , php_ctlr->callback_instance_id);
938 if ((php_ctlr->power_fault_callback) && (intr_loc & PWR_FAULT_DETECTED))
939 schedule_flag += php_ctlr->power_fault_callback(
940 hp_slot, php_ctlr->callback_instance_id);
942 /* Clear all events after serving them */
944 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
946 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
949 /* Unmask Hot-plug Interrupt Enable */
950 if (!pciehp_poll_mode) {
951 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
953 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
957 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
958 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
960 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
962 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
966 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
968 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
972 /* Clear command complete interrupt caused by this write */
974 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
976 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
979 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
985 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
987 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
988 enum pcie_link_speed lnk_speed;
995 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
999 if (slot->hp_slot >= php_ctlr->num_slots) {
1000 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1004 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1007 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1011 switch (lnk_cap & 0x000F) {
1013 lnk_speed = PCIE_2PT5GB;
1016 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1021 dbg("Max link speed = %d\n", lnk_speed);
1026 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
1028 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1029 enum pcie_link_width lnk_wdth;
1036 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1040 if (slot->hp_slot >= php_ctlr->num_slots) {
1041 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1045 retval = hp_register_read_dword(php_ctlr->pci_dev, LNK_CAP(slot->ctrl->cap_base), lnk_cap);
1048 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
1052 switch ((lnk_cap & 0x03F0) >> 4){
1054 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1057 lnk_wdth = PCIE_LNK_X1;
1060 lnk_wdth = PCIE_LNK_X2;
1063 lnk_wdth = PCIE_LNK_X4;
1066 lnk_wdth = PCIE_LNK_X8;
1069 lnk_wdth = PCIE_LNK_X12;
1072 lnk_wdth = PCIE_LNK_X16;
1075 lnk_wdth = PCIE_LNK_X32;
1078 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1083 dbg("Max link width = %d\n", lnk_wdth);
1088 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
1090 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1091 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1098 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1102 if (slot->hp_slot >= php_ctlr->num_slots) {
1103 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1107 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1110 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1114 switch (lnk_status & 0x0F) {
1116 lnk_speed = PCIE_2PT5GB;
1119 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1124 dbg("Current link speed = %d\n", lnk_speed);
1129 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1131 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1132 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1139 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1143 if (slot->hp_slot >= php_ctlr->num_slots) {
1144 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1148 retval = hp_register_read_word(php_ctlr->pci_dev, LNK_STATUS(slot->ctrl->cap_base), lnk_status);
1151 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
1155 switch ((lnk_status & 0x03F0) >> 4){
1157 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1160 lnk_wdth = PCIE_LNK_X1;
1163 lnk_wdth = PCIE_LNK_X2;
1166 lnk_wdth = PCIE_LNK_X4;
1169 lnk_wdth = PCIE_LNK_X8;
1172 lnk_wdth = PCIE_LNK_X12;
1175 lnk_wdth = PCIE_LNK_X16;
1178 lnk_wdth = PCIE_LNK_X32;
1181 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1186 dbg("Current link width = %d\n", lnk_wdth);
1191 static struct hpc_ops pciehp_hpc_ops = {
1192 .power_on_slot = hpc_power_on_slot,
1193 .power_off_slot = hpc_power_off_slot,
1194 .set_attention_status = hpc_set_attention_status,
1195 .get_power_status = hpc_get_power_status,
1196 .get_attention_status = hpc_get_attention_status,
1197 .get_latch_status = hpc_get_latch_status,
1198 .get_adapter_status = hpc_get_adapter_status,
1200 .get_max_bus_speed = hpc_get_max_lnk_speed,
1201 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1202 .get_max_lnk_width = hpc_get_max_lnk_width,
1203 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1205 .query_power_fault = hpc_query_power_fault,
1206 .green_led_on = hpc_set_green_led_on,
1207 .green_led_off = hpc_set_green_led_off,
1208 .green_led_blink = hpc_set_green_led_blink,
1210 .release_ctlr = hpc_release_ctlr,
1211 .check_lnk_status = hpc_check_lnk_status,
1214 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1216 struct php_ctlr_state_s *php_ctlr, *p;
1217 void *instance_id = ctrl;
1219 static int first = 1;
1222 u16 intr_enable = 0;
1224 int cap_base, saved_cap_base;
1225 u16 slot_status, slot_ctrl;
1226 struct pci_dev *pdev;
1230 spin_lock_init(&list_lock);
1231 php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1233 if (!php_ctlr) { /* allocate controller state data */
1234 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1238 memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1241 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1243 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1244 __FUNCTION__, pdev->vendor, pdev->device);
1246 saved_cap_base = pcie_cap_base;
1248 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1249 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1250 goto abort_free_ctlr;
1253 ctrl->cap_base = cap_base;
1255 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1257 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1259 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1260 goto abort_free_ctlr;
1262 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1264 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1265 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1266 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1267 goto abort_free_ctlr;
1270 rc = hp_register_read_dword(php_ctlr->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1272 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1273 goto abort_free_ctlr;
1275 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1277 if (!(slot_cap & HP_CAP)) {
1278 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1279 goto abort_free_ctlr;
1281 /* For debugging purpose */
1282 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1284 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1285 goto abort_free_ctlr;
1287 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1289 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1291 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1292 goto abort_free_ctlr;
1294 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1297 spin_lock_init(&hpc_event_lock);
1301 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1302 if (pci_resource_len(pdev, rc) > 0)
1303 dbg("pci resource[%d] start=0x%lx(len=0x%lx)\n", rc,
1304 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc));
1306 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1307 pdev->subsystem_vendor, pdev->subsystem_device);
1309 if (pci_enable_device(pdev))
1310 goto abort_free_ctlr;
1312 init_MUTEX(&ctrl->crit_sect);
1313 /* setup wait queue */
1314 init_waitqueue_head(&ctrl->queue);
1317 php_ctlr->irq = dev->irq;
1319 /* Save interrupt callback info */
1320 php_ctlr->attention_button_callback = pciehp_handle_attention_button;
1321 php_ctlr->switch_change_callback = pciehp_handle_switch_change;
1322 php_ctlr->presence_change_callback = pciehp_handle_presence_change;
1323 php_ctlr->power_fault_callback = pciehp_handle_power_fault;
1324 php_ctlr->callback_instance_id = instance_id;
1326 /* return PCI Controller Info */
1327 php_ctlr->slot_device_offset = 0;
1328 php_ctlr->num_slots = 1;
1330 /* Mask Hot-plug Interrupt Enable */
1331 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1333 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1334 goto abort_free_ctlr;
1337 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1338 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1340 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1342 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1343 goto abort_free_ctlr;
1346 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1348 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1349 goto abort_free_ctlr;
1352 temp_word = 0x1F; /* Clear all events */
1353 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1355 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1356 goto abort_free_ctlr;
1359 if (pciehp_poll_mode) {/* Install interrupt polling code */
1360 /* Install and start the interrupt polling timer */
1361 init_timer(&php_ctlr->int_poll_timer);
1362 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1364 /* Installs the interrupt handler */
1365 rc = request_irq(php_ctlr->irq, pcie_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1366 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1368 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1369 goto abort_free_ctlr;
1373 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1374 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1376 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1378 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1379 goto abort_free_ctlr;
1382 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1384 if (ATTN_BUTTN(slot_cap))
1385 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1387 if (POWER_CTRL(slot_cap))
1388 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1390 if (MRL_SENS(slot_cap))
1391 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1393 temp_word = (temp_word & ~intr_enable) | intr_enable;
1395 if (pciehp_poll_mode) {
1396 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1398 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1401 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1402 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1404 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1405 goto abort_free_ctlr;
1407 rc = hp_register_read_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1409 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1410 goto abort_free_ctlr;
1413 temp_word = 0x1F; /* Clear all events */
1414 rc = hp_register_write_word(php_ctlr->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1416 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1417 goto abort_free_ctlr;
1420 rc = get_hp_hw_control_from_firmware(ctrl->pci_dev);
1422 goto abort_free_ctlr;
1424 /* Add this HPC instance into the HPC list */
1425 spin_lock(&list_lock);
1426 if (php_ctlr_list_head == 0) {
1427 php_ctlr_list_head = php_ctlr;
1428 p = php_ctlr_list_head;
1431 p = php_ctlr_list_head;
1436 p->pnext = php_ctlr;
1438 spin_unlock(&list_lock);
1441 ctrl->hpc_ctlr_handle = php_ctlr;
1442 ctrl->hpc_ops = &pciehp_hpc_ops;
1447 /* We end up here for the many possible ways to fail this API. */
1449 pcie_cap_base = saved_cap_base;