2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
61 } __attribute__ ((packed));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
129 /* Link Width Encoding */
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
169 /* Attention indicator and Power indicator states */
171 #define LED_BLINK 0x10
174 /* Power Control Command */
176 #define POWER_OFF 0x0400
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
199 struct controller *ctrl = (struct controller *)data;
201 /* Poll for interrupt events. regs == NULL => polling */
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
208 start_int_poll_timer(ctrl, pciehp_poll_time);
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
224 static inline int pciehp_request_irq(struct controller *ctrl)
226 int retval, irq = ctrl->pci_dev->irq;
228 /* Install interrupt polling timer. Start with 10 sec delay */
229 if (pciehp_poll_mode) {
230 init_timer(&ctrl->poll_timer);
231 start_int_poll_timer(ctrl, 10);
235 /* Installs the interrupt handler */
236 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
238 err("Cannot get irq %d for the hotplug controller\n", irq);
242 static inline void pciehp_free_irq(struct controller *ctrl)
244 if (pciehp_poll_mode)
245 del_timer_sync(&ctrl->poll_timer);
247 free_irq(ctrl->pci_dev->irq, ctrl);
250 static inline int pcie_poll_cmd(struct controller *ctrl)
255 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status))
256 if (slot_status & CMD_COMPLETED)
258 for (timeout = 1000; timeout > 0; timeout -= 100) {
260 if (!pciehp_readw(ctrl, SLOTSTATUS, &slot_status))
261 if (slot_status & CMD_COMPLETED)
264 return 0; /* timeout */
267 pciehp_writew(ctrl, SLOTSTATUS, CMD_COMPLETED);
271 static inline void pcie_wait_cmd(struct controller *ctrl, int poll)
273 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
274 unsigned long timeout = msecs_to_jiffies(msecs);
278 rc = pcie_poll_cmd(ctrl);
280 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
282 dbg("Command not completed in 1000 msec\n");
286 * pcie_write_cmd - Issue controller command
287 * @ctrl: controller to which the command is issued
288 * @cmd: command value written to slot control register
289 * @mask: bitmask of slot control register to be modified
291 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
297 mutex_lock(&ctrl->ctrl_lock);
299 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
301 err("%s: Cannot read SLOTSTATUS register\n", __func__);
305 if (slot_status & CMD_COMPLETED) {
306 if (!ctrl->no_cmd_complete) {
308 * After 1 sec and CMD_COMPLETED still not set, just
309 * proceed forward to issue the next command according
310 * to spec. Just print out the error message.
312 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
314 } else if (!NO_CMD_CMPL(ctrl)) {
316 * This controller semms to notify of command completed
317 * event even though it supports none of power
318 * controller, attention led, power led and EMI.
320 dbg("%s: Unexpected CMD_COMPLETED. Need to wait for "
321 "command completed event.\n", __func__);
322 ctrl->no_cmd_complete = 0;
324 dbg("%s: Unexpected CMD_COMPLETED. Maybe the "
325 "controller is broken.\n", __func__);
329 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
331 err("%s: Cannot read SLOTCTRL register\n", __func__);
336 slot_ctrl |= (cmd & mask);
337 /* Don't enable command completed if caller is changing it. */
338 if (!(mask & CMD_CMPL_INTR_ENABLE))
339 slot_ctrl |= CMD_CMPL_INTR_ENABLE;
343 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
345 err("%s: Cannot write to SLOTCTRL register\n", __func__);
348 * Wait for command completion.
350 if (!retval && !ctrl->no_cmd_complete) {
353 * if hotplug interrupt is not enabled or command
354 * completed interrupt is not enabled, we need to poll
355 * command completed event.
357 if (!(slot_ctrl & HP_INTR_ENABLE) ||
358 !(slot_ctrl & CMD_CMPL_INTR_ENABLE))
360 pcie_wait_cmd(ctrl, poll);
363 mutex_unlock(&ctrl->ctrl_lock);
367 static int hpc_check_lnk_status(struct controller *ctrl)
372 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
374 err("%s: Cannot read LNKSTATUS register\n", __func__);
378 dbg("%s: lnk_status = %x\n", __func__, lnk_status);
379 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
380 !(lnk_status & NEG_LINK_WD)) {
381 err("%s : Link Training Error occurs \n", __func__);
389 static int hpc_get_attention_status(struct slot *slot, u8 *status)
391 struct controller *ctrl = slot->ctrl;
396 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
398 err("%s: Cannot read SLOTCTRL register\n", __func__);
402 dbg("%s: SLOTCTRL %x, value read %x\n",
403 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
405 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
407 switch (atten_led_state) {
409 *status = 0xFF; /* Reserved */
412 *status = 1; /* On */
415 *status = 2; /* Blink */
418 *status = 0; /* Off */
428 static int hpc_get_power_status(struct slot *slot, u8 *status)
430 struct controller *ctrl = slot->ctrl;
435 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
437 err("%s: Cannot read SLOTCTRL register\n", __func__);
440 dbg("%s: SLOTCTRL %x value read %x\n",
441 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
443 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
460 static int hpc_get_latch_status(struct slot *slot, u8 *status)
462 struct controller *ctrl = slot->ctrl;
466 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
468 err("%s: Cannot read SLOTSTATUS register\n", __func__);
472 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
477 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
479 struct controller *ctrl = slot->ctrl;
484 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
486 err("%s: Cannot read SLOTSTATUS register\n", __func__);
489 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
490 *status = (card_state == 1) ? 1 : 0;
495 static int hpc_query_power_fault(struct slot *slot)
497 struct controller *ctrl = slot->ctrl;
502 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
504 err("%s: Cannot check for power fault\n", __func__);
507 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
512 static int hpc_get_emi_status(struct slot *slot, u8 *status)
514 struct controller *ctrl = slot->ctrl;
518 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
520 err("%s : Cannot check EMI status\n", __func__);
523 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
528 static int hpc_toggle_emi(struct slot *slot)
536 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
537 slot->last_emi_toggle = get_seconds();
542 static int hpc_set_attention_status(struct slot *slot, u8 value)
544 struct controller *ctrl = slot->ctrl;
549 cmd_mask = ATTN_LED_CTRL;
551 case 0 : /* turn off */
554 case 1: /* turn on */
557 case 2: /* turn blink */
563 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
564 dbg("%s: SLOTCTRL %x write cmd %x\n",
565 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
570 static void hpc_set_green_led_on(struct slot *slot)
572 struct controller *ctrl = slot->ctrl;
577 cmd_mask = PWR_LED_CTRL;
578 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
579 dbg("%s: SLOTCTRL %x write cmd %x\n",
580 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
583 static void hpc_set_green_led_off(struct slot *slot)
585 struct controller *ctrl = slot->ctrl;
590 cmd_mask = PWR_LED_CTRL;
591 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
592 dbg("%s: SLOTCTRL %x write cmd %x\n",
593 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
596 static void hpc_set_green_led_blink(struct slot *slot)
598 struct controller *ctrl = slot->ctrl;
603 cmd_mask = PWR_LED_CTRL;
604 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
605 dbg("%s: SLOTCTRL %x write cmd %x\n",
606 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
609 static void hpc_release_ctlr(struct controller *ctrl)
611 /* Mask Hot-plug Interrupt Enable */
612 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE))
613 err("%s: Cannot mask hotplut interrupt enable\n", __func__);
615 /* Free interrupt handler or interrupt polling timer */
616 pciehp_free_irq(ctrl);
619 * If this is the last controller to be released, destroy the
622 if (atomic_dec_and_test(&pciehp_num_controllers))
623 destroy_workqueue(pciehp_wq);
626 static int hpc_power_on_slot(struct slot * slot)
628 struct controller *ctrl = slot->ctrl;
634 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
636 /* Clear sticky power-fault bit from previous power failures */
637 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
639 err("%s: Cannot read SLOTSTATUS register\n", __func__);
642 slot_status &= PWR_FAULT_DETECTED;
644 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
646 err("%s: Cannot write to SLOTSTATUS register\n",
654 /* Enable detection that we turned off at slot power-off time */
655 if (!pciehp_poll_mode) {
656 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
658 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
662 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
665 err("%s: Write %x command failed!\n", __func__, slot_cmd);
668 dbg("%s: SLOTCTRL %x write cmd %x\n",
669 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
674 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
676 struct pci_dev *dev = ctrl->pci_dev;
680 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
683 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
684 if (reg & PCI_ERR_COR_BAD_DLLP)
686 reg |= PCI_ERR_COR_BAD_DLLP;
687 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
691 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
693 struct pci_dev *dev = ctrl->pci_dev;
697 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
700 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
701 if (!(reg & PCI_ERR_COR_BAD_DLLP))
703 reg &= ~PCI_ERR_COR_BAD_DLLP;
704 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
707 static int hpc_power_off_slot(struct slot * slot)
709 struct controller *ctrl = slot->ctrl;
715 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
718 * Set Bad DLLP Mask bit in Correctable Error Mask
719 * Register. This is the workaround against Bad DLLP error
720 * that sometimes happens during turning power off the slot
721 * which conforms to PCI Express 1.0a spec.
723 changed = pcie_mask_bad_dllp(ctrl);
725 slot_cmd = POWER_OFF;
728 * If we get MRL or presence detect interrupts now, the isr
729 * will notice the sticky power-fault bit too and issue power
730 * indicator change commands. This will lead to an endless loop
731 * of command completions, since the power-fault bit remains on
732 * till the slot is powered on again.
734 if (!pciehp_poll_mode) {
735 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
737 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
741 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
743 err("%s: Write command failed!\n", __func__);
747 dbg("%s: SLOTCTRL %x write cmd %x\n",
748 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
751 pcie_unmask_bad_dllp(ctrl);
756 static irqreturn_t pcie_isr(int irq, void *dev_id)
758 struct controller *ctrl = (struct controller *)dev_id;
759 u16 detected, intr_loc;
763 * In order to guarantee that all interrupt events are
764 * serviced, we need to re-inspect Slot Status register after
765 * clearing what is presumed to be the last pending interrupt.
769 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
770 err("%s: Cannot read SLOTSTATUS\n", __func__);
774 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
775 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
777 intr_loc |= detected;
780 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
781 err("%s: Cannot write to SLOTSTATUS\n", __func__);
786 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
788 /* Check Command Complete Interrupt Pending */
789 if (intr_loc & CMD_COMPLETED) {
792 wake_up(&ctrl->queue);
795 if (!(intr_loc & ~CMD_COMPLETED))
799 * Return without handling events if this handler routine is
800 * called before controller initialization is done. This may
801 * happen if hotplug event or another interrupt that shares
802 * the IRQ with pciehp arrives before slot initialization is
803 * done after interrupt handler is registered.
805 * FIXME - Need more structural fixes. We need to be ready to
806 * handle the event before installing interrupt handler.
808 p_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
809 if (!p_slot || !p_slot->hpc_ops)
812 /* Check MRL Sensor Changed */
813 if (intr_loc & MRL_SENS_CHANGED)
814 pciehp_handle_switch_change(p_slot);
816 /* Check Attention Button Pressed */
817 if (intr_loc & ATTN_BUTTN_PRESSED)
818 pciehp_handle_attention_button(p_slot);
820 /* Check Presence Detect Changed */
821 if (intr_loc & PRSN_DETECT_CHANGED)
822 pciehp_handle_presence_change(p_slot);
824 /* Check Power Fault Detected */
825 if (intr_loc & PWR_FAULT_DETECTED)
826 pciehp_handle_power_fault(p_slot);
831 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
833 struct controller *ctrl = slot->ctrl;
834 enum pcie_link_speed lnk_speed;
838 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
840 err("%s: Cannot read LNKCAP register\n", __func__);
844 switch (lnk_cap & 0x000F) {
846 lnk_speed = PCIE_2PT5GB;
849 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
854 dbg("Max link speed = %d\n", lnk_speed);
859 static int hpc_get_max_lnk_width(struct slot *slot,
860 enum pcie_link_width *value)
862 struct controller *ctrl = slot->ctrl;
863 enum pcie_link_width lnk_wdth;
867 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
869 err("%s: Cannot read LNKCAP register\n", __func__);
873 switch ((lnk_cap & 0x03F0) >> 4){
875 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
878 lnk_wdth = PCIE_LNK_X1;
881 lnk_wdth = PCIE_LNK_X2;
884 lnk_wdth = PCIE_LNK_X4;
887 lnk_wdth = PCIE_LNK_X8;
890 lnk_wdth = PCIE_LNK_X12;
893 lnk_wdth = PCIE_LNK_X16;
896 lnk_wdth = PCIE_LNK_X32;
899 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
904 dbg("Max link width = %d\n", lnk_wdth);
909 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
911 struct controller *ctrl = slot->ctrl;
912 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
916 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
918 err("%s: Cannot read LNKSTATUS register\n", __func__);
922 switch (lnk_status & 0x0F) {
924 lnk_speed = PCIE_2PT5GB;
927 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
932 dbg("Current link speed = %d\n", lnk_speed);
937 static int hpc_get_cur_lnk_width(struct slot *slot,
938 enum pcie_link_width *value)
940 struct controller *ctrl = slot->ctrl;
941 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
945 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
947 err("%s: Cannot read LNKSTATUS register\n", __func__);
951 switch ((lnk_status & 0x03F0) >> 4){
953 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
956 lnk_wdth = PCIE_LNK_X1;
959 lnk_wdth = PCIE_LNK_X2;
962 lnk_wdth = PCIE_LNK_X4;
965 lnk_wdth = PCIE_LNK_X8;
968 lnk_wdth = PCIE_LNK_X12;
971 lnk_wdth = PCIE_LNK_X16;
974 lnk_wdth = PCIE_LNK_X32;
977 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
982 dbg("Current link width = %d\n", lnk_wdth);
987 static struct hpc_ops pciehp_hpc_ops = {
988 .power_on_slot = hpc_power_on_slot,
989 .power_off_slot = hpc_power_off_slot,
990 .set_attention_status = hpc_set_attention_status,
991 .get_power_status = hpc_get_power_status,
992 .get_attention_status = hpc_get_attention_status,
993 .get_latch_status = hpc_get_latch_status,
994 .get_adapter_status = hpc_get_adapter_status,
995 .get_emi_status = hpc_get_emi_status,
996 .toggle_emi = hpc_toggle_emi,
998 .get_max_bus_speed = hpc_get_max_lnk_speed,
999 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1000 .get_max_lnk_width = hpc_get_max_lnk_width,
1001 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1003 .query_power_fault = hpc_query_power_fault,
1004 .green_led_on = hpc_set_green_led_on,
1005 .green_led_off = hpc_set_green_led_off,
1006 .green_led_blink = hpc_set_green_led_blink,
1008 .release_ctlr = hpc_release_ctlr,
1009 .check_lnk_status = hpc_check_lnk_status,
1013 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1016 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1017 struct pci_dev *pdev = dev;
1018 struct pci_bus *parent;
1019 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1022 * Per PCI firmware specification, we should run the ACPI _OSC
1023 * method to get control of hotplug hardware before using it.
1024 * If an _OSC is missing, we look for an OSHP to do the same thing.
1025 * To handle different BIOS behavior, we look for _OSC and OSHP
1026 * within the scope of the hotplug controller and its parents, upto
1027 * the host bridge under which this controller exists.
1031 * This hotplug controller was not listed in the ACPI name
1032 * space at all. Try to get acpi handle of parent pci bus.
1034 if (!pdev || !pdev->bus->parent)
1036 parent = pdev->bus->parent;
1037 dbg("Could not find %s in acpi namespace, trying parent\n",
1040 /* Parent must be a host bridge */
1041 handle = acpi_get_pci_rootbridge_handle(
1042 pci_domain_nr(parent),
1045 handle = DEVICE_ACPI_HANDLE(
1046 &(parent->self->dev));
1047 pdev = parent->self;
1051 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1052 dbg("Trying to get hotplug control for %s \n",
1053 (char *)string.pointer);
1054 status = pci_osc_control_set(handle,
1055 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1056 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1057 if (status == AE_NOT_FOUND)
1058 status = acpi_run_oshp(handle);
1059 if (ACPI_SUCCESS(status)) {
1060 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1061 pci_name(dev), (char *)string.pointer);
1062 kfree(string.pointer);
1065 if (acpi_root_bridge(handle))
1068 status = acpi_get_parent(chandle, &handle);
1069 if (ACPI_FAILURE(status))
1073 dbg("Cannot get control of hotplug hardware for pci %s\n",
1076 kfree(string.pointer);
1081 static int pcie_init_hardware_part1(struct controller *ctrl,
1082 struct pcie_device *dev)
1084 /* Clear all remaining event bits in Slot Status register */
1085 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1086 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1090 /* Mask Hot-plug Interrupt Enable */
1091 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1092 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1098 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1102 cmd = PRSN_DETECT_ENABLE;
1103 if (ATTN_BUTTN(ctrl))
1104 cmd |= ATTN_BUTTN_ENABLE;
1105 if (POWER_CTRL(ctrl))
1106 cmd |= PWR_FAULT_DETECT_ENABLE;
1108 cmd |= MRL_DETECT_ENABLE;
1109 if (!pciehp_poll_mode)
1110 cmd |= HP_INTR_ENABLE;
1112 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1113 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1115 if (pcie_write_cmd(ctrl, cmd, mask)) {
1116 err("%s: Cannot enable software notification\n", __func__);
1123 static inline void dbg_ctrl(struct controller *ctrl)
1127 struct pci_dev *pdev = ctrl->pci_dev;
1132 dbg("Hotplug Controller:\n");
1133 dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
1134 dbg(" Vendor ID : 0x%04x\n", pdev->vendor);
1135 dbg(" Device ID : 0x%04x\n", pdev->device);
1136 dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device);
1137 dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor);
1138 dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
1139 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1140 if (!pci_resource_len(pdev, i))
1142 dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i,
1143 (unsigned long long)pci_resource_len(pdev, i),
1144 (unsigned long long)pci_resource_start(pdev, i));
1146 dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
1147 dbg(" Physical Slot Number : %d\n", ctrl->first_slot);
1148 dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
1149 dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
1150 dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no");
1151 dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no");
1152 dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no");
1153 dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
1154 dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no");
1155 dbg(" Comamnd Completed : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
1156 pciehp_readw(ctrl, SLOTSTATUS, ®16);
1157 dbg("Slot Status : 0x%04x\n", reg16);
1158 pciehp_readw(ctrl, SLOTSTATUS, ®16);
1159 dbg("Slot Control : 0x%04x\n", reg16);
1162 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1165 struct pci_dev *pdev = dev->port;
1167 ctrl->pci_dev = pdev;
1168 ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1169 if (!ctrl->cap_base) {
1170 err("%s: Cannot find PCI Express capability\n", __func__);
1173 if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
1174 err("%s: Cannot read SLOTCAP register\n", __func__);
1178 ctrl->slot_cap = slot_cap;
1179 ctrl->first_slot = slot_cap >> 19;
1180 ctrl->slot_device_offset = 0;
1181 ctrl->num_slots = 1;
1182 ctrl->hpc_ops = &pciehp_hpc_ops;
1183 mutex_init(&ctrl->crit_sect);
1184 mutex_init(&ctrl->ctrl_lock);
1185 init_waitqueue_head(&ctrl->queue);
1188 * Controller doesn't notify of command completion if the "No
1189 * Command Completed Support" bit is set in Slot Capability
1190 * register or the controller supports none of power
1191 * controller, attention led, power led and EMI.
1193 if (NO_CMD_CMPL(ctrl) ||
1194 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
1195 ctrl->no_cmd_complete = 1;
1197 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1198 pdev->vendor, pdev->device,
1199 pdev->subsystem_vendor, pdev->subsystem_device);
1201 if (pcie_init_hardware_part1(ctrl, dev))
1204 if (pciehp_request_irq(ctrl))
1208 * If this is the first controller to be initialized,
1209 * initialize the pciehp work queue
1211 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1212 pciehp_wq = create_singlethread_workqueue("pciehpd");
1214 goto abort_free_irq;
1218 if (pcie_init_hardware_part2(ctrl, dev))
1219 goto abort_free_irq;
1224 pciehp_free_irq(ctrl);