2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/string.h>
20 #include <linux/log2.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24 unsigned int pci_pm_d3_delay = 10;
26 #define DEFAULT_CARDBUS_IO_SIZE (256)
27 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
28 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
29 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
30 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
33 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
34 * @bus: pointer to PCI bus structure to search
36 * Given a PCI bus, returns the highest PCI bus number present in the set
37 * including the given PCI bus and its list of child PCI buses.
39 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
41 struct list_head *tmp;
44 max = bus->subordinate;
45 list_for_each(tmp, &bus->children) {
46 n = pci_bus_max_busnr(pci_bus_b(tmp));
52 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
56 * pci_max_busnr - returns maximum PCI bus number
58 * Returns the highest PCI bus number present in the system global list of
61 unsigned char __devinit
64 struct pci_bus *bus = NULL;
68 while ((bus = pci_find_next_bus(bus)) != NULL) {
69 n = pci_bus_max_busnr(bus);
78 #define PCI_FIND_CAP_TTL 48
80 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
81 u8 pos, int cap, int *ttl)
86 pci_bus_read_config_byte(bus, devfn, pos, &pos);
90 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
96 pos += PCI_CAP_LIST_NEXT;
101 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
104 int ttl = PCI_FIND_CAP_TTL;
106 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
109 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
111 return __pci_find_next_cap(dev->bus, dev->devfn,
112 pos + PCI_CAP_LIST_NEXT, cap);
114 EXPORT_SYMBOL_GPL(pci_find_next_capability);
116 static int __pci_bus_find_cap_start(struct pci_bus *bus,
117 unsigned int devfn, u8 hdr_type)
121 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
122 if (!(status & PCI_STATUS_CAP_LIST))
126 case PCI_HEADER_TYPE_NORMAL:
127 case PCI_HEADER_TYPE_BRIDGE:
128 return PCI_CAPABILITY_LIST;
129 case PCI_HEADER_TYPE_CARDBUS:
130 return PCI_CB_CAPABILITY_LIST;
139 * pci_find_capability - query for devices' capabilities
140 * @dev: PCI device to query
141 * @cap: capability code
143 * Tell if a device supports a given PCI capability.
144 * Returns the address of the requested capability structure within the
145 * device's PCI configuration space or 0 in case the device does not
146 * support it. Possible values for @cap:
148 * %PCI_CAP_ID_PM Power Management
149 * %PCI_CAP_ID_AGP Accelerated Graphics Port
150 * %PCI_CAP_ID_VPD Vital Product Data
151 * %PCI_CAP_ID_SLOTID Slot Identification
152 * %PCI_CAP_ID_MSI Message Signalled Interrupts
153 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
154 * %PCI_CAP_ID_PCIX PCI-X
155 * %PCI_CAP_ID_EXP PCI Express
157 int pci_find_capability(struct pci_dev *dev, int cap)
161 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
163 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
169 * pci_bus_find_capability - query for devices' capabilities
170 * @bus: the PCI bus to query
171 * @devfn: PCI device to query
172 * @cap: capability code
174 * Like pci_find_capability() but works for pci devices that do not have a
175 * pci_dev structure set up yet.
177 * Returns the address of the requested capability structure within the
178 * device's PCI configuration space or 0 in case the device does not
181 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
186 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
188 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
190 pos = __pci_find_next_cap(bus, devfn, pos, cap);
196 * pci_find_ext_capability - Find an extended capability
197 * @dev: PCI device to query
198 * @cap: capability code
200 * Returns the address of the requested extended capability structure
201 * within the device's PCI configuration space or 0 if the device does
202 * not support it. Possible values for @cap:
204 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
205 * %PCI_EXT_CAP_ID_VC Virtual Channel
206 * %PCI_EXT_CAP_ID_DSN Device Serial Number
207 * %PCI_EXT_CAP_ID_PWR Power Budgeting
209 int pci_find_ext_capability(struct pci_dev *dev, int cap)
212 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
215 if (dev->cfg_size <= 256)
218 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
222 * If we have no capabilities, this is indicated by cap ID,
223 * cap version and next pointer all being 0.
229 if (PCI_EXT_CAP_ID(header) == cap)
232 pos = PCI_EXT_CAP_NEXT(header);
236 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
242 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
244 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
246 int rc, ttl = PCI_FIND_CAP_TTL;
249 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
250 mask = HT_3BIT_CAP_MASK;
252 mask = HT_5BIT_CAP_MASK;
254 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
255 PCI_CAP_ID_HT, &ttl);
257 rc = pci_read_config_byte(dev, pos + 3, &cap);
258 if (rc != PCIBIOS_SUCCESSFUL)
261 if ((cap & mask) == ht_cap)
264 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
265 pos + PCI_CAP_LIST_NEXT,
266 PCI_CAP_ID_HT, &ttl);
272 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
273 * @dev: PCI device to query
274 * @pos: Position from which to continue searching
275 * @ht_cap: Hypertransport capability code
277 * To be used in conjunction with pci_find_ht_capability() to search for
278 * all capabilities matching @ht_cap. @pos should always be a value returned
279 * from pci_find_ht_capability().
281 * NB. To be 100% safe against broken PCI devices, the caller should take
282 * steps to avoid an infinite loop.
284 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
286 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
288 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
291 * pci_find_ht_capability - query a device's Hypertransport capabilities
292 * @dev: PCI device to query
293 * @ht_cap: Hypertransport capability code
295 * Tell if a device supports a given Hypertransport capability.
296 * Returns an address within the device's PCI configuration space
297 * or 0 in case the device does not support the request capability.
298 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
299 * which has a Hypertransport capability matching @ht_cap.
301 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
305 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
307 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
311 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
314 * pci_find_parent_resource - return resource region of parent bus of given region
315 * @dev: PCI device structure contains resources to be searched
316 * @res: child resource record for which parent is sought
318 * For given resource region of given device, return the resource
319 * region of parent bus the given region is contained in or where
320 * it should be allocated from.
323 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
325 const struct pci_bus *bus = dev->bus;
327 struct resource *best = NULL;
329 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
330 struct resource *r = bus->resource[i];
333 if (res->start && !(res->start >= r->start && res->end <= r->end))
334 continue; /* Not contained */
335 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
336 continue; /* Wrong type */
337 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
338 return r; /* Exact match */
339 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
340 best = r; /* Approximating prefetchable by non-prefetchable */
346 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
347 * @dev: PCI device to have its BARs restored
349 * Restore the BAR values for a given device, so as to make it
350 * accessible by its driver.
353 pci_restore_bars(struct pci_dev *dev)
357 switch (dev->hdr_type) {
358 case PCI_HEADER_TYPE_NORMAL:
361 case PCI_HEADER_TYPE_BRIDGE:
364 case PCI_HEADER_TYPE_CARDBUS:
368 /* Should never get here, but just in case... */
372 for (i = 0; i < numres; i ++)
373 pci_update_resource(dev, &dev->resource[i], i);
376 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
379 * pci_set_power_state - Set the power state of a PCI device
380 * @dev: PCI device to be suspended
381 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
383 * Transition a device to a new power state, using the Power Management
384 * Capabilities in the device's config space.
387 * -EINVAL if trying to enter a lower state than we're already in.
388 * 0 if we're already in the requested state.
389 * -EIO if device does not support PCI PM.
390 * 0 if we can successfully change the power state.
393 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
395 int pm, need_restore = 0;
398 /* bound the state we're entering */
399 if (state > PCI_D3hot)
403 * If the device or the parent bridge can't support PCI PM, ignore
404 * the request if we're doing anything besides putting it into D0
405 * (which would only happen on boot).
407 if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
410 /* find PCI PM capability in list */
411 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
413 /* abort if the device doesn't support PM capabilities */
417 /* Validate current state:
418 * Can enter D0 from any state, but if we can only go deeper
419 * to sleep if we're already in a low power state
421 if (state != PCI_D0 && dev->current_state > state) {
422 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
423 __FUNCTION__, pci_name(dev), state, dev->current_state);
425 } else if (dev->current_state == state)
426 return 0; /* we're already there */
429 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
430 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
432 "PCI: %s has unsupported PM cap regs version (%u)\n",
433 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
437 /* check if this device supports the desired state */
438 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
440 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
443 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
445 /* If we're (effectively) in D3, force entire word to 0.
446 * This doesn't affect PME_Status, disables PME_En, and
447 * sets PowerState to 0.
449 switch (dev->current_state) {
453 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
456 case PCI_UNKNOWN: /* Boot-up */
457 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
458 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
460 /* Fall-through: force to D0 */
466 /* enter specified state */
467 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
469 /* Mandatory power management transition delays */
470 /* see PCI PM 1.1 5.6.1 table 18 */
471 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
472 msleep(pci_pm_d3_delay);
473 else if (state == PCI_D2 || dev->current_state == PCI_D2)
477 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
478 * Firmware method after native method ?
480 if (platform_pci_set_power_state)
481 platform_pci_set_power_state(dev, state);
483 dev->current_state = state;
485 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
486 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
487 * from D3hot to D0 _may_ perform an internal reset, thereby
488 * going to "D0 Uninitialized" rather than "D0 Initialized".
489 * For example, at least some versions of the 3c905B and the
490 * 3c556B exhibit this behaviour.
492 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
493 * devices in a D3hot state at boot. Consequently, we need to
494 * restore at least the BARs so that the device will be
495 * accessible to its driver.
498 pci_restore_bars(dev);
503 pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
506 * pci_choose_state - Choose the power state of a PCI device
507 * @dev: PCI device to be suspended
508 * @state: target sleep state for the whole system. This is the value
509 * that is passed to suspend() function.
511 * Returns PCI power state suitable for given device and given system
515 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
519 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
522 if (platform_pci_choose_state) {
523 ret = platform_pci_choose_state(dev, state);
524 if (ret != PCI_POWER_ERROR)
528 switch (state.event) {
531 case PM_EVENT_FREEZE:
532 case PM_EVENT_PRETHAW:
533 /* REVISIT both freeze and pre-thaw "should" use D0 */
534 case PM_EVENT_SUSPEND:
537 printk("Unrecognized suspend event %d\n", state.event);
543 EXPORT_SYMBOL(pci_choose_state);
545 static int pci_save_pcie_state(struct pci_dev *dev)
548 struct pci_cap_saved_state *save_state;
551 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
555 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
557 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
559 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
562 cap = (u16 *)&save_state->data[0];
564 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
565 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
566 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
567 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
568 pci_add_saved_cap(dev, save_state);
572 static void pci_restore_pcie_state(struct pci_dev *dev)
575 struct pci_cap_saved_state *save_state;
578 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
579 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
580 if (!save_state || pos <= 0)
582 cap = (u16 *)&save_state->data[0];
584 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
585 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
586 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
587 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
591 static int pci_save_pcix_state(struct pci_dev *dev)
594 struct pci_cap_saved_state *save_state;
597 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
601 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
603 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
605 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
608 cap = (u16 *)&save_state->data[0];
610 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
611 pci_add_saved_cap(dev, save_state);
615 static void pci_restore_pcix_state(struct pci_dev *dev)
618 struct pci_cap_saved_state *save_state;
621 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
622 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
623 if (!save_state || pos <= 0)
625 cap = (u16 *)&save_state->data[0];
627 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
632 * pci_save_state - save the PCI configuration space of a device before suspending
633 * @dev: - PCI device that we're dealing with
636 pci_save_state(struct pci_dev *dev)
639 /* XXX: 100% dword access ok here? */
640 for (i = 0; i < 16; i++)
641 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
642 if ((i = pci_save_pcie_state(dev)) != 0)
644 if ((i = pci_save_pcix_state(dev)) != 0)
650 * pci_restore_state - Restore the saved state of a PCI device
651 * @dev: - PCI device that we're dealing with
654 pci_restore_state(struct pci_dev *dev)
659 /* PCI Express register must be restored first */
660 pci_restore_pcie_state(dev);
663 * The Base Address register should be programmed before the command
666 for (i = 15; i >= 0; i--) {
667 pci_read_config_dword(dev, i * 4, &val);
668 if (val != dev->saved_config_space[i]) {
669 printk(KERN_DEBUG "PM: Writing back config space on "
670 "device %s at offset %x (was %x, writing %x)\n",
672 val, (int)dev->saved_config_space[i]);
673 pci_write_config_dword(dev,i * 4,
674 dev->saved_config_space[i]);
677 pci_restore_pcix_state(dev);
678 pci_restore_msi_state(dev);
683 static int do_pci_enable_device(struct pci_dev *dev, int bars)
687 err = pci_set_power_state(dev, PCI_D0);
688 if (err < 0 && err != -EIO)
690 err = pcibios_enable_device(dev, bars);
693 pci_fixup_device(pci_fixup_enable, dev);
699 * pci_reenable_device - Resume abandoned device
700 * @dev: PCI device to be resumed
702 * Note this function is a backend of pci_default_resume and is not supposed
703 * to be called by normal code, write proper resume handler and use it instead.
705 int pci_reenable_device(struct pci_dev *dev)
707 if (atomic_read(&dev->enable_cnt))
708 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
713 * pci_enable_device_bars - Initialize some of a device for use
714 * @dev: PCI device to be initialized
715 * @bars: bitmask of BAR's that must be configured
717 * Initialize device before it's used by a driver. Ask low-level code
718 * to enable selected I/O and memory resources. Wake up the device if it
719 * was suspended. Beware, this function can fail.
722 pci_enable_device_bars(struct pci_dev *dev, int bars)
726 if (atomic_add_return(1, &dev->enable_cnt) > 1)
727 return 0; /* already enabled */
729 err = do_pci_enable_device(dev, bars);
731 atomic_dec(&dev->enable_cnt);
736 * pci_enable_device - Initialize device before it's used by a driver.
737 * @dev: PCI device to be initialized
739 * Initialize device before it's used by a driver. Ask low-level code
740 * to enable I/O and memory. Wake up the device if it was suspended.
741 * Beware, this function can fail.
743 * Note we don't actually enable the device many times if we call
744 * this function repeatedly (we just increment the count).
746 int pci_enable_device(struct pci_dev *dev)
748 return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
752 * Managed PCI resources. This manages device on/off, intx/msi/msix
753 * on/off and BAR regions. pci_dev itself records msi/msix status, so
754 * there's no need to track it separately. pci_devres is initialized
755 * when a device is enabled using managed PCI device enable interface.
758 unsigned int enabled:1;
759 unsigned int pinned:1;
760 unsigned int orig_intx:1;
761 unsigned int restore_intx:1;
765 static void pcim_release(struct device *gendev, void *res)
767 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
768 struct pci_devres *this = res;
771 if (dev->msi_enabled)
772 pci_disable_msi(dev);
773 if (dev->msix_enabled)
774 pci_disable_msix(dev);
776 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
777 if (this->region_mask & (1 << i))
778 pci_release_region(dev, i);
780 if (this->restore_intx)
781 pci_intx(dev, this->orig_intx);
783 if (this->enabled && !this->pinned)
784 pci_disable_device(dev);
787 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
789 struct pci_devres *dr, *new_dr;
791 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
795 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
798 return devres_get(&pdev->dev, new_dr, NULL, NULL);
801 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
803 if (pci_is_managed(pdev))
804 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
809 * pcim_enable_device - Managed pci_enable_device()
810 * @pdev: PCI device to be initialized
812 * Managed pci_enable_device().
814 int pcim_enable_device(struct pci_dev *pdev)
816 struct pci_devres *dr;
819 dr = get_pci_dr(pdev);
822 WARN_ON(!!dr->enabled);
824 rc = pci_enable_device(pdev);
826 pdev->is_managed = 1;
833 * pcim_pin_device - Pin managed PCI device
834 * @pdev: PCI device to pin
836 * Pin managed PCI device @pdev. Pinned device won't be disabled on
837 * driver detach. @pdev must have been enabled with
838 * pcim_enable_device().
840 void pcim_pin_device(struct pci_dev *pdev)
842 struct pci_devres *dr;
844 dr = find_pci_dr(pdev);
845 WARN_ON(!dr || !dr->enabled);
851 * pcibios_disable_device - disable arch specific PCI resources for device dev
852 * @dev: the PCI device to disable
854 * Disables architecture specific PCI resources for the device. This
855 * is the default implementation. Architecture implementations can
858 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
861 * pci_disable_device - Disable PCI device after use
862 * @dev: PCI device to be disabled
864 * Signal to the system that the PCI device is not in use by the system
865 * anymore. This only involves disabling PCI bus-mastering, if active.
867 * Note we don't actually disable the device until all callers of
868 * pci_device_enable() have called pci_device_disable().
871 pci_disable_device(struct pci_dev *dev)
873 struct pci_devres *dr;
876 dr = find_pci_dr(dev);
880 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
883 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
884 if (pci_command & PCI_COMMAND_MASTER) {
885 pci_command &= ~PCI_COMMAND_MASTER;
886 pci_write_config_word(dev, PCI_COMMAND, pci_command);
888 dev->is_busmaster = 0;
890 pcibios_disable_device(dev);
894 * pcibios_set_pcie_reset_state - set reset state for device dev
895 * @dev: the PCI-E device reset
896 * @state: Reset state to enter into
899 * Sets the PCI-E reset state for the device. This is the default
900 * implementation. Architecture implementations can override this.
902 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
903 enum pcie_reset_state state)
909 * pci_set_pcie_reset_state - set reset state for device dev
910 * @dev: the PCI-E device reset
911 * @state: Reset state to enter into
914 * Sets the PCI reset state for the device.
916 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
918 return pcibios_set_pcie_reset_state(dev, state);
922 * pci_enable_wake - enable PCI device as wakeup event source
923 * @dev: PCI device affected
924 * @state: PCI state from which device will issue wakeup events
925 * @enable: True to enable event generation; false to disable
927 * This enables the device as a wakeup event source, or disables it.
928 * When such events involves platform-specific hooks, those hooks are
929 * called automatically by this routine.
931 * Devices with legacy power management (no standard PCI PM capabilities)
932 * always require such platform hooks. Depending on the platform, devices
933 * supporting the standard PCI PME# signal may require such platform hooks;
934 * they always update bits in config space to allow PME# generation.
936 * -EIO is returned if the device can't ever be a wakeup event source.
937 * -EINVAL is returned if the device can't generate wakeup events from
938 * the specified PCI state. Returns zero if the operation is successful.
940 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
946 /* Note that drivers should verify device_may_wakeup(&dev->dev)
947 * before calling this function. Platform code should report
948 * errors when drivers try to enable wakeup on devices that
949 * can't issue wakeups, or on which wakeups were disabled by
950 * userspace updating the /sys/devices.../power/wakeup file.
953 status = call_platform_enable_wakeup(&dev->dev, enable);
955 /* find PCI PM capability in list */
956 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
958 /* If device doesn't support PM Capabilities, but caller wants to
959 * disable wake events, it's a NOP. Otherwise fail unless the
960 * platform hooks handled this legacy device already.
963 return enable ? status : 0;
965 /* Check device's ability to generate PME# */
966 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
968 value &= PCI_PM_CAP_PME_MASK;
969 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
971 /* Check if it can generate PME# from requested state. */
972 if (!value || !(value & (1 << state))) {
973 /* if it can't, revert what the platform hook changed,
974 * always reporting the base "EINVAL, can't PME#" error
977 call_platform_enable_wakeup(&dev->dev, 0);
978 return enable ? -EINVAL : 0;
981 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
983 /* Clear PME_Status by writing 1 to it and enable PME# */
984 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
987 value &= ~PCI_PM_CTRL_PME_ENABLE;
989 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
995 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1003 while (dev->bus->self) {
1004 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1005 dev = dev->bus->self;
1012 * pci_release_region - Release a PCI bar
1013 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1014 * @bar: BAR to release
1016 * Releases the PCI I/O and memory resources previously reserved by a
1017 * successful call to pci_request_region. Call this function only
1018 * after all use of the PCI regions has ceased.
1020 void pci_release_region(struct pci_dev *pdev, int bar)
1022 struct pci_devres *dr;
1024 if (pci_resource_len(pdev, bar) == 0)
1026 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1027 release_region(pci_resource_start(pdev, bar),
1028 pci_resource_len(pdev, bar));
1029 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1030 release_mem_region(pci_resource_start(pdev, bar),
1031 pci_resource_len(pdev, bar));
1033 dr = find_pci_dr(pdev);
1035 dr->region_mask &= ~(1 << bar);
1039 * pci_request_region - Reserved PCI I/O and memory resource
1040 * @pdev: PCI device whose resources are to be reserved
1041 * @bar: BAR to be reserved
1042 * @res_name: Name to be associated with resource.
1044 * Mark the PCI region associated with PCI device @pdev BR @bar as
1045 * being reserved by owner @res_name. Do not access any
1046 * address inside the PCI regions unless this call returns
1049 * Returns 0 on success, or %EBUSY on error. A warning
1050 * message is also printed on failure.
1052 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1054 struct pci_devres *dr;
1056 if (pci_resource_len(pdev, bar) == 0)
1059 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1060 if (!request_region(pci_resource_start(pdev, bar),
1061 pci_resource_len(pdev, bar), res_name))
1064 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1065 if (!request_mem_region(pci_resource_start(pdev, bar),
1066 pci_resource_len(pdev, bar), res_name))
1070 dr = find_pci_dr(pdev);
1072 dr->region_mask |= 1 << bar;
1077 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%llx@%llx "
1079 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
1080 bar + 1, /* PCI BAR # */
1081 (unsigned long long)pci_resource_len(pdev, bar),
1082 (unsigned long long)pci_resource_start(pdev, bar),
1088 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1089 * @pdev: PCI device whose resources were previously reserved
1090 * @bars: Bitmask of BARs to be released
1092 * Release selected PCI I/O and memory resources previously reserved.
1093 * Call this function only after all use of the PCI regions has ceased.
1095 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1099 for (i = 0; i < 6; i++)
1100 if (bars & (1 << i))
1101 pci_release_region(pdev, i);
1105 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1106 * @pdev: PCI device whose resources are to be reserved
1107 * @bars: Bitmask of BARs to be requested
1108 * @res_name: Name to be associated with resource
1110 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1111 const char *res_name)
1115 for (i = 0; i < 6; i++)
1116 if (bars & (1 << i))
1117 if(pci_request_region(pdev, i, res_name))
1123 if (bars & (1 << i))
1124 pci_release_region(pdev, i);
1130 * pci_release_regions - Release reserved PCI I/O and memory resources
1131 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1133 * Releases all PCI I/O and memory resources previously reserved by a
1134 * successful call to pci_request_regions. Call this function only
1135 * after all use of the PCI regions has ceased.
1138 void pci_release_regions(struct pci_dev *pdev)
1140 pci_release_selected_regions(pdev, (1 << 6) - 1);
1144 * pci_request_regions - Reserved PCI I/O and memory resources
1145 * @pdev: PCI device whose resources are to be reserved
1146 * @res_name: Name to be associated with resource.
1148 * Mark all PCI regions associated with PCI device @pdev as
1149 * being reserved by owner @res_name. Do not access any
1150 * address inside the PCI regions unless this call returns
1153 * Returns 0 on success, or %EBUSY on error. A warning
1154 * message is also printed on failure.
1156 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1158 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1162 * pci_set_master - enables bus-mastering for device dev
1163 * @dev: the PCI device to enable
1165 * Enables bus-mastering on the device and calls pcibios_set_master()
1166 * to do the needed arch specific settings.
1169 pci_set_master(struct pci_dev *dev)
1173 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1174 if (! (cmd & PCI_COMMAND_MASTER)) {
1175 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
1176 cmd |= PCI_COMMAND_MASTER;
1177 pci_write_config_word(dev, PCI_COMMAND, cmd);
1179 dev->is_busmaster = 1;
1180 pcibios_set_master(dev);
1183 #ifdef PCI_DISABLE_MWI
1184 int pci_set_mwi(struct pci_dev *dev)
1189 int pci_try_set_mwi(struct pci_dev *dev)
1194 void pci_clear_mwi(struct pci_dev *dev)
1200 #ifndef PCI_CACHE_LINE_BYTES
1201 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1204 /* This can be overridden by arch code. */
1205 /* Don't forget this is measured in 32-bit words, not bytes */
1206 u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1209 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1210 * @dev: the PCI device for which MWI is to be enabled
1212 * Helper function for pci_set_mwi.
1213 * Originally copied from drivers/net/acenic.c.
1214 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1216 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1219 pci_set_cacheline_size(struct pci_dev *dev)
1223 if (!pci_cache_line_size)
1224 return -EINVAL; /* The system doesn't support MWI. */
1226 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1227 equal to or multiple of the right value. */
1228 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1229 if (cacheline_size >= pci_cache_line_size &&
1230 (cacheline_size % pci_cache_line_size) == 0)
1233 /* Write the correct value. */
1234 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1236 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1237 if (cacheline_size == pci_cache_line_size)
1240 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
1241 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
1247 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1248 * @dev: the PCI device for which MWI is enabled
1250 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1252 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1255 pci_set_mwi(struct pci_dev *dev)
1260 rc = pci_set_cacheline_size(dev);
1264 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1265 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1266 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n",
1268 cmd |= PCI_COMMAND_INVALIDATE;
1269 pci_write_config_word(dev, PCI_COMMAND, cmd);
1276 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1277 * @dev: the PCI device for which MWI is enabled
1279 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1280 * Callers are not required to check the return value.
1282 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1284 int pci_try_set_mwi(struct pci_dev *dev)
1286 int rc = pci_set_mwi(dev);
1291 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1292 * @dev: the PCI device to disable
1294 * Disables PCI Memory-Write-Invalidate transaction on the device
1297 pci_clear_mwi(struct pci_dev *dev)
1301 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1302 if (cmd & PCI_COMMAND_INVALIDATE) {
1303 cmd &= ~PCI_COMMAND_INVALIDATE;
1304 pci_write_config_word(dev, PCI_COMMAND, cmd);
1307 #endif /* ! PCI_DISABLE_MWI */
1310 * pci_intx - enables/disables PCI INTx for device dev
1311 * @pdev: the PCI device to operate on
1312 * @enable: boolean: whether to enable or disable PCI INTx
1314 * Enables/disables PCI INTx for device dev
1317 pci_intx(struct pci_dev *pdev, int enable)
1319 u16 pci_command, new;
1321 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1324 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
1326 new = pci_command | PCI_COMMAND_INTX_DISABLE;
1329 if (new != pci_command) {
1330 struct pci_devres *dr;
1332 pci_write_config_word(pdev, PCI_COMMAND, new);
1334 dr = find_pci_dr(pdev);
1335 if (dr && !dr->restore_intx) {
1336 dr->restore_intx = 1;
1337 dr->orig_intx = !enable;
1343 * pci_msi_off - disables any msi or msix capabilities
1344 * @dev: the PCI device to operate on
1346 * If you want to use msi see pci_enable_msi and friends.
1347 * This is a lower level primitive that allows us to disable
1348 * msi operation at the device level.
1350 void pci_msi_off(struct pci_dev *dev)
1355 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
1357 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
1358 control &= ~PCI_MSI_FLAGS_ENABLE;
1359 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
1361 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1363 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
1364 control &= ~PCI_MSIX_FLAGS_ENABLE;
1365 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
1369 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1371 * These can be overridden by arch-specific implementations
1374 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1376 if (!pci_dma_supported(dev, mask))
1379 dev->dma_mask = mask;
1385 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1387 if (!pci_dma_supported(dev, mask))
1390 dev->dev.coherent_dma_mask = mask;
1397 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1398 * @dev: PCI device to query
1400 * Returns mmrbc: maximum designed memory read count in bytes
1401 * or appropriate error value.
1403 int pcix_get_max_mmrbc(struct pci_dev *dev)
1408 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1412 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1416 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
1418 EXPORT_SYMBOL(pcix_get_max_mmrbc);
1421 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1422 * @dev: PCI device to query
1424 * Returns mmrbc: maximum memory read count in bytes
1425 * or appropriate error value.
1427 int pcix_get_mmrbc(struct pci_dev *dev)
1432 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1436 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1438 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
1442 EXPORT_SYMBOL(pcix_get_mmrbc);
1445 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1446 * @dev: PCI device to query
1447 * @mmrbc: maximum memory read count in bytes
1448 * valid values are 512, 1024, 2048, 4096
1450 * If possible sets maximum memory read byte count, some bridges have erratas
1451 * that prevent this.
1453 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
1455 int cap, err = -EINVAL;
1456 u32 stat, cmd, v, o;
1458 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
1461 v = ffs(mmrbc) - 10;
1463 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1467 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
1471 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
1474 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
1478 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
1480 if (v > o && dev->bus &&
1481 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
1484 cmd &= ~PCI_X_CMD_MAX_READ;
1486 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
1491 EXPORT_SYMBOL(pcix_set_mmrbc);
1494 * pcie_get_readrq - get PCI Express read request size
1495 * @dev: PCI device to query
1497 * Returns maximum memory read request in bytes
1498 * or appropriate error value.
1500 int pcie_get_readrq(struct pci_dev *dev)
1505 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1509 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1511 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
1515 EXPORT_SYMBOL(pcie_get_readrq);
1518 * pcie_set_readrq - set PCI Express maximum memory read request
1519 * @dev: PCI device to query
1520 * @rq: maximum memory read count in bytes
1521 * valid values are 128, 256, 512, 1024, 2048, 4096
1523 * If possible sets maximum read byte count
1525 int pcie_set_readrq(struct pci_dev *dev, int rq)
1527 int cap, err = -EINVAL;
1530 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
1533 v = (ffs(rq) - 8) << 12;
1535 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
1539 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
1543 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
1544 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1546 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
1552 EXPORT_SYMBOL(pcie_set_readrq);
1555 * pci_select_bars - Make BAR mask from the type of resource
1556 * @dev: the PCI device for which BAR mask is made
1557 * @flags: resource type mask to be selected
1559 * This helper routine makes bar mask from the type of resource.
1561 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
1564 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1565 if (pci_resource_flags(dev, i) & flags)
1570 static int __devinit pci_init(void)
1572 struct pci_dev *dev = NULL;
1574 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1575 pci_fixup_device(pci_fixup_final, dev);
1580 static int __devinit pci_setup(char *str)
1583 char *k = strchr(str, ',');
1586 if (*str && (str = pcibios_setup(str)) && *str) {
1587 if (!strcmp(str, "nomsi")) {
1589 } else if (!strcmp(str, "noaer")) {
1591 } else if (!strncmp(str, "cbiosize=", 9)) {
1592 pci_cardbus_io_size = memparse(str + 9, &str);
1593 } else if (!strncmp(str, "cbmemsize=", 10)) {
1594 pci_cardbus_mem_size = memparse(str + 10, &str);
1596 printk(KERN_ERR "PCI: Unknown option `%s'\n",
1604 early_param("pci", pci_setup);
1606 device_initcall(pci_init);
1608 EXPORT_SYMBOL_GPL(pci_restore_bars);
1609 EXPORT_SYMBOL(pci_reenable_device);
1610 EXPORT_SYMBOL(pci_enable_device_bars);
1611 EXPORT_SYMBOL(pci_enable_device);
1612 EXPORT_SYMBOL(pcim_enable_device);
1613 EXPORT_SYMBOL(pcim_pin_device);
1614 EXPORT_SYMBOL(pci_disable_device);
1615 EXPORT_SYMBOL(pci_find_capability);
1616 EXPORT_SYMBOL(pci_bus_find_capability);
1617 EXPORT_SYMBOL(pci_release_regions);
1618 EXPORT_SYMBOL(pci_request_regions);
1619 EXPORT_SYMBOL(pci_release_region);
1620 EXPORT_SYMBOL(pci_request_region);
1621 EXPORT_SYMBOL(pci_release_selected_regions);
1622 EXPORT_SYMBOL(pci_request_selected_regions);
1623 EXPORT_SYMBOL(pci_set_master);
1624 EXPORT_SYMBOL(pci_set_mwi);
1625 EXPORT_SYMBOL(pci_try_set_mwi);
1626 EXPORT_SYMBOL(pci_clear_mwi);
1627 EXPORT_SYMBOL_GPL(pci_intx);
1628 EXPORT_SYMBOL(pci_set_dma_mask);
1629 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
1630 EXPORT_SYMBOL(pci_assign_resource);
1631 EXPORT_SYMBOL(pci_find_parent_resource);
1632 EXPORT_SYMBOL(pci_select_bars);
1634 EXPORT_SYMBOL(pci_set_power_state);
1635 EXPORT_SYMBOL(pci_save_state);
1636 EXPORT_SYMBOL(pci_restore_state);
1637 EXPORT_SYMBOL(pci_enable_wake);
1638 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);