2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
25 static int find_anything(struct device *dev, void *data)
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
35 int no_pci_devices(void)
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
45 EXPORT_SYMBOL(no_pci_devices);
47 #ifdef HAVE_PCI_LEGACY
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
56 * On error unwind, but don't propogate the error to the caller
57 * as it is ok to set up the PCI bus without these files.
59 static void pci_create_legacy_files(struct pci_bus *b)
63 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
68 b->legacy_io->attr.name = "legacy_io";
69 b->legacy_io->size = 0xffff;
70 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
71 b->legacy_io->read = pci_read_legacy_io;
72 b->legacy_io->write = pci_write_legacy_io;
73 error = device_create_bin_file(&b->dev, b->legacy_io);
77 /* Allocated above after the legacy_io struct */
78 b->legacy_mem = b->legacy_io + 1;
79 b->legacy_mem->attr.name = "legacy_mem";
80 b->legacy_mem->size = 1024*1024;
81 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
82 b->legacy_mem->mmap = pci_mmap_legacy_mem;
83 error = device_create_bin_file(&b->dev, b->legacy_mem);
90 device_remove_bin_file(&b->dev, b->legacy_io);
95 printk(KERN_WARNING "pci: warning: could not create legacy I/O port "
96 "and ISA memory resources to sysfs\n");
100 void pci_remove_legacy_files(struct pci_bus *b)
103 device_remove_bin_file(&b->dev, b->legacy_io);
104 device_remove_bin_file(&b->dev, b->legacy_mem);
105 kfree(b->legacy_io); /* both are allocated here */
108 #else /* !HAVE_PCI_LEGACY */
109 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
110 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
111 #endif /* HAVE_PCI_LEGACY */
114 * PCI Bus Class Devices
116 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
118 struct device_attribute *attr,
124 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
126 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
127 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
133 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
134 struct device_attribute *attr,
137 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
140 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
141 struct device_attribute *attr,
144 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
147 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
148 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
153 static void release_pcibus_dev(struct device *dev)
155 struct pci_bus *pci_bus = to_pci_bus(dev);
158 put_device(pci_bus->bridge);
162 static struct class pcibus_class = {
164 .dev_release = &release_pcibus_dev,
167 static int __init pcibus_class_init(void)
169 return class_register(&pcibus_class);
171 postcore_initcall(pcibus_class_init);
174 * Translate the low bits of the PCI base
175 * to the resource type
177 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
179 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
180 return IORESOURCE_IO;
182 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
183 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
185 return IORESOURCE_MEM;
188 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
190 u64 size = mask & maxbase; /* Find the significant bits */
194 /* Get the lowest of them to find the decode size, and
195 from that the extent. */
196 size = (size & ~(size-1)) - 1;
198 /* base == maxbase can be valid only if the BAR has
199 already been programmed with all 1s. */
200 if (base == maxbase && ((base | size) & mask) != mask)
207 pci_bar_unknown, /* Standard PCI BAR probe */
208 pci_bar_io, /* An io port BAR */
209 pci_bar_mem32, /* A 32-bit memory BAR */
210 pci_bar_mem64, /* A 64-bit memory BAR */
213 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
215 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
216 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
220 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
222 if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64)
223 return pci_bar_mem64;
224 return pci_bar_mem32;
228 * If the type is not unknown, we assume that the lowest bit is 'enable'.
229 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
231 static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
232 struct resource *res, unsigned int pos)
236 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
238 res->name = pci_name(dev);
240 pci_read_config_dword(dev, pos, &l);
241 pci_write_config_dword(dev, pos, mask);
242 pci_read_config_dword(dev, pos, &sz);
243 pci_write_config_dword(dev, pos, l);
246 * All bits set in sz means the device isn't working properly.
247 * If the BAR isn't implemented, all bits must be 0. If it's a
248 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
251 if (!sz || sz == 0xffffffff)
255 * I don't know how l can have all bits set. Copied from old code.
256 * Maybe it fixes a bug on some ancient platform.
261 if (type == pci_bar_unknown) {
262 type = decode_bar(res, l);
263 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
264 if (type == pci_bar_io) {
265 l &= PCI_BASE_ADDRESS_IO_MASK;
266 mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
268 l &= PCI_BASE_ADDRESS_MEM_MASK;
269 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
272 res->flags |= (l & IORESOURCE_ROM_ENABLE);
273 l &= PCI_ROM_ADDRESS_MASK;
274 mask = (u32)PCI_ROM_ADDRESS_MASK;
277 if (type == pci_bar_mem64) {
280 u64 mask64 = mask | (u64)~0 << 32;
282 pci_read_config_dword(dev, pos + 4, &l);
283 pci_write_config_dword(dev, pos + 4, ~0);
284 pci_read_config_dword(dev, pos + 4, &sz);
285 pci_write_config_dword(dev, pos + 4, l);
287 l64 |= ((u64)l << 32);
288 sz64 |= ((u64)sz << 32);
290 sz64 = pci_size(l64, sz64, mask64);
295 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
296 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
298 } else if ((sizeof(resource_size_t) < 8) && l) {
299 /* Address above 32-bit boundary; disable the BAR */
300 pci_write_config_dword(dev, pos, 0);
301 pci_write_config_dword(dev, pos + 4, 0);
306 res->end = l64 + sz64;
309 sz = pci_size(l, sz, mask);
319 return (type == pci_bar_mem64) ? 1 : 0;
325 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
327 unsigned int pos, reg;
329 for (pos = 0; pos < howmany; pos++) {
330 struct resource *res = &dev->resource[pos];
331 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
332 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
336 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
337 dev->rom_base_reg = rom;
338 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
339 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
340 IORESOURCE_SIZEALIGN;
341 __pci_read_base(dev, pci_bar_mem32, res, rom);
345 void __devinit pci_read_bridge_bases(struct pci_bus *child)
347 struct pci_dev *dev = child->self;
348 u8 io_base_lo, io_limit_lo;
349 u16 mem_base_lo, mem_limit_lo;
350 unsigned long base, limit;
351 struct resource *res;
354 if (!dev) /* It's a host bus, nothing to read */
357 if (dev->transparent) {
358 dev_info(&dev->dev, "transparent bridge\n");
359 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
360 child->resource[i] = child->parent->resource[i - 3];
364 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
366 res = child->resource[0];
367 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
368 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
369 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
370 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
372 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
373 u16 io_base_hi, io_limit_hi;
374 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
375 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
376 base |= (io_base_hi << 16);
377 limit |= (io_limit_hi << 16);
381 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
385 res->end = limit + 0xfff;
386 printk(KERN_INFO "PCI: bridge %s io port: [%llx, %llx]\n",
387 pci_name(dev), (unsigned long long) res->start,
388 (unsigned long long) res->end);
391 res = child->resource[1];
392 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
393 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
394 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
397 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
399 res->end = limit + 0xfffff;
400 printk(KERN_INFO "PCI: bridge %s 32bit mmio: [%llx, %llx]\n", pci_name(dev),
401 (unsigned long long) res->start, (unsigned long long) res->end);
404 res = child->resource[2];
405 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
406 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
407 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
408 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
410 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
411 u32 mem_base_hi, mem_limit_hi;
412 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
413 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
416 * Some bridges set the base > limit by default, and some
417 * (broken) BIOSes do not initialize them. If we find
418 * this, just assume they are not being used.
420 if (mem_base_hi <= mem_limit_hi) {
421 #if BITS_PER_LONG == 64
422 base |= ((long) mem_base_hi) << 32;
423 limit |= ((long) mem_limit_hi) << 32;
425 if (mem_base_hi || mem_limit_hi) {
426 dev_err(&dev->dev, "can't handle 64-bit "
427 "address space for bridge\n");
434 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
436 res->end = limit + 0xfffff;
437 printk(KERN_INFO "PCI: bridge %s %sbit mmio pref: [%llx, %llx]\n",
438 pci_name(dev), (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
439 (unsigned long long) res->start, (unsigned long long) res->end);
443 static struct pci_bus * pci_alloc_bus(void)
447 b = kzalloc(sizeof(*b), GFP_KERNEL);
449 INIT_LIST_HEAD(&b->node);
450 INIT_LIST_HEAD(&b->children);
451 INIT_LIST_HEAD(&b->devices);
452 INIT_LIST_HEAD(&b->slots);
457 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
458 struct pci_dev *bridge, int busnr)
460 struct pci_bus *child;
464 * Allocate a new bus, and inherit stuff from the parent..
466 child = pci_alloc_bus();
470 child->self = bridge;
471 child->parent = parent;
472 child->ops = parent->ops;
473 child->sysdata = parent->sysdata;
474 child->bus_flags = parent->bus_flags;
475 child->bridge = get_device(&bridge->dev);
477 /* initialize some portions of the bus device, but don't register it
478 * now as the parent is not properly set up yet. This device will get
479 * registered later in pci_bus_add_devices()
481 child->dev.class = &pcibus_class;
482 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
485 * Set up the primary, secondary and subordinate
488 child->number = child->secondary = busnr;
489 child->primary = parent->secondary;
490 child->subordinate = 0xff;
492 /* Set up default resource pointers and names.. */
493 for (i = 0; i < 4; i++) {
494 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
495 child->resource[i]->name = child->name;
497 bridge->subordinate = child;
502 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
504 struct pci_bus *child;
506 child = pci_alloc_child_bus(parent, dev, busnr);
508 down_write(&pci_bus_sem);
509 list_add_tail(&child->node, &parent->children);
510 up_write(&pci_bus_sem);
515 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
517 struct pci_bus *parent = child->parent;
519 /* Attempts to fix that up are really dangerous unless
520 we're going to re-assign all bus numbers. */
521 if (!pcibios_assign_all_busses())
524 while (parent->parent && parent->subordinate < max) {
525 parent->subordinate = max;
526 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
527 parent = parent->parent;
532 * If it's a bridge, configure it and scan the bus behind it.
533 * For CardBus bridges, we don't scan behind as the devices will
534 * be handled by the bridge driver itself.
536 * We need to process bridges in two passes -- first we scan those
537 * already configured by the BIOS and after we are done with all of
538 * them, we proceed to assigning numbers to the remaining buses in
539 * order to avoid overlaps between old and new bus numbers.
541 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
543 struct pci_bus *child;
544 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
548 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
550 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
551 buses & 0xffffff, pass);
553 /* Disable MasterAbortMode during probing to avoid reporting
554 of bus errors (in some architectures) */
555 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
556 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
557 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
559 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
560 unsigned int cmax, busnr;
562 * Bus already configured by firmware, process it in the first
563 * pass and just note the configuration.
567 busnr = (buses >> 8) & 0xFF;
570 * If we already got to this bus through a different bridge,
571 * ignore it. This can happen with the i450NX chipset.
573 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
574 dev_info(&dev->dev, "bus %04x:%02x already known\n",
575 pci_domain_nr(bus), busnr);
579 child = pci_add_new_bus(bus, dev, busnr);
582 child->primary = buses & 0xFF;
583 child->subordinate = (buses >> 16) & 0xFF;
584 child->bridge_ctl = bctl;
586 cmax = pci_scan_child_bus(child);
589 if (child->subordinate > max)
590 max = child->subordinate;
593 * We need to assign a number to this bus which we always
594 * do in the second pass.
597 if (pcibios_assign_all_busses())
598 /* Temporarily disable forwarding of the
599 configuration cycles on all bridges in
600 this bus segment to avoid possible
601 conflicts in the second pass between two
602 bridges programmed with overlapping
604 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
610 pci_write_config_word(dev, PCI_STATUS, 0xffff);
612 /* Prevent assigning a bus number that already exists.
613 * This can happen when a bridge is hot-plugged */
614 if (pci_find_bus(pci_domain_nr(bus), max+1))
616 child = pci_add_new_bus(bus, dev, ++max);
617 buses = (buses & 0xff000000)
618 | ((unsigned int)(child->primary) << 0)
619 | ((unsigned int)(child->secondary) << 8)
620 | ((unsigned int)(child->subordinate) << 16);
623 * yenta.c forces a secondary latency timer of 176.
624 * Copy that behaviour here.
627 buses &= ~0xff000000;
628 buses |= CARDBUS_LATENCY_TIMER << 24;
632 * We need to blast all three values with a single write.
634 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
637 child->bridge_ctl = bctl;
639 * Adjust subordinate busnr in parent buses.
640 * We do this before scanning for children because
641 * some devices may not be detected if the bios
644 pci_fixup_parent_subordinate_busnr(child, max);
645 /* Now we can scan all subordinate buses... */
646 max = pci_scan_child_bus(child);
648 * now fix it up again since we have found
649 * the real value of max.
651 pci_fixup_parent_subordinate_busnr(child, max);
654 * For CardBus bridges, we leave 4 bus numbers
655 * as cards with a PCI-to-PCI bridge can be
658 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
659 struct pci_bus *parent = bus;
660 if (pci_find_bus(pci_domain_nr(bus),
663 while (parent->parent) {
664 if ((!pcibios_assign_all_busses()) &&
665 (parent->subordinate > max) &&
666 (parent->subordinate <= max+i)) {
669 parent = parent->parent;
673 * Often, there are two cardbus bridges
674 * -- try to leave one valid bus number
682 pci_fixup_parent_subordinate_busnr(child, max);
685 * Set the subordinate bus number to its real value.
687 child->subordinate = max;
688 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
692 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
693 pci_domain_nr(bus), child->number);
695 /* Has only triggered on CardBus, fixup is in yenta_socket */
696 while (bus->parent) {
697 if ((child->subordinate > bus->subordinate) ||
698 (child->number > bus->subordinate) ||
699 (child->number < bus->number) ||
700 (child->subordinate < bus->number)) {
701 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
702 "hidden behind%s bridge #%02x (-#%02x)\n",
703 child->number, child->subordinate,
704 (bus->number > child->subordinate &&
705 bus->subordinate < child->number) ?
706 "wholly" : "partially",
707 bus->self->transparent ? " transparent" : "",
708 bus->number, bus->subordinate);
714 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
720 * Read interrupt line and base address registers.
721 * The architecture-dependent code can tweak these, of course.
723 static void pci_read_irq(struct pci_dev *dev)
727 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
730 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
734 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
737 * pci_setup_device - fill in class and map information of a device
738 * @dev: the device structure to fill
740 * Initialize the device structure with information about the device's
741 * vendor,class,memory and IO-space addresses,IRQ lines etc.
742 * Called at initialisation of the PCI subsystem and by CardBus services.
743 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
746 static int pci_setup_device(struct pci_dev * dev)
750 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
751 dev->bus->number, PCI_SLOT(dev->devfn),
752 PCI_FUNC(dev->devfn));
754 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
755 dev->revision = class & 0xff;
756 class >>= 8; /* upper 3 bytes */
760 dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n",
761 dev->vendor, dev->device, class, dev->hdr_type);
763 /* "Unknown power state" */
764 dev->current_state = PCI_UNKNOWN;
766 /* Early fixups, before probing the BARs */
767 pci_fixup_device(pci_fixup_early, dev);
768 class = dev->class >> 8;
770 switch (dev->hdr_type) { /* header type */
771 case PCI_HEADER_TYPE_NORMAL: /* standard header */
772 if (class == PCI_CLASS_BRIDGE_PCI)
775 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
776 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
777 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
780 * Do the ugly legacy mode stuff here rather than broken chip
781 * quirk code. Legacy mode ATA controllers have fixed
782 * addresses. These are not always echoed in BAR0-3, and
783 * BAR0-3 in a few cases contain junk!
785 if (class == PCI_CLASS_STORAGE_IDE) {
787 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
788 if ((progif & 1) == 0) {
789 dev->resource[0].start = 0x1F0;
790 dev->resource[0].end = 0x1F7;
791 dev->resource[0].flags = LEGACY_IO_RESOURCE;
792 dev->resource[1].start = 0x3F6;
793 dev->resource[1].end = 0x3F6;
794 dev->resource[1].flags = LEGACY_IO_RESOURCE;
796 if ((progif & 4) == 0) {
797 dev->resource[2].start = 0x170;
798 dev->resource[2].end = 0x177;
799 dev->resource[2].flags = LEGACY_IO_RESOURCE;
800 dev->resource[3].start = 0x376;
801 dev->resource[3].end = 0x376;
802 dev->resource[3].flags = LEGACY_IO_RESOURCE;
807 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
808 if (class != PCI_CLASS_BRIDGE_PCI)
810 /* The PCI-to-PCI bridge spec requires that subtractive
811 decoding (i.e. transparent) bridge must have programming
812 interface code of 0x01. */
814 dev->transparent = ((dev->class & 0xff) == 1);
815 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
818 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
819 if (class != PCI_CLASS_BRIDGE_CARDBUS)
822 pci_read_bases(dev, 1, 0);
823 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
824 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
827 default: /* unknown header */
828 dev_err(&dev->dev, "unknown header type %02x, "
829 "ignoring device\n", dev->hdr_type);
833 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
834 "type %02x)\n", class, dev->hdr_type);
835 dev->class = PCI_CLASS_NOT_DEFINED;
838 /* We found a fine healthy device, go go go... */
843 * pci_release_dev - free a pci device structure when all users of it are finished.
844 * @dev: device that's been disconnected
846 * Will be called only by the device core when all users of this pci device are
849 static void pci_release_dev(struct device *dev)
851 struct pci_dev *pci_dev;
853 pci_dev = to_pci_dev(dev);
854 pci_vpd_release(pci_dev);
858 static void set_pcie_port_type(struct pci_dev *pdev)
863 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
867 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
868 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
872 * pci_cfg_space_size - get the configuration space size of the PCI device.
875 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
876 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
877 * access it. Maybe we don't have a way to generate extended config space
878 * accesses, or the device is behind a reverse Express bridge. So we try
879 * reading the dword at 0x100 which must either be 0 or a valid extended
882 int pci_cfg_space_size_ext(struct pci_dev *dev)
886 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
888 if (status == 0xffffffff)
891 return PCI_CFG_SPACE_EXP_SIZE;
894 return PCI_CFG_SPACE_SIZE;
897 int pci_cfg_space_size(struct pci_dev *dev)
902 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
904 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
908 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
909 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
913 return pci_cfg_space_size_ext(dev);
916 return PCI_CFG_SPACE_SIZE;
919 static void pci_release_bus_bridge_dev(struct device *dev)
924 struct pci_dev *alloc_pci_dev(void)
928 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
932 INIT_LIST_HEAD(&dev->bus_list);
934 pci_msi_init_pci_dev(dev);
938 EXPORT_SYMBOL(alloc_pci_dev);
941 * Read the config data for a PCI device, sanity-check it
942 * and fill in the dev structure...
944 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
951 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
954 /* some broken boards return 0 or ~0 if a slot is empty: */
955 if (l == 0xffffffff || l == 0x00000000 ||
956 l == 0x0000ffff || l == 0xffff0000)
959 /* Configuration request Retry Status */
960 while (l == 0xffff0001) {
963 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
965 /* Card hasn't responded in 60 seconds? Must be stuck. */
966 if (delay > 60 * 1000) {
967 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
968 "responding\n", pci_domain_nr(bus),
969 bus->number, PCI_SLOT(devfn),
975 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
978 dev = alloc_pci_dev();
983 dev->sysdata = bus->sysdata;
984 dev->dev.parent = bus->bridge;
985 dev->dev.bus = &pci_bus_type;
987 dev->hdr_type = hdr_type & 0x7f;
988 dev->multifunction = !!(hdr_type & 0x80);
989 dev->vendor = l & 0xffff;
990 dev->device = (l >> 16) & 0xffff;
991 dev->cfg_size = pci_cfg_space_size(dev);
992 dev->error_state = pci_channel_io_normal;
993 set_pcie_port_type(dev);
995 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
996 set this higher, assuming the system even supports it. */
997 dev->dma_mask = 0xffffffff;
998 if (pci_setup_device(dev) < 0) {
1003 pci_vpd_pci22_init(dev);
1008 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1010 device_initialize(&dev->dev);
1011 dev->dev.release = pci_release_dev;
1014 dev->dev.dma_mask = &dev->dma_mask;
1015 dev->dev.dma_parms = &dev->dma_parms;
1016 dev->dev.coherent_dma_mask = 0xffffffffull;
1018 pci_set_dma_max_seg_size(dev, 65536);
1019 pci_set_dma_seg_boundary(dev, 0xffffffff);
1021 /* Fix up broken headers */
1022 pci_fixup_device(pci_fixup_header, dev);
1024 /* Initialize power management of the device */
1028 * Add the device to our list of discovered devices
1029 * and the bus list for fixup functions, etc.
1031 down_write(&pci_bus_sem);
1032 list_add_tail(&dev->bus_list, &bus->devices);
1033 up_write(&pci_bus_sem);
1036 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1038 struct pci_dev *dev;
1040 dev = pci_scan_device(bus, devfn);
1044 pci_device_add(dev, bus);
1048 EXPORT_SYMBOL(pci_scan_single_device);
1051 * pci_scan_slot - scan a PCI slot on a bus for devices.
1052 * @bus: PCI bus to scan
1053 * @devfn: slot number to scan (must have zero function.)
1055 * Scan a PCI slot on the specified PCI bus for devices, adding
1056 * discovered devices to the @bus->devices list. New devices
1057 * will not have is_added set.
1059 int pci_scan_slot(struct pci_bus *bus, int devfn)
1064 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1066 for (func = 0; func < 8; func++, devfn++) {
1067 struct pci_dev *dev;
1069 dev = pci_scan_single_device(bus, devfn);
1074 * If this is a single function device,
1075 * don't scan past the first function.
1077 if (!dev->multifunction) {
1079 dev->multifunction = 1;
1085 if (func == 0 && !scan_all_fns)
1090 /* only one slot has pcie device */
1091 if (bus->self && nr)
1092 pcie_aspm_init_link_state(bus->self);
1097 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1099 unsigned int devfn, pass, max = bus->secondary;
1100 struct pci_dev *dev;
1102 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1104 /* Go find them, Rover! */
1105 for (devfn = 0; devfn < 0x100; devfn += 8)
1106 pci_scan_slot(bus, devfn);
1109 * After performing arch-dependent fixup of the bus, look behind
1110 * all PCI-to-PCI bridges on this bus.
1112 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1113 pcibios_fixup_bus(bus);
1114 for (pass=0; pass < 2; pass++)
1115 list_for_each_entry(dev, &bus->devices, bus_list) {
1116 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1117 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1118 max = pci_scan_bridge(bus, dev, max, pass);
1122 * We've scanned the bus and so we know all about what's on
1123 * the other side of any bridges that may be on this bus plus
1126 * Return how far we've got finding sub-buses.
1128 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1129 pci_domain_nr(bus), bus->number, max);
1133 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1137 struct pci_bus * pci_create_bus(struct device *parent,
1138 int bus, struct pci_ops *ops, void *sysdata)
1144 b = pci_alloc_bus();
1148 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1154 b->sysdata = sysdata;
1157 if (pci_find_bus(pci_domain_nr(b), bus)) {
1158 /* If we already got to this bus through a different bridge, ignore it */
1159 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1163 down_write(&pci_bus_sem);
1164 list_add_tail(&b->node, &pci_root_buses);
1165 up_write(&pci_bus_sem);
1167 memset(dev, 0, sizeof(*dev));
1168 dev->parent = parent;
1169 dev->release = pci_release_bus_bridge_dev;
1170 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1171 error = device_register(dev);
1174 b->bridge = get_device(dev);
1177 set_dev_node(b->bridge, pcibus_to_node(b));
1179 b->dev.class = &pcibus_class;
1180 b->dev.parent = b->bridge;
1181 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1182 error = device_register(&b->dev);
1184 goto class_dev_reg_err;
1185 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1187 goto dev_create_file_err;
1189 /* Create legacy_io and legacy_mem files for this bus */
1190 pci_create_legacy_files(b);
1192 b->number = b->secondary = bus;
1193 b->resource[0] = &ioport_resource;
1194 b->resource[1] = &iomem_resource;
1196 set_pci_bus_resources_arch_default(b);
1200 dev_create_file_err:
1201 device_unregister(&b->dev);
1203 device_unregister(dev);
1205 down_write(&pci_bus_sem);
1207 up_write(&pci_bus_sem);
1214 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1215 int bus, struct pci_ops *ops, void *sysdata)
1219 b = pci_create_bus(parent, bus, ops, sysdata);
1221 b->subordinate = pci_scan_child_bus(b);
1224 EXPORT_SYMBOL(pci_scan_bus_parented);
1226 #ifdef CONFIG_HOTPLUG
1227 EXPORT_SYMBOL(pci_add_new_bus);
1228 EXPORT_SYMBOL(pci_scan_slot);
1229 EXPORT_SYMBOL(pci_scan_bridge);
1230 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1233 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1235 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1236 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1238 if (a->bus->number < b->bus->number) return -1;
1239 else if (a->bus->number > b->bus->number) return 1;
1241 if (a->devfn < b->devfn) return -1;
1242 else if (a->devfn > b->devfn) return 1;
1248 * Yes, this forcably breaks the klist abstraction temporarily. It
1249 * just wants to sort the klist, not change reference counts and
1250 * take/drop locks rapidly in the process. It does all this while
1251 * holding the lock for the list, so objects can't otherwise be
1252 * added/removed while we're swizzling.
1254 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1256 struct list_head *pos;
1257 struct klist_node *n;
1261 list_for_each(pos, list) {
1262 n = container_of(pos, struct klist_node, n_node);
1263 dev = container_of(n, struct device, knode_bus);
1264 b = to_pci_dev(dev);
1265 if (pci_sort_bf_cmp(a, b) <= 0) {
1266 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1270 list_move_tail(&a->dev.knode_bus.n_node, list);
1273 void __init pci_sort_breadthfirst(void)
1275 LIST_HEAD(sorted_devices);
1276 struct list_head *pos, *tmp;
1277 struct klist_node *n;
1279 struct pci_dev *pdev;
1280 struct klist *device_klist;
1282 device_klist = bus_get_device_klist(&pci_bus_type);
1284 spin_lock(&device_klist->k_lock);
1285 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1286 n = container_of(pos, struct klist_node, n_node);
1287 dev = container_of(n, struct device, knode_bus);
1288 pdev = to_pci_dev(dev);
1289 pci_insertion_sort_klist(pdev, &sorted_devices);
1291 list_splice(&sorted_devices, &device_klist->k_list);
1292 spin_unlock(&device_klist->k_lock);