1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2008 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
68 /* Common Transport structures and definitions */
71 /* Structure is in Big Endian format */
79 union CtCommandResponse {
80 /* Structure is in Big Endian format */
88 #define FC4_FEATURE_INIT 0x2
89 #define FC4_FEATURE_TARGET 0x1
91 struct lpfc_sli_ct_request {
92 /* Structure is in Big Endian format */
93 union CtRevisionId RevisionId;
98 union CtCommandResponse CommandResponse;
102 uint8_t VendorUnique;
107 uint8_t PortType; /* for GID_PT requests */
110 uint8_t Fc4Type; /* for GID_FT requests */
113 uint32_t PortId; /* For RFT_ID requests */
115 #ifdef __BIG_ENDIAN_BITFIELD
118 uint32_t fcpReg:1; /* Type 8 */
120 uint32_t ipReg:1; /* Type 5 */
122 #else /* __LITTLE_ENDIAN_BITFIELD */
124 uint32_t fcpReg:1; /* Type 8 */
127 uint32_t ipReg:1; /* Type 5 */
134 uint32_t PortId; /* For RNN_ID requests */
137 struct rsnn { /* For RSNN_ID requests */
140 uint8_t symbname[255];
142 struct da_id { /* For DA_ID requests */
145 struct rspn { /* For RSPN_ID requests */
148 uint8_t symbname[255];
156 #define FCP_TYPE_FEATURE_OFFSET 7
161 uint8_t type_code; /* type=8 for FCP */
166 #define SLI_CT_REVISION 1
167 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
169 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
171 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
173 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
180 sizeof(struct da_id))
181 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
188 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
189 #define SLI_CT_TIME_SERVICE 0xFB
190 #define SLI_CT_DIRECTORY_SERVICE 0xFC
191 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
194 * Directory Service Subtypes
197 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
203 #define SLI_CT_RESPONSE_FS_RJT 0x8001
204 #define SLI_CT_RESPONSE_FS_ACC 0x8002
210 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
211 #define SLI_CT_INVALID_COMMAND 0x01
212 #define SLI_CT_INVALID_VERSION 0x02
213 #define SLI_CT_LOGICAL_ERROR 0x03
214 #define SLI_CT_INVALID_IU_SIZE 0x04
215 #define SLI_CT_LOGICAL_BUSY 0x05
216 #define SLI_CT_PROTOCOL_ERROR 0x07
217 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
218 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
219 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
220 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
221 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
222 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
223 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
224 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
225 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
226 #define SLI_CT_VENDOR_UNIQUE 0xff
229 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
232 #define SLI_CT_NO_PORT_ID 0x01
233 #define SLI_CT_NO_PORT_NAME 0x02
234 #define SLI_CT_NO_NODE_NAME 0x03
235 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
236 #define SLI_CT_NO_IP_ADDRESS 0x05
237 #define SLI_CT_NO_IPA 0x06
238 #define SLI_CT_NO_FC4_TYPES 0x07
239 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
240 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
241 #define SLI_CT_NO_PORT_TYPE 0x0A
242 #define SLI_CT_ACCESS_DENIED 0x10
243 #define SLI_CT_INVALID_PORT_ID 0x11
244 #define SLI_CT_DATABASE_EMPTY 0x12
247 * Name Server Command Codes
250 #define SLI_CTNS_GA_NXT 0x0100
251 #define SLI_CTNS_GPN_ID 0x0112
252 #define SLI_CTNS_GNN_ID 0x0113
253 #define SLI_CTNS_GCS_ID 0x0114
254 #define SLI_CTNS_GFT_ID 0x0117
255 #define SLI_CTNS_GSPN_ID 0x0118
256 #define SLI_CTNS_GPT_ID 0x011A
257 #define SLI_CTNS_GFF_ID 0x011F
258 #define SLI_CTNS_GID_PN 0x0121
259 #define SLI_CTNS_GID_NN 0x0131
260 #define SLI_CTNS_GIP_NN 0x0135
261 #define SLI_CTNS_GIPA_NN 0x0136
262 #define SLI_CTNS_GSNN_NN 0x0139
263 #define SLI_CTNS_GNN_IP 0x0153
264 #define SLI_CTNS_GIPA_IP 0x0156
265 #define SLI_CTNS_GID_FT 0x0171
266 #define SLI_CTNS_GID_PT 0x01A1
267 #define SLI_CTNS_RPN_ID 0x0212
268 #define SLI_CTNS_RNN_ID 0x0213
269 #define SLI_CTNS_RCS_ID 0x0214
270 #define SLI_CTNS_RFT_ID 0x0217
271 #define SLI_CTNS_RSPN_ID 0x0218
272 #define SLI_CTNS_RPT_ID 0x021A
273 #define SLI_CTNS_RFF_ID 0x021F
274 #define SLI_CTNS_RIP_NN 0x0235
275 #define SLI_CTNS_RIPA_NN 0x0236
276 #define SLI_CTNS_RSNN_NN 0x0239
277 #define SLI_CTNS_DA_ID 0x0300
283 #define SLI_CTPT_N_PORT 0x01
284 #define SLI_CTPT_NL_PORT 0x02
285 #define SLI_CTPT_FNL_PORT 0x03
286 #define SLI_CTPT_IP 0x04
287 #define SLI_CTPT_FCP 0x08
288 #define SLI_CTPT_NX_PORT 0x7F
289 #define SLI_CTPT_F_PORT 0x81
290 #define SLI_CTPT_FL_PORT 0x82
291 #define SLI_CTPT_E_PORT 0x84
293 #define SLI_CT_LAST_ENTRY 0x80000000
295 /* Fibre Channel Service Parameter definitions */
297 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
298 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
299 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
300 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
302 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
303 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
304 #define FC_PH3 0x20 /* FC-PH-3 version */
306 #define FF_FRAME_SIZE 2048
311 #ifdef __BIG_ENDIAN_BITFIELD
312 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
313 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
315 #else /* __LITTLE_ENDIAN_BITFIELD */
316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
318 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
321 #define NAME_IEEE 0x1 /* IEEE name - nameType */
322 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
323 #define NAME_FC_TYPE 0x3 /* FC native name type */
324 #define NAME_IP_TYPE 0x4 /* IP address */
325 #define NAME_CCITT_TYPE 0xC
326 #define NAME_CCITT_GR_TYPE 0xE
327 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
329 uint8_t IEEE[6]; /* FC IEEE address */
336 uint8_t fcphHigh; /* FC Word 0, byte 0 */
339 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
341 #ifdef __BIG_ENDIAN_BITFIELD
342 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
343 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
344 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
345 uint16_t fPort:1; /* FC Word 1, bit 28 */
346 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
347 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
348 uint16_t multicast:1; /* FC Word 1, bit 25 */
349 uint16_t broadcast:1; /* FC Word 1, bit 24 */
351 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
352 uint16_t simplex:1; /* FC Word 1, bit 22 */
353 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
354 uint16_t dhd:1; /* FC Word 1, bit 18 */
355 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
356 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
357 #else /* __LITTLE_ENDIAN_BITFIELD */
358 uint16_t broadcast:1; /* FC Word 1, bit 24 */
359 uint16_t multicast:1; /* FC Word 1, bit 25 */
360 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
361 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
362 uint16_t fPort:1; /* FC Word 1, bit 28 */
363 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
364 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
365 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
367 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
368 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
369 uint16_t dhd:1; /* FC Word 1, bit 18 */
370 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
371 uint16_t simplex:1; /* FC Word 1, bit 22 */
372 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
375 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
376 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
379 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
381 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
382 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
384 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
386 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
389 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
393 #ifdef __BIG_ENDIAN_BITFIELD
394 uint8_t classValid:1; /* FC Word 0, bit 31 */
395 uint8_t intermix:1; /* FC Word 0, bit 30 */
396 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
397 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
398 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
399 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
400 #else /* __LITTLE_ENDIAN_BITFIELD */
401 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
402 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
403 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
404 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
405 uint8_t intermix:1; /* FC Word 0, bit 30 */
406 uint8_t classValid:1; /* FC Word 0, bit 31 */
410 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
412 #ifdef __BIG_ENDIAN_BITFIELD
413 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
414 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
415 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
416 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
417 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
418 #else /* __LITTLE_ENDIAN_BITFIELD */
419 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
420 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
421 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
422 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
423 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
426 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
428 #ifdef __BIG_ENDIAN_BITFIELD
429 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
430 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
431 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
432 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
433 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
434 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
435 #else /* __LITTLE_ENDIAN_BITFIELD */
436 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
437 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
438 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
439 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
440 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
441 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
444 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
445 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
446 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
448 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
449 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
450 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
451 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
453 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
454 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
455 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
456 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
459 struct serv_parm { /* Structure is in Big Endian format */
461 struct lpfc_name portName;
462 struct lpfc_name nodeName;
463 struct class_parms cls1;
464 struct class_parms cls2;
465 struct class_parms cls3;
466 struct class_parms cls4;
467 uint8_t vendorVersion[16];
471 * Extended Link Service LS_COMMAND codes (Payload Word 0)
473 #ifdef __BIG_ENDIAN_BITFIELD
474 #define ELS_CMD_MASK 0xffff0000
475 #define ELS_RSP_MASK 0xff000000
476 #define ELS_CMD_LS_RJT 0x01000000
477 #define ELS_CMD_ACC 0x02000000
478 #define ELS_CMD_PLOGI 0x03000000
479 #define ELS_CMD_FLOGI 0x04000000
480 #define ELS_CMD_LOGO 0x05000000
481 #define ELS_CMD_ABTX 0x06000000
482 #define ELS_CMD_RCS 0x07000000
483 #define ELS_CMD_RES 0x08000000
484 #define ELS_CMD_RSS 0x09000000
485 #define ELS_CMD_RSI 0x0A000000
486 #define ELS_CMD_ESTS 0x0B000000
487 #define ELS_CMD_ESTC 0x0C000000
488 #define ELS_CMD_ADVC 0x0D000000
489 #define ELS_CMD_RTV 0x0E000000
490 #define ELS_CMD_RLS 0x0F000000
491 #define ELS_CMD_ECHO 0x10000000
492 #define ELS_CMD_TEST 0x11000000
493 #define ELS_CMD_RRQ 0x12000000
494 #define ELS_CMD_PRLI 0x20100014
495 #define ELS_CMD_PRLO 0x21100014
496 #define ELS_CMD_PRLO_ACC 0x02100014
497 #define ELS_CMD_PDISC 0x50000000
498 #define ELS_CMD_FDISC 0x51000000
499 #define ELS_CMD_ADISC 0x52000000
500 #define ELS_CMD_FARP 0x54000000
501 #define ELS_CMD_FARPR 0x55000000
502 #define ELS_CMD_RPS 0x56000000
503 #define ELS_CMD_RPL 0x57000000
504 #define ELS_CMD_FAN 0x60000000
505 #define ELS_CMD_RSCN 0x61040000
506 #define ELS_CMD_SCR 0x62000000
507 #define ELS_CMD_RNID 0x78000000
508 #define ELS_CMD_LIRR 0x7A000000
509 #else /* __LITTLE_ENDIAN_BITFIELD */
510 #define ELS_CMD_MASK 0xffff
511 #define ELS_RSP_MASK 0xff
512 #define ELS_CMD_LS_RJT 0x01
513 #define ELS_CMD_ACC 0x02
514 #define ELS_CMD_PLOGI 0x03
515 #define ELS_CMD_FLOGI 0x04
516 #define ELS_CMD_LOGO 0x05
517 #define ELS_CMD_ABTX 0x06
518 #define ELS_CMD_RCS 0x07
519 #define ELS_CMD_RES 0x08
520 #define ELS_CMD_RSS 0x09
521 #define ELS_CMD_RSI 0x0A
522 #define ELS_CMD_ESTS 0x0B
523 #define ELS_CMD_ESTC 0x0C
524 #define ELS_CMD_ADVC 0x0D
525 #define ELS_CMD_RTV 0x0E
526 #define ELS_CMD_RLS 0x0F
527 #define ELS_CMD_ECHO 0x10
528 #define ELS_CMD_TEST 0x11
529 #define ELS_CMD_RRQ 0x12
530 #define ELS_CMD_PRLI 0x14001020
531 #define ELS_CMD_PRLO 0x14001021
532 #define ELS_CMD_PRLO_ACC 0x14001002
533 #define ELS_CMD_PDISC 0x50
534 #define ELS_CMD_FDISC 0x51
535 #define ELS_CMD_ADISC 0x52
536 #define ELS_CMD_FARP 0x54
537 #define ELS_CMD_FARPR 0x55
538 #define ELS_CMD_RPS 0x56
539 #define ELS_CMD_RPL 0x57
540 #define ELS_CMD_FAN 0x60
541 #define ELS_CMD_RSCN 0x0461
542 #define ELS_CMD_SCR 0x62
543 #define ELS_CMD_RNID 0x78
544 #define ELS_CMD_LIRR 0x7A
548 * LS_RJT Payload Definition
551 struct ls_rjt { /* Structure is in Big Endian format */
555 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
557 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
558 /* LS_RJT reason codes */
559 #define LSRJT_INVALID_CMD 0x01
560 #define LSRJT_LOGICAL_ERR 0x03
561 #define LSRJT_LOGICAL_BSY 0x05
562 #define LSRJT_PROTOCOL_ERR 0x07
563 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
564 #define LSRJT_CMD_UNSUPPORTED 0x0B
565 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
567 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
568 /* LS_RJT reason explanation */
569 #define LSEXP_NOTHING_MORE 0x00
570 #define LSEXP_SPARM_OPTIONS 0x01
571 #define LSEXP_SPARM_ICTL 0x03
572 #define LSEXP_SPARM_RCTL 0x05
573 #define LSEXP_SPARM_RCV_SIZE 0x07
574 #define LSEXP_SPARM_CONCUR_SEQ 0x09
575 #define LSEXP_SPARM_CREDIT 0x0B
576 #define LSEXP_INVALID_PNAME 0x0D
577 #define LSEXP_INVALID_NNAME 0x0E
578 #define LSEXP_INVALID_CSP 0x0F
579 #define LSEXP_INVALID_ASSOC_HDR 0x11
580 #define LSEXP_ASSOC_HDR_REQ 0x13
581 #define LSEXP_INVALID_O_SID 0x15
582 #define LSEXP_INVALID_OX_RX 0x17
583 #define LSEXP_CMD_IN_PROGRESS 0x19
584 #define LSEXP_PORT_LOGIN_REQ 0x1E
585 #define LSEXP_INVALID_NPORT_ID 0x1F
586 #define LSEXP_INVALID_SEQ_ID 0x21
587 #define LSEXP_INVALID_XCHG 0x23
588 #define LSEXP_INACTIVE_XCHG 0x25
589 #define LSEXP_RQ_REQUIRED 0x27
590 #define LSEXP_OUT_OF_RESOURCE 0x29
591 #define LSEXP_CANT_GIVE_DATA 0x2A
592 #define LSEXP_REQ_UNSUPPORTED 0x2C
593 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
599 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
602 typedef struct _LOGO { /* Structure is in Big Endian format */
604 uint32_t nPortId32; /* Access nPortId as a word */
606 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
607 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
608 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
609 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
612 struct lpfc_name portName; /* N_port name field */
616 * FCP Login (PRLI Request / ACC) Payload Definition
619 #define PRLX_PAGE_LEN 0x10
620 #define TPRLO_PAGE_LEN 0x14
622 typedef struct _PRLI { /* Structure is in Big Endian format */
623 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
625 #define PRLI_FCP_TYPE 0x08
626 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
628 #ifdef __BIG_ENDIAN_BITFIELD
629 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
630 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
631 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
633 /* ACC = imagePairEstablished */
634 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
635 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
636 #else /* __LITTLE_ENDIAN_BITFIELD */
637 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
638 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
639 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
640 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
641 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
642 /* ACC = imagePairEstablished */
645 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
646 #define PRLI_NO_RESOURCES 0x2
647 #define PRLI_INIT_INCOMPLETE 0x3
648 #define PRLI_NO_SUCH_PA 0x4
649 #define PRLI_PREDEF_CONFIG 0x5
650 #define PRLI_PARTIAL_SUCCESS 0x6
651 #define PRLI_INVALID_PAGE_CNT 0x7
652 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
654 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
656 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
658 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
659 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
661 #ifdef __BIG_ENDIAN_BITFIELD
662 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
663 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
664 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
665 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
666 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
667 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
668 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
669 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
670 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
671 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
672 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
673 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
674 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
675 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
676 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
677 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
678 #else /* __LITTLE_ENDIAN_BITFIELD */
679 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
680 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
681 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
682 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
683 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
684 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
685 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
686 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
687 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
688 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
689 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
690 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
691 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
692 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
693 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
694 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
699 * FCP Logout (PRLO Request / ACC) Payload Definition
702 typedef struct _PRLO { /* Structure is in Big Endian format */
703 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
705 #define PRLO_FCP_TYPE 0x08
706 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
708 #ifdef __BIG_ENDIAN_BITFIELD
709 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
710 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
711 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
712 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
713 #else /* __LITTLE_ENDIAN_BITFIELD */
714 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
715 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
716 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
717 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
720 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
721 #define PRLO_NO_SUCH_IMAGE 0x4
722 #define PRLO_INVALID_PAGE_CNT 0x7
724 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
726 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
728 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
730 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
733 typedef struct _ADISC { /* Structure is in Big Endian format */
735 struct lpfc_name portName;
736 struct lpfc_name nodeName;
740 typedef struct _FARP { /* Structure is in Big Endian format */
743 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
745 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
746 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
747 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
748 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
750 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
754 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
755 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
756 struct lpfc_name OportName;
757 struct lpfc_name OnodeName;
758 struct lpfc_name RportName;
759 struct lpfc_name RnodeName;
764 typedef struct _FAN { /* Structure is in Big Endian format */
766 struct lpfc_name FportName;
767 struct lpfc_name FnodeName;
770 typedef struct _SCR { /* Structure is in Big Endian format */
775 #define SCR_FUNC_FABRIC 0x01
776 #define SCR_FUNC_NPORT 0x02
777 #define SCR_FUNC_FULL 0x03
778 #define SCR_CLEAR 0xff
781 typedef struct _RNID_TOP_DISC {
782 struct lpfc_name portName;
786 #define RNID_HOST 0xa
787 #define RNID_DRIVER 0xd
789 uint32_t attachedNodes;
791 #define RNID_IPV4 0x1
792 #define RNID_IPV6 0x2
797 #define RNID_TD_SUPPORT 0x1
798 #define RNID_LP_VALID 0x2
801 typedef struct _RNID { /* Structure is in Big Endian format */
803 #define RNID_TOPOLOGY_DISC 0xdf
807 struct lpfc_name portName;
808 struct lpfc_name nodeName;
810 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
814 typedef struct _RPS { /* Structure is in Big Endian format */
817 struct lpfc_name portName;
821 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
824 uint32_t linkFailureCnt;
825 uint32_t lossSyncCnt;
826 uint32_t lossSignalCnt;
827 uint32_t primSeqErrCnt;
828 uint32_t invalidXmitWord;
832 typedef struct _RPL { /* Structure is in Big Endian format */
837 typedef struct _PORT_NUM_BLK {
840 struct lpfc_name portName;
843 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
846 PORT_NUM_BLK port_num_blk;
849 /* This is used for RSCN command */
850 typedef struct _D_ID { /* Structure is in Big Endian format */
854 #ifdef __BIG_ENDIAN_BITFIELD
859 #else /* __LITTLE_ENDIAN_BITFIELD */
870 * Structure to define all ELS Payload types
873 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
874 uint8_t elsCode; /* FC Word 0, bit 24:31 */
879 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
880 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
881 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
882 PRLI prli; /* Payload for PRLI/ACC */
883 PRLO prlo; /* Payload for PRLO/ACC */
884 ADISC adisc; /* Payload for ADISC/ACC */
885 FARP farp; /* Payload for FARP/ACC */
886 FAN fan; /* Payload for FAN */
887 SCR scr; /* Payload for SCR/ACC */
888 RNID rnid; /* Payload for RNID */
889 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
895 * HBA MAnagement Operations Command Codes
897 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
898 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
899 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
900 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
901 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
902 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
903 #define SLI_MGMT_RPRT 0x210 /* Register Port */
904 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
905 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
906 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
909 * Management Service Subtypes
911 #define SLI_CT_FDMI_Subtypes 0x10
914 * HBA Management Service Reject Code
916 #define REJECT_CODE 0x9 /* Unable to perform command request */
919 * HBA Management Service Reject Reason Code
920 * Please refer to the Reason Codes above
924 * HBA Attribute Types
926 #define NODE_NAME 0x1
927 #define MANUFACTURER 0x2
928 #define SERIAL_NUMBER 0x3
930 #define MODEL_DESCRIPTION 0x5
931 #define HARDWARE_VERSION 0x6
932 #define DRIVER_VERSION 0x7
933 #define OPTION_ROM_VERSION 0x8
934 #define FIRMWARE_VERSION 0x9
935 #define OS_NAME_VERSION 0xa
936 #define MAX_CT_PAYLOAD_LEN 0xb
939 * Port Attrubute Types
941 #define SUPPORTED_FC4_TYPES 0x1
942 #define SUPPORTED_SPEED 0x2
943 #define PORT_SPEED 0x3
944 #define MAX_FRAME_SIZE 0x4
945 #define OS_DEVICE_NAME 0x5
946 #define HOST_NAME 0x6
948 union AttributesDef {
949 /* Structure is in Big Endian format */
951 uint32_t AttrType:16;
959 * HBA Attribute Entry (8 - 260 bytes)
962 union AttributesDef ad;
964 uint32_t VendorSpecific;
965 uint8_t Manufacturer[64];
966 uint8_t SerialNumber[64];
968 uint8_t ModelDescription[256];
969 uint8_t HardwareVersion[256];
970 uint8_t DriverVersion[256];
971 uint8_t OptionROMVersion[256];
972 uint8_t FirmwareVersion[256];
973 struct lpfc_name NodeName;
974 uint8_t SupportFC4Types[32];
975 uint32_t SupportSpeed;
977 uint32_t MaxFrameSize;
978 uint8_t OsDeviceName[256];
979 uint8_t OsNameVersion[256];
980 uint32_t MaxCTPayloadLen;
981 uint8_t HostName[256];
986 * HBA Attribute Block
989 uint32_t EntryCnt; /* Number of HBA attribute entries */
990 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
997 struct lpfc_name PortName;
1004 struct lpfc_name PortName;
1008 * Registered Port List Format
1012 PORT_ENTRY pe; /* Variable-length array */
1016 * Register HBA(RHBA)
1020 REG_PORT_LIST rpl; /* variable-length array */
1021 /* ATTRIBUTE_BLOCK ab; */
1025 * Register HBA Attributes (RHAT)
1028 struct lpfc_name HBA_PortName;
1030 } REG_HBA_ATTRIBUTE;
1033 * Register Port Attributes (RPA)
1036 struct lpfc_name PortName;
1038 } REG_PORT_ATTRIBUTE;
1041 * Get Registered HBA List (GRHL) Accept Payload Format
1044 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1045 struct lpfc_name HBA_PortName; /* Variable-length array */
1049 * Get Registered Port List (GRPL) Accept Payload Format
1052 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1053 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1057 * Get Port Attributes (GPAT) Accept Payload Format
1061 ATTRIBUTE_BLOCK pab;
1066 * Begin HBA configuration parameters.
1067 * The PCI configuration register BAR assignments are:
1068 * BAR0, offset 0x10 - SLIM base memory address
1069 * BAR1, offset 0x14 - SLIM base memory high address
1070 * BAR2, offset 0x18 - REGISTER base memory address
1071 * BAR3, offset 0x1c - REGISTER base memory high address
1072 * BAR4, offset 0x20 - BIU I/O registers
1073 * BAR5, offset 0x24 - REGISTER base io high address
1076 /* Number of rings currently used and available. */
1077 #define MAX_CONFIGURED_RINGS 3
1080 /* IOCB / Mailbox is owned by FireFly */
1083 /* IOCB / Mailbox is owned by Host */
1086 /* Number of 4-byte words in an IOCB. */
1087 #define IOCB_WORD_SZ 8
1089 /* defines for type field in fc header */
1090 #define FC_ELS_DATA 0x1
1091 #define FC_LLC_SNAP 0x5
1092 #define FC_FCP_DATA 0x8
1093 #define FC_COMMON_TRANSPORT_ULP 0x20
1095 /* defines for rctl field in fc header */
1096 #define FC_DEV_DATA 0x0
1097 #define FC_UNSOL_CTL 0x2
1098 #define FC_SOL_CTL 0x3
1099 #define FC_UNSOL_DATA 0x4
1100 #define FC_FCP_CMND 0x6
1101 #define FC_ELS_REQ 0x22
1102 #define FC_ELS_RSP 0x23
1104 /* network headers for Dfctl field */
1105 #define FC_NET_HDR 0x20
1107 /* Start FireFly Register definitions */
1108 #define PCI_VENDOR_ID_EMULEX 0x10df
1109 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1110 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1111 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1112 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1113 #define PCI_DEVICE_ID_SAT_MID 0xf015
1114 #define PCI_DEVICE_ID_RFLY 0xf095
1115 #define PCI_DEVICE_ID_PFLY 0xf098
1116 #define PCI_DEVICE_ID_LP101 0xf0a1
1117 #define PCI_DEVICE_ID_TFLY 0xf0a5
1118 #define PCI_DEVICE_ID_BSMB 0xf0d1
1119 #define PCI_DEVICE_ID_BMID 0xf0d5
1120 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1121 #define PCI_DEVICE_ID_ZMID 0xf0e5
1122 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1123 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1124 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1125 #define PCI_DEVICE_ID_SAT 0xf100
1126 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1127 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1128 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1129 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1130 #define PCI_DEVICE_ID_CENTAUR 0xf900
1131 #define PCI_DEVICE_ID_PEGASUS 0xf980
1132 #define PCI_DEVICE_ID_THOR 0xfa00
1133 #define PCI_DEVICE_ID_VIPER 0xfb00
1134 #define PCI_DEVICE_ID_LP10000S 0xfc00
1135 #define PCI_DEVICE_ID_LP11000S 0xfc10
1136 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1137 #define PCI_DEVICE_ID_SAT_S 0xfc40
1138 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1139 #define PCI_DEVICE_ID_HELIOS 0xfd00
1140 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1141 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1142 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1143 #define PCI_DEVICE_ID_HORNET 0xfe05
1144 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1145 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1147 #define JEDEC_ID_ADDRESS 0x0080001c
1148 #define FIREFLY_JEDEC_ID 0x1ACC
1149 #define SUPERFLY_JEDEC_ID 0x0020
1150 #define DRAGONFLY_JEDEC_ID 0x0021
1151 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1152 #define CENTAUR_2G_JEDEC_ID 0x0026
1153 #define CENTAUR_1G_JEDEC_ID 0x0028
1154 #define PEGASUS_ORION_JEDEC_ID 0x0036
1155 #define PEGASUS_JEDEC_ID 0x0038
1156 #define THOR_JEDEC_ID 0x0012
1157 #define HELIOS_JEDEC_ID 0x0364
1158 #define ZEPHYR_JEDEC_ID 0x0577
1159 #define VIPER_JEDEC_ID 0x4838
1160 #define SATURN_JEDEC_ID 0x1004
1161 #define HORNET_JDEC_ID 0x2057706D
1163 #define JEDEC_ID_MASK 0x0FFFF000
1164 #define JEDEC_ID_SHIFT 12
1165 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1167 typedef struct { /* FireFly BIU registers */
1168 uint32_t hostAtt; /* See definitions for Host Attention
1170 uint32_t chipAtt; /* See definitions for Chip Attention
1172 uint32_t hostStatus; /* See definitions for Host Status register */
1173 uint32_t hostControl; /* See definitions for Host Control register */
1174 uint32_t buiConfig; /* See definitions for BIU configuration
1178 /* IO Register size in bytes */
1179 #define FF_REG_AREA_SIZE 256
1181 /* Host Attention Register */
1183 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1185 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1186 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1187 #define HA_R0ATT 0x00000008 /* Bit 3 */
1188 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1189 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1190 #define HA_R1ATT 0x00000080 /* Bit 7 */
1191 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1192 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1193 #define HA_R2ATT 0x00000800 /* Bit 11 */
1194 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1195 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1196 #define HA_R3ATT 0x00008000 /* Bit 15 */
1197 #define HA_LATT 0x20000000 /* Bit 29 */
1198 #define HA_MBATT 0x40000000 /* Bit 30 */
1199 #define HA_ERATT 0x80000000 /* Bit 31 */
1201 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1202 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1203 #define HA_RXATT 0x00000008 /* Bit 3 */
1204 #define HA_RXMASK 0x0000000f
1206 /* Chip Attention Register */
1208 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1210 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1211 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1212 #define CA_R0ATT 0x00000008 /* Bit 3 */
1213 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1214 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1215 #define CA_R1ATT 0x00000080 /* Bit 7 */
1216 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1217 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1218 #define CA_R2ATT 0x00000800 /* Bit 11 */
1219 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1220 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1221 #define CA_R3ATT 0x00008000 /* Bit 15 */
1222 #define CA_MBATT 0x40000000 /* Bit 30 */
1224 /* Host Status Register */
1226 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1228 #define HS_MBRDY 0x00400000 /* Bit 22 */
1229 #define HS_FFRDY 0x00800000 /* Bit 23 */
1230 #define HS_FFER8 0x01000000 /* Bit 24 */
1231 #define HS_FFER7 0x02000000 /* Bit 25 */
1232 #define HS_FFER6 0x04000000 /* Bit 26 */
1233 #define HS_FFER5 0x08000000 /* Bit 27 */
1234 #define HS_FFER4 0x10000000 /* Bit 28 */
1235 #define HS_FFER3 0x20000000 /* Bit 29 */
1236 #define HS_FFER2 0x40000000 /* Bit 30 */
1237 #define HS_FFER1 0x80000000 /* Bit 31 */
1238 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1239 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1241 /* Host Control Register */
1243 #define HC_REG_OFFSET 12 /* Word offset from register base address */
1245 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1246 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1247 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1248 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1249 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1250 #define HC_INITHBI 0x02000000 /* Bit 25 */
1251 #define HC_INITMB 0x04000000 /* Bit 26 */
1252 #define HC_INITFF 0x08000000 /* Bit 27 */
1253 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1254 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1256 /* Mailbox Commands */
1257 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1258 #define MBX_LOAD_SM 0x01
1259 #define MBX_READ_NV 0x02
1260 #define MBX_WRITE_NV 0x03
1261 #define MBX_RUN_BIU_DIAG 0x04
1262 #define MBX_INIT_LINK 0x05
1263 #define MBX_DOWN_LINK 0x06
1264 #define MBX_CONFIG_LINK 0x07
1265 #define MBX_CONFIG_RING 0x09
1266 #define MBX_RESET_RING 0x0A
1267 #define MBX_READ_CONFIG 0x0B
1268 #define MBX_READ_RCONFIG 0x0C
1269 #define MBX_READ_SPARM 0x0D
1270 #define MBX_READ_STATUS 0x0E
1271 #define MBX_READ_RPI 0x0F
1272 #define MBX_READ_XRI 0x10
1273 #define MBX_READ_REV 0x11
1274 #define MBX_READ_LNK_STAT 0x12
1275 #define MBX_REG_LOGIN 0x13
1276 #define MBX_UNREG_LOGIN 0x14
1277 #define MBX_READ_LA 0x15
1278 #define MBX_CLEAR_LA 0x16
1279 #define MBX_DUMP_MEMORY 0x17
1280 #define MBX_DUMP_CONTEXT 0x18
1281 #define MBX_RUN_DIAGS 0x19
1282 #define MBX_RESTART 0x1A
1283 #define MBX_UPDATE_CFG 0x1B
1284 #define MBX_DOWN_LOAD 0x1C
1285 #define MBX_DEL_LD_ENTRY 0x1D
1286 #define MBX_RUN_PROGRAM 0x1E
1287 #define MBX_SET_MASK 0x20
1288 #define MBX_SET_VARIABLE 0x21
1289 #define MBX_UNREG_D_ID 0x23
1290 #define MBX_KILL_BOARD 0x24
1291 #define MBX_CONFIG_FARP 0x25
1292 #define MBX_BEACON 0x2A
1293 #define MBX_HEARTBEAT 0x31
1294 #define MBX_WRITE_VPARMS 0x32
1295 #define MBX_ASYNCEVT_ENABLE 0x33
1297 #define MBX_PORT_CAPABILITIES 0x3B
1298 #define MBX_PORT_IOV_CONTROL 0x3C
1300 #define MBX_CONFIG_HBQ 0x7C
1301 #define MBX_LOAD_AREA 0x81
1302 #define MBX_RUN_BIU_DIAG64 0x84
1303 #define MBX_CONFIG_PORT 0x88
1304 #define MBX_READ_SPARM64 0x8D
1305 #define MBX_READ_RPI64 0x8F
1306 #define MBX_REG_LOGIN64 0x93
1307 #define MBX_READ_LA64 0x95
1308 #define MBX_REG_VPI 0x96
1309 #define MBX_UNREG_VPI 0x97
1310 #define MBX_REG_VNPID 0x96
1311 #define MBX_UNREG_VNPID 0x97
1313 #define MBX_WRITE_WWN 0x98
1314 #define MBX_SET_DEBUG 0x99
1315 #define MBX_LOAD_EXP_ROM 0x9C
1317 #define MBX_MAX_CMDS 0x9D
1318 #define MBX_SLI2_CMD_MASK 0x80
1322 #define CMD_RCV_SEQUENCE_CX 0x01
1323 #define CMD_XMIT_SEQUENCE_CR 0x02
1324 #define CMD_XMIT_SEQUENCE_CX 0x03
1325 #define CMD_XMIT_BCAST_CN 0x04
1326 #define CMD_XMIT_BCAST_CX 0x05
1327 #define CMD_QUE_RING_BUF_CN 0x06
1328 #define CMD_QUE_XRI_BUF_CX 0x07
1329 #define CMD_IOCB_CONTINUE_CN 0x08
1330 #define CMD_RET_XRI_BUF_CX 0x09
1331 #define CMD_ELS_REQUEST_CR 0x0A
1332 #define CMD_ELS_REQUEST_CX 0x0B
1333 #define CMD_RCV_ELS_REQ_CX 0x0D
1334 #define CMD_ABORT_XRI_CN 0x0E
1335 #define CMD_ABORT_XRI_CX 0x0F
1336 #define CMD_CLOSE_XRI_CN 0x10
1337 #define CMD_CLOSE_XRI_CX 0x11
1338 #define CMD_CREATE_XRI_CR 0x12
1339 #define CMD_CREATE_XRI_CX 0x13
1340 #define CMD_GET_RPI_CN 0x14
1341 #define CMD_XMIT_ELS_RSP_CX 0x15
1342 #define CMD_GET_RPI_CR 0x16
1343 #define CMD_XRI_ABORTED_CX 0x17
1344 #define CMD_FCP_IWRITE_CR 0x18
1345 #define CMD_FCP_IWRITE_CX 0x19
1346 #define CMD_FCP_IREAD_CR 0x1A
1347 #define CMD_FCP_IREAD_CX 0x1B
1348 #define CMD_FCP_ICMND_CR 0x1C
1349 #define CMD_FCP_ICMND_CX 0x1D
1350 #define CMD_FCP_TSEND_CX 0x1F
1351 #define CMD_FCP_TRECEIVE_CX 0x21
1352 #define CMD_FCP_TRSP_CX 0x23
1353 #define CMD_FCP_AUTO_TRSP_CX 0x29
1355 #define CMD_ADAPTER_MSG 0x20
1356 #define CMD_ADAPTER_DUMP 0x22
1358 /* SLI_2 IOCB Command Set */
1360 #define CMD_ASYNC_STATUS 0x7C
1361 #define CMD_RCV_SEQUENCE64_CX 0x81
1362 #define CMD_XMIT_SEQUENCE64_CR 0x82
1363 #define CMD_XMIT_SEQUENCE64_CX 0x83
1364 #define CMD_XMIT_BCAST64_CN 0x84
1365 #define CMD_XMIT_BCAST64_CX 0x85
1366 #define CMD_QUE_RING_BUF64_CN 0x86
1367 #define CMD_QUE_XRI_BUF64_CX 0x87
1368 #define CMD_IOCB_CONTINUE64_CN 0x88
1369 #define CMD_RET_XRI_BUF64_CX 0x89
1370 #define CMD_ELS_REQUEST64_CR 0x8A
1371 #define CMD_ELS_REQUEST64_CX 0x8B
1372 #define CMD_ABORT_MXRI64_CN 0x8C
1373 #define CMD_RCV_ELS_REQ64_CX 0x8D
1374 #define CMD_XMIT_ELS_RSP64_CX 0x95
1375 #define CMD_FCP_IWRITE64_CR 0x98
1376 #define CMD_FCP_IWRITE64_CX 0x99
1377 #define CMD_FCP_IREAD64_CR 0x9A
1378 #define CMD_FCP_IREAD64_CX 0x9B
1379 #define CMD_FCP_ICMND64_CR 0x9C
1380 #define CMD_FCP_ICMND64_CX 0x9D
1381 #define CMD_FCP_TSEND64_CX 0x9F
1382 #define CMD_FCP_TRECEIVE64_CX 0xA1
1383 #define CMD_FCP_TRSP64_CX 0xA3
1385 #define CMD_QUE_XRI64_CX 0xB3
1386 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1387 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1388 #define CMD_IOCB_RET_XRI64_CX 0xB9
1389 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1391 #define CMD_GEN_REQUEST64_CR 0xC2
1392 #define CMD_GEN_REQUEST64_CX 0xC3
1394 /* Unhandled SLI-3 Commands */
1395 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1396 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1397 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1398 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1399 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1400 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1401 #define CMD_IOCB_RET_HBQE64_CN 0xCA
1402 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1403 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1404 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1405 #define CMD_IOCB_LOGENTRY_CN 0x94
1406 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1408 #define CMD_MAX_IOCB_CMD 0xE6
1409 #define CMD_IOCB_MASK 0xff
1411 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1413 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1417 #define MBX_SUCCESS 0
1418 #define MBXERR_NUM_RINGS 1
1419 #define MBXERR_NUM_IOCBS 2
1420 #define MBXERR_IOCBS_EXCEEDED 3
1421 #define MBXERR_BAD_RING_NUMBER 4
1422 #define MBXERR_MASK_ENTRIES_RANGE 5
1423 #define MBXERR_MASKS_EXCEEDED 6
1424 #define MBXERR_BAD_PROFILE 7
1425 #define MBXERR_BAD_DEF_CLASS 8
1426 #define MBXERR_BAD_MAX_RESPONDER 9
1427 #define MBXERR_BAD_MAX_ORIGINATOR 10
1428 #define MBXERR_RPI_REGISTERED 11
1429 #define MBXERR_RPI_FULL 12
1430 #define MBXERR_NO_RESOURCES 13
1431 #define MBXERR_BAD_RCV_LENGTH 14
1432 #define MBXERR_DMA_ERROR 15
1433 #define MBXERR_ERROR 16
1434 #define MBX_NOT_FINISHED 255
1436 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1437 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1439 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1442 * Begin Structure Definitions for Mailbox Commands
1446 #ifdef __BIG_ENDIAN_BITFIELD
1451 #else /* __LITTLE_ENDIAN_BITFIELD */
1460 uint32_t bdeAddress;
1461 #ifdef __BIG_ENDIAN_BITFIELD
1462 uint32_t bdeReserved:4;
1463 uint32_t bdeAddrHigh:4;
1464 uint32_t bdeSize:24;
1465 #else /* __LITTLE_ENDIAN_BITFIELD */
1466 uint32_t bdeSize:24;
1467 uint32_t bdeAddrHigh:4;
1468 uint32_t bdeReserved:4;
1472 struct ulp_bde64 { /* SLI-2 */
1476 #ifdef __BIG_ENDIAN_BITFIELD
1477 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1479 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1480 #else /* __LITTLE_ENDIAN_BITFIELD */
1481 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1482 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1485 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
1486 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
1487 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
1488 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
1489 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
1490 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
1491 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
1498 typedef struct ULP_BDL { /* SLI-2 */
1499 #ifdef __BIG_ENDIAN_BITFIELD
1500 uint32_t bdeFlags:8; /* BDL Flags */
1501 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1502 #else /* __LITTLE_ENDIAN_BITFIELD */
1503 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1504 uint32_t bdeFlags:8; /* BDL Flags */
1507 uint32_t addrLow; /* Address 0:31 */
1508 uint32_t addrHigh; /* Address 32:63 */
1509 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1512 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1515 #ifdef __BIG_ENDIAN_BITFIELD
1517 uint32_t acknowledgment:1;
1519 uint32_t erase_or_prog:1;
1520 uint32_t update_flash:1;
1521 uint32_t update_ram:1;
1523 uint32_t load_cmplt:1;
1524 #else /* __LITTLE_ENDIAN_BITFIELD */
1525 uint32_t load_cmplt:1;
1527 uint32_t update_ram:1;
1528 uint32_t update_flash:1;
1529 uint32_t erase_or_prog:1;
1531 uint32_t acknowledgment:1;
1535 uint32_t dl_to_adr_low;
1536 uint32_t dl_to_adr_high;
1539 uint32_t dl_from_mbx_offset;
1540 struct ulp_bde dl_from_bde;
1541 struct ulp_bde64 dl_from_bde64;
1546 /* Structure for MB Command READ_NVPARM (02) */
1549 uint32_t rsvd1[3]; /* Read as all one's */
1550 uint32_t rsvd2; /* Read as all zero's */
1551 uint32_t portname[2]; /* N_PORT name */
1552 uint32_t nodename[2]; /* NODE name */
1554 #ifdef __BIG_ENDIAN_BITFIELD
1555 uint32_t pref_DID:24;
1556 uint32_t hardAL_PA:8;
1557 #else /* __LITTLE_ENDIAN_BITFIELD */
1558 uint32_t hardAL_PA:8;
1559 uint32_t pref_DID:24;
1562 uint32_t rsvd3[21]; /* Read as all one's */
1565 /* Structure for MB Command WRITE_NVPARMS (03) */
1568 uint32_t rsvd1[3]; /* Must be all one's */
1569 uint32_t rsvd2; /* Must be all zero's */
1570 uint32_t portname[2]; /* N_PORT name */
1571 uint32_t nodename[2]; /* NODE name */
1573 #ifdef __BIG_ENDIAN_BITFIELD
1574 uint32_t pref_DID:24;
1575 uint32_t hardAL_PA:8;
1576 #else /* __LITTLE_ENDIAN_BITFIELD */
1577 uint32_t hardAL_PA:8;
1578 uint32_t pref_DID:24;
1581 uint32_t rsvd3[21]; /* Must be all one's */
1584 /* Structure for MB Command RUN_BIU_DIAG (04) */
1585 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1591 struct ulp_bde xmit_bde;
1592 struct ulp_bde rcv_bde;
1595 struct ulp_bde64 xmit_bde64;
1596 struct ulp_bde64 rcv_bde64;
1601 /* Structure for MB Command INIT_LINK (05) */
1604 #ifdef __BIG_ENDIAN_BITFIELD
1606 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1607 #else /* __LITTLE_ENDIAN_BITFIELD */
1608 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1612 #ifdef __BIG_ENDIAN_BITFIELD
1613 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1615 uint16_t link_flags;
1616 #else /* __LITTLE_ENDIAN_BITFIELD */
1617 uint16_t link_flags;
1619 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1622 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1623 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1624 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1625 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1626 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1627 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1628 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1630 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1631 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1632 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1634 uint32_t link_speed;
1635 #define LINK_SPEED_AUTO 0 /* Auto selection */
1636 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1637 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1638 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1639 #define LINK_SPEED_8G 8 /* 8 Gigabaud */
1640 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1644 /* Structure for MB Command DOWN_LINK (06) */
1650 /* Structure for MB Command CONFIG_LINK (07) */
1653 #ifdef __BIG_ENDIAN_BITFIELD
1656 uint32_t cr_delay:6;
1657 uint32_t cr_count:8;
1660 #else /* __LITTLE_ENDIAN_BITFIELD */
1663 uint32_t cr_count:8;
1664 uint32_t cr_delay:6;
1678 #ifdef __BIG_ENDIAN_BITFIELD
1679 uint32_t rrq_enable:1;
1680 uint32_t rrq_immed:1;
1682 uint32_t ack0_enable:1;
1683 #else /* __LITTLE_ENDIAN_BITFIELD */
1684 uint32_t ack0_enable:1;
1686 uint32_t rrq_immed:1;
1687 uint32_t rrq_enable:1;
1691 /* Structure for MB Command PART_SLIM (08)
1692 * will be removed since SLI1 is no longer supported!
1695 #ifdef __BIG_ENDIAN_BITFIELD
1700 #else /* __LITTLE_ENDIAN_BITFIELD */
1709 #ifdef __BIG_ENDIAN_BITFIELD
1710 uint32_t unused1:24;
1712 #else /* __LITTLE_ENDIAN_BITFIELD */
1714 uint32_t unused1:24;
1717 RING_DEF ringdef[4];
1721 /* Structure for MB Command CONFIG_RING (09) */
1724 #ifdef __BIG_ENDIAN_BITFIELD
1727 uint32_t recvNotify:1;
1732 #else /* __LITTLE_ENDIAN_BITFIELD */
1737 uint32_t recvNotify:1;
1742 #ifdef __BIG_ENDIAN_BITFIELD
1743 uint16_t maxRespXchg;
1744 uint16_t maxOrigXchg;
1745 #else /* __LITTLE_ENDIAN_BITFIELD */
1746 uint16_t maxOrigXchg;
1747 uint16_t maxRespXchg;
1753 /* Structure for MB Command RESET_RING (10) */
1759 /* Structure for MB Command READ_CONFIG (11) */
1762 #ifdef __BIG_ENDIAN_BITFIELD
1765 uint32_t cr_delay:6;
1766 uint32_t cr_count:8;
1769 #else /* __LITTLE_ENDIAN_BITFIELD */
1772 uint32_t cr_count:8;
1773 uint32_t cr_delay:6;
1778 #ifdef __BIG_ENDIAN_BITFIELD
1779 uint32_t topology:8;
1781 #else /* __LITTLE_ENDIAN_BITFIELD */
1783 uint32_t topology:8;
1786 /* Defines for topology (defined previously) */
1787 #ifdef __BIG_ENDIAN_BITFIELD
1792 #else /* __LITTLE_ENDIAN_BITFIELD */
1805 #define LMT_RESERVED 0x000 /* Not used */
1806 #define LMT_1Gb 0x004
1807 #define LMT_2Gb 0x008
1808 #define LMT_4Gb 0x040
1809 #define LMT_8Gb 0x080
1810 #define LMT_10Gb 0x100
1817 uint32_t avail_iocb;
1825 /* Structure for MB Command READ_RCONFIG (12) */
1828 #ifdef __BIG_ENDIAN_BITFIELD
1830 uint32_t recvNotify:1;
1835 #else /* __LITTLE_ENDIAN_BITFIELD */
1840 uint32_t recvNotify:1;
1844 #ifdef __BIG_ENDIAN_BITFIELD
1847 #else /* __LITTLE_ENDIAN_BITFIELD */
1854 #ifdef __BIG_ENDIAN_BITFIELD
1855 uint16_t cmdRingOffset;
1856 uint16_t cmdEntryCnt;
1857 uint16_t rspRingOffset;
1858 uint16_t rspEntryCnt;
1859 uint16_t nextCmdOffset;
1861 uint16_t nextRspOffset;
1863 #else /* __LITTLE_ENDIAN_BITFIELD */
1864 uint16_t cmdEntryCnt;
1865 uint16_t cmdRingOffset;
1866 uint16_t rspEntryCnt;
1867 uint16_t rspRingOffset;
1869 uint16_t nextCmdOffset;
1871 uint16_t nextRspOffset;
1875 /* Structure for MB Command READ_SPARM (13) */
1876 /* Structure for MB Command READ_SPARM64 (0x8D) */
1882 struct ulp_bde sp; /* This BDE points to struct serv_parm
1884 struct ulp_bde64 sp64;
1886 #ifdef __BIG_ENDIAN_BITFIELD
1889 #else /* __LITTLE_ENDIAN_BITFIELD */
1895 /* Structure for MB Command READ_STATUS (14) */
1898 #ifdef __BIG_ENDIAN_BITFIELD
1900 uint32_t clrCounters:1;
1901 uint16_t activeXriCnt;
1902 uint16_t activeRpiCnt;
1903 #else /* __LITTLE_ENDIAN_BITFIELD */
1904 uint32_t clrCounters:1;
1906 uint16_t activeRpiCnt;
1907 uint16_t activeXriCnt;
1910 uint32_t xmitByteCnt;
1911 uint32_t rcvByteCnt;
1912 uint32_t xmitFrameCnt;
1913 uint32_t rcvFrameCnt;
1914 uint32_t xmitSeqCnt;
1916 uint32_t totalOrigExchanges;
1917 uint32_t totalRespExchanges;
1918 uint32_t rcvPbsyCnt;
1919 uint32_t rcvFbsyCnt;
1922 /* Structure for MB Command READ_RPI (15) */
1923 /* Structure for MB Command READ_RPI64 (0x8F) */
1926 #ifdef __BIG_ENDIAN_BITFIELD
1931 #else /* __LITTLE_ENDIAN_BITFIELD */
1940 struct ulp_bde64 sp64;
1945 /* Structure for MB Command READ_XRI (16) */
1948 #ifdef __BIG_ENDIAN_BITFIELD
1965 uint32_t exchOrig:1;
1966 #else /* __LITTLE_ENDIAN_BITFIELD */
1981 uint32_t exchOrig:1;
1987 /* Structure for MB Command READ_REV (17) */
1990 #ifdef __BIG_ENDIAN_BITFIELD
1998 #else /* __LITTLE_ENDIAN_BITFIELD */
2013 #ifdef __BIG_ENDIAN_BITFIELD
2018 uint16_t ProgFixLvl:2;
2019 uint16_t ProgDistType:2;
2021 #else /* __LITTLE_ENDIAN_BITFIELD */
2023 uint16_t ProgDistType:2;
2024 uint16_t ProgFixLvl:2;
2034 #ifdef __BIG_ENDIAN_BITFIELD
2035 uint8_t feaLevelHigh;
2036 uint8_t feaLevelLow;
2039 #else /* __LITTLE_ENDIAN_BITFIELD */
2042 uint8_t feaLevelLow;
2043 uint8_t feaLevelHigh;
2046 uint32_t postKernRev;
2048 uint8_t opFwName[16];
2050 uint8_t sli1FwName[16];
2052 uint8_t sli2FwName[16];
2054 uint32_t RandomData[6];
2057 /* Structure for MB Command READ_LINK_STAT (18) */
2061 uint32_t linkFailureCnt;
2062 uint32_t lossSyncCnt;
2064 uint32_t lossSignalCnt;
2065 uint32_t primSeqErrCnt;
2066 uint32_t invalidXmitWord;
2068 uint32_t primSeqTimeout;
2069 uint32_t elasticOverrun;
2070 uint32_t arbTimeout;
2073 /* Structure for MB Command REG_LOGIN (19) */
2074 /* Structure for MB Command REG_LOGIN64 (0x93) */
2077 #ifdef __BIG_ENDIAN_BITFIELD
2082 #else /* __LITTLE_ENDIAN_BITFIELD */
2091 struct ulp_bde64 sp64;
2094 #ifdef __BIG_ENDIAN_BITFIELD
2097 #else /* __LITTLE_ENDIAN_BITFIELD */
2104 /* Word 30 contents for REG_LOGIN */
2107 #ifdef __BIG_ENDIAN_BITFIELD
2109 uint16_t wd30_class:4;
2111 #else /* __LITTLE_ENDIAN_BITFIELD */
2113 uint16_t wd30_class:4;
2120 /* Structure for MB Command UNREG_LOGIN (20) */
2123 #ifdef __BIG_ENDIAN_BITFIELD
2132 #else /* __LITTLE_ENDIAN_BITFIELD */
2144 /* Structure for MB Command REG_VPI (0x96) */
2146 #ifdef __BIG_ENDIAN_BITFIELD
2155 #else /* __LITTLE_ENDIAN */
2167 /* Structure for MB Command UNREG_VPI (0x97) */
2174 #ifdef __BIG_ENDIAN_BITFIELD
2177 #else /* __LITTLE_ENDIAN */
2183 /* Structure for MB Command UNREG_D_ID (0x23) */
2191 #ifdef __BIG_ENDIAN_BITFIELD
2200 /* Structure for MB Command READ_LA (21) */
2201 /* Structure for MB Command READ_LA64 (0x95) */
2204 uint32_t eventTag; /* Event tag */
2205 #ifdef __BIG_ENDIAN_BITFIELD
2208 uint32_t mm:1; /* Menlo Maintenance mode enabled */
2213 #else /* __LITTLE_ENDIAN_BITFIELD */
2223 #define AT_RESERVED 0x00 /* Reserved - attType */
2224 #define AT_LINK_UP 0x01 /* Link is up */
2225 #define AT_LINK_DOWN 0x02 /* Link is down */
2227 #ifdef __BIG_ENDIAN_BITFIELD
2228 uint8_t granted_AL_PA;
2232 #else /* __LITTLE_ENDIAN_BITFIELD */
2236 uint8_t granted_AL_PA;
2239 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2240 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2241 #define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */
2244 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2246 /* store the LILP AL_PA position map into */
2247 struct ulp_bde64 lilpBde64;
2250 #ifdef __BIG_ENDIAN_BITFIELD
2254 uint32_t DlnkSpeed:8;
2258 #else /* __LITTLE_ENDIAN_BITFIELD */
2262 uint32_t DlnkSpeed:8;
2268 #ifdef __BIG_ENDIAN_BITFIELD
2272 uint32_t UlnkSpeed:8;
2276 #else /* __LITTLE_ENDIAN_BITFIELD */
2280 uint32_t UlnkSpeed:8;
2286 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2287 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2288 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2289 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2290 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2291 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2295 /* Structure for MB Command CLEAR_LA (22) */
2298 uint32_t eventTag; /* Event tag */
2302 /* Structure for MB Command DUMP */
2305 #ifdef __BIG_ENDIAN_BITFIELD
2311 uint32_t entry_index:16;
2312 uint32_t region_id:16;
2313 #else /* __LITTLE_ENDIAN_BITFIELD */
2319 uint32_t region_id:16;
2320 uint32_t entry_index:16;
2325 uint32_t resp_offset;
2328 #define DMP_MEM_REG 0x1
2329 #define DMP_NV_PARAMS 0x2
2331 #define DMP_REGION_VPD 0xe
2332 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2333 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2334 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2336 /* Structure for MB Command UPDATE_CFG (0x1B) */
2338 struct update_cfg_var {
2339 #ifdef __BIG_ENDIAN_BITFIELD
2347 uint32_t entry_length:16;
2348 uint32_t region_id:16;
2349 #else /* __LITTLE_ENDIAN_BITFIELD */
2357 uint32_t region_id:16;
2358 uint32_t entry_length:16;
2363 uint32_t data_offset;
2367 #ifdef __BIG_ENDIAN_BITFIELD
2372 #else /* __LITTLE_ENDIAN */
2381 /* Structure for MB Command CONFIG_HBQ (7c) */
2383 struct config_hbq_var {
2384 #ifdef __BIG_ENDIAN_BITFIELD
2386 uint32_t recvNotify :1; /* Receive Notification */
2387 uint32_t numMask :8; /* # Mask Entries */
2388 uint32_t profile :8; /* Selection Profile */
2390 #else /* __LITTLE_ENDIAN */
2392 uint32_t profile :8; /* Selection Profile */
2393 uint32_t numMask :8; /* # Mask Entries */
2394 uint32_t recvNotify :1; /* Receive Notification */
2398 #ifdef __BIG_ENDIAN_BITFIELD
2401 uint32_t ringMask :4;
2402 #else /* __LITTLE_ENDIAN */
2403 uint32_t ringMask :4;
2408 #ifdef __BIG_ENDIAN_BITFIELD
2409 uint32_t entry_count :16;
2411 uint32_t headerLen :8;
2412 #else /* __LITTLE_ENDIAN */
2413 uint32_t headerLen :8;
2415 uint32_t entry_count :16;
2418 uint32_t hbqaddrLow;
2419 uint32_t hbqaddrHigh;
2421 #ifdef __BIG_ENDIAN_BITFIELD
2423 uint32_t logEntry :1;
2424 #else /* __LITTLE_ENDIAN */
2425 uint32_t logEntry :1;
2429 uint32_t rsvd6; /* w7 */
2430 uint32_t rsvd7; /* w8 */
2431 uint32_t rsvd8; /* w9 */
2433 struct hbq_mask hbqMasks[6];
2437 uint32_t allprofiles[12];
2440 #ifdef __BIG_ENDIAN_BITFIELD
2441 uint32_t seqlenoff :16;
2442 uint32_t maxlen :16;
2443 #else /* __LITTLE_ENDIAN */
2444 uint32_t maxlen :16;
2445 uint32_t seqlenoff :16;
2447 #ifdef __BIG_ENDIAN_BITFIELD
2449 uint32_t seqlenbcnt :4;
2450 #else /* __LITTLE_ENDIAN */
2451 uint32_t seqlenbcnt :4;
2458 #ifdef __BIG_ENDIAN_BITFIELD
2459 uint32_t seqlenoff :16;
2460 uint32_t maxlen :16;
2461 #else /* __LITTLE_ENDIAN */
2462 uint32_t maxlen :16;
2463 uint32_t seqlenoff :16;
2465 #ifdef __BIG_ENDIAN_BITFIELD
2466 uint32_t cmdcodeoff :28;
2468 uint32_t seqlenbcnt :4;
2469 #else /* __LITTLE_ENDIAN */
2470 uint32_t seqlenbcnt :4;
2472 uint32_t cmdcodeoff :28;
2474 uint32_t cmdmatch[8];
2480 #ifdef __BIG_ENDIAN_BITFIELD
2481 uint32_t seqlenoff :16;
2482 uint32_t maxlen :16;
2483 #else /* __LITTLE_ENDIAN */
2484 uint32_t maxlen :16;
2485 uint32_t seqlenoff :16;
2487 #ifdef __BIG_ENDIAN_BITFIELD
2488 uint32_t cmdcodeoff :28;
2490 uint32_t seqlenbcnt :4;
2491 #else /* __LITTLE_ENDIAN */
2492 uint32_t seqlenbcnt :4;
2494 uint32_t cmdcodeoff :28;
2496 uint32_t cmdmatch[8];
2507 /* Structure for MB Command CONFIG_PORT (0x88) */
2509 #ifdef __BIG_ENDIAN_BITFIELD
2514 uint32_t sli_mode : 4;
2515 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2517 #else /* __LITTLE_ENDIAN */
2518 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2520 uint32_t sli_mode : 4;
2527 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2528 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2529 uint32_t hbainit[6];
2531 #ifdef __BIG_ENDIAN_BITFIELD
2532 uint32_t rsvd : 24; /* Reserved */
2533 uint32_t cmv : 1; /* Configure Max VPIs */
2534 uint32_t ccrp : 1; /* Config Command Ring Polling */
2535 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2536 uint32_t chbs : 1; /* Cofigure Host Backing store */
2537 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2538 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2539 uint32_t cmx : 1; /* Configure Max XRIs */
2540 uint32_t cmr : 1; /* Configure Max RPIs */
2541 #else /* __LITTLE_ENDIAN */
2542 uint32_t cmr : 1; /* Configure Max RPIs */
2543 uint32_t cmx : 1; /* Configure Max XRIs */
2544 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2545 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2546 uint32_t chbs : 1; /* Cofigure Host Backing store */
2547 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2548 uint32_t ccrp : 1; /* Config Command Ring Polling */
2549 uint32_t cmv : 1; /* Configure Max VPIs */
2550 uint32_t rsvd : 24; /* Reserved */
2552 #ifdef __BIG_ENDIAN_BITFIELD
2553 uint32_t rsvd2 : 24; /* Reserved */
2554 uint32_t gmv : 1; /* Grant Max VPIs */
2555 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2556 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2557 uint32_t ghbs : 1; /* Grant Host Backing Store */
2558 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2559 uint32_t gerbm : 1; /* Grant ERBM Request */
2560 uint32_t gmx : 1; /* Grant Max XRIs */
2561 uint32_t gmr : 1; /* Grant Max RPIs */
2562 #else /* __LITTLE_ENDIAN */
2563 uint32_t gmr : 1; /* Grant Max RPIs */
2564 uint32_t gmx : 1; /* Grant Max XRIs */
2565 uint32_t gerbm : 1; /* Grant ERBM Request */
2566 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2567 uint32_t ghbs : 1; /* Grant Host Backing Store */
2568 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2569 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2570 uint32_t gmv : 1; /* Grant Max VPIs */
2571 uint32_t rsvd2 : 24; /* Reserved */
2574 #ifdef __BIG_ENDIAN_BITFIELD
2575 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2576 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2577 #else /* __LITTLE_ENDIAN */
2578 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2579 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2582 #ifdef __BIG_ENDIAN_BITFIELD
2583 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2584 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2585 #else /* __LITTLE_ENDIAN */
2586 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2587 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2590 uint32_t rsvd4; /* Reserved */
2592 #ifdef __BIG_ENDIAN_BITFIELD
2593 uint32_t rsvd5 : 16; /* Reserved */
2594 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2595 #else /* __LITTLE_ENDIAN */
2596 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2597 uint32_t rsvd5 : 16; /* Reserved */
2602 /* SLI-2 Port Control Block */
2605 #define SLIMOFF 0x30 /* WORD */
2607 typedef struct _SLI2_RDSC {
2608 uint32_t cmdEntries;
2609 uint32_t cmdAddrLow;
2610 uint32_t cmdAddrHigh;
2612 uint32_t rspEntries;
2613 uint32_t rspAddrLow;
2614 uint32_t rspAddrHigh;
2617 typedef struct _PCB {
2618 #ifdef __BIG_ENDIAN_BITFIELD
2620 #define TYPE_NATIVE_SLI2 0x01;
2622 #define FEATURE_INITIAL_SLI2 0x01;
2625 #else /* __LITTLE_ENDIAN_BITFIELD */
2629 #define FEATURE_INITIAL_SLI2 0x01;
2631 #define TYPE_NATIVE_SLI2 0x01;
2634 uint32_t mailBoxSize;
2636 uint32_t mbAddrHigh;
2638 uint32_t hgpAddrLow;
2639 uint32_t hgpAddrHigh;
2641 uint32_t pgpAddrLow;
2642 uint32_t pgpAddrHigh;
2643 SLI2_RDSC rdsc[MAX_RINGS];
2648 #ifdef __BIG_ENDIAN_BITFIELD
2650 uint32_t discardFarp:1;
2651 uint32_t IPEnable:1;
2652 uint32_t nodeName:1;
2653 uint32_t portName:1;
2654 uint32_t filterEnable:1;
2655 #else /* __LITTLE_ENDIAN_BITFIELD */
2656 uint32_t filterEnable:1;
2657 uint32_t portName:1;
2658 uint32_t nodeName:1;
2659 uint32_t IPEnable:1;
2660 uint32_t discardFarp:1;
2664 uint8_t portname[8]; /* Used to be struct lpfc_name */
2665 uint8_t nodename[8];
2672 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
2675 #ifdef __BIG_ENDIAN_BITFIELD
2677 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2678 #else /* __LITTLE_ENDIAN */
2679 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
2682 } ASYNCEVT_ENABLE_VAR;
2684 /* Union of all Mailbox Command types */
2685 #define MAILBOX_CMD_WSIZE 32
2686 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2689 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2690 * feature/max ring number
2692 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2693 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2694 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2695 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2696 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2697 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2698 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2699 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2700 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2701 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2702 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2703 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2704 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2705 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2706 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2707 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2708 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2709 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2710 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2711 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2712 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2713 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2714 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2715 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2716 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2719 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2720 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
2721 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2722 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2723 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2724 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
2728 * SLI-2 specific structures
2742 uint32_t unused1[16];
2743 struct lpfc_hgp host[MAX_RINGS];
2744 struct lpfc_pgp port[MAX_RINGS];
2748 struct lpfc_hgp host[MAX_RINGS];
2749 uint32_t reserved[8];
2750 uint32_t hbq_put[16];
2754 struct lpfc_pgp port[MAX_RINGS];
2755 uint32_t hbq_get[16];
2758 struct sli3_inb_pgp {
2761 struct lpfc_pgp port[MAX_RINGS];
2762 uint32_t hbq_get[16];
2766 struct sli2_desc s2;
2767 struct sli3_desc s3;
2768 struct sli3_pgp s3_pgp;
2769 struct sli3_inb_pgp s3_inb_pgp;
2773 #ifdef __BIG_ENDIAN_BITFIELD
2776 uint8_t mbxReserved:6;
2778 uint8_t mbxOwner:1; /* Low order bit first word */
2779 #else /* __LITTLE_ENDIAN_BITFIELD */
2780 uint8_t mbxOwner:1; /* Low order bit first word */
2782 uint8_t mbxReserved:6;
2792 * Begin Structure Definitions for IOCB Commands
2796 #ifdef __BIG_ENDIAN_BITFIELD
2800 uint8_t statLocalError;
2801 #else /* __LITTLE_ENDIAN_BITFIELD */
2802 uint8_t statLocalError;
2807 /* statRsn P/F_RJT reason codes */
2808 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2809 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2810 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2811 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2812 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2813 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2814 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2815 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2816 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2817 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2818 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2819 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2820 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2821 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2822 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2823 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
2824 #define RJT_XCHG_ERR 0x11 /* Exchange error */
2825 #define RJT_PROT_ERR 0x12 /* Protocol error */
2826 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2827 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2828 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2829 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2830 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2831 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2832 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2833 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2835 #define IOERR_SUCCESS 0x00 /* statLocalError */
2836 #define IOERR_MISSING_CONTINUE 0x01
2837 #define IOERR_SEQUENCE_TIMEOUT 0x02
2838 #define IOERR_INTERNAL_ERROR 0x03
2839 #define IOERR_INVALID_RPI 0x04
2840 #define IOERR_NO_XRI 0x05
2841 #define IOERR_ILLEGAL_COMMAND 0x06
2842 #define IOERR_XCHG_DROPPED 0x07
2843 #define IOERR_ILLEGAL_FIELD 0x08
2844 #define IOERR_BAD_CONTINUE 0x09
2845 #define IOERR_TOO_MANY_BUFFERS 0x0A
2846 #define IOERR_RCV_BUFFER_WAITING 0x0B
2847 #define IOERR_NO_CONNECTION 0x0C
2848 #define IOERR_TX_DMA_FAILED 0x0D
2849 #define IOERR_RX_DMA_FAILED 0x0E
2850 #define IOERR_ILLEGAL_FRAME 0x0F
2851 #define IOERR_EXTRA_DATA 0x10
2852 #define IOERR_NO_RESOURCES 0x11
2853 #define IOERR_RESERVED 0x12
2854 #define IOERR_ILLEGAL_LENGTH 0x13
2855 #define IOERR_UNSUPPORTED_FEATURE 0x14
2856 #define IOERR_ABORT_IN_PROGRESS 0x15
2857 #define IOERR_ABORT_REQUESTED 0x16
2858 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2859 #define IOERR_LOOP_OPEN_FAILURE 0x18
2860 #define IOERR_RING_RESET 0x19
2861 #define IOERR_LINK_DOWN 0x1A
2862 #define IOERR_CORRUPTED_DATA 0x1B
2863 #define IOERR_CORRUPTED_RPI 0x1C
2864 #define IOERR_OUT_OF_ORDER_DATA 0x1D
2865 #define IOERR_OUT_OF_ORDER_ACK 0x1E
2866 #define IOERR_DUP_FRAME 0x1F
2867 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2868 #define IOERR_BAD_HOST_ADDRESS 0x21
2869 #define IOERR_RCV_HDRBUF_WAITING 0x22
2870 #define IOERR_MISSING_HDR_BUFFER 0x23
2871 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2872 #define IOERR_ABORTMULT_REQUESTED 0x25
2873 #define IOERR_BUFFER_SHORTAGE 0x28
2874 #define IOERR_DEFAULT 0x29
2875 #define IOERR_CNT 0x2A
2877 #define IOERR_DRVR_MASK 0x100
2878 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2879 #define IOERR_SLI_BRESET 0x102
2880 #define IOERR_SLI_ABORTED 0x103
2885 #ifdef __BIG_ENDIAN_BITFIELD
2886 uint8_t Rctl; /* R_CTL field */
2887 uint8_t Type; /* TYPE field */
2888 uint8_t Dfctl; /* DF_CTL field */
2889 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2890 #else /* __LITTLE_ENDIAN_BITFIELD */
2891 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2892 uint8_t Dfctl; /* DF_CTL field */
2893 uint8_t Type; /* TYPE field */
2894 uint8_t Rctl; /* R_CTL field */
2897 #define BC 0x02 /* Broadcast Received - Fctl */
2898 #define SI 0x04 /* Sequence Initiative */
2899 #define LA 0x08 /* Ignore Link Attention state */
2900 #define LS 0x80 /* Last Sequence */
2905 /* IOCB Command template for a generic response */
2907 uint32_t reserved[4];
2911 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2913 struct ulp_bde xrsqbde[2];
2914 uint32_t xrsqRo; /* Starting Relative Offset */
2915 WORD5 w5; /* Header control/status word */
2918 /* IOCB Command template for ELS_REQUEST */
2920 struct ulp_bde elsReq;
2921 struct ulp_bde elsRsp;
2923 #ifdef __BIG_ENDIAN_BITFIELD
2924 uint32_t word4Rsvd:7;
2927 uint32_t word5Rsvd:8;
2928 uint32_t remoteID:24;
2929 #else /* __LITTLE_ENDIAN_BITFIELD */
2932 uint32_t word4Rsvd:7;
2933 uint32_t remoteID:24;
2934 uint32_t word5Rsvd:8;
2938 /* IOCB Command template for RCV_ELS_REQ */
2940 struct ulp_bde elsReq[2];
2943 #ifdef __BIG_ENDIAN_BITFIELD
2944 uint32_t word5Rsvd:8;
2945 uint32_t remoteID:24;
2946 #else /* __LITTLE_ENDIAN_BITFIELD */
2947 uint32_t remoteID:24;
2948 uint32_t word5Rsvd:8;
2952 /* IOCB Command template for ABORT / CLOSE_XRI */
2956 #define ABORT_TYPE_ABTX 0x00000000
2957 #define ABORT_TYPE_ABTS 0x00000001
2959 #ifdef __BIG_ENDIAN_BITFIELD
2960 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2961 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2962 #else /* __LITTLE_ENDIAN_BITFIELD */
2963 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2964 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2968 /* IOCB Command template for ABORT_MXRI64 */
2976 /* IOCB Command template for GET_RPI */
2980 #ifdef __BIG_ENDIAN_BITFIELD
2981 uint32_t word5Rsvd:8;
2982 uint32_t remoteID:24;
2983 #else /* __LITTLE_ENDIAN_BITFIELD */
2984 uint32_t remoteID:24;
2985 uint32_t word5Rsvd:8;
2989 /* IOCB Command template for all FCP Initiator commands */
2991 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2992 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2994 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2997 /* IOCB Command template for all FCP Target commands */
2999 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3000 uint32_t fcpt_Offset;
3001 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3004 /* SLI-2 IOCB structure definitions */
3006 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3009 uint32_t xrsqRo; /* Starting Relative Offset */
3010 WORD5 w5; /* Header control/status word */
3013 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3015 struct ulp_bde64 rcvBde;
3017 uint32_t xrsqRo; /* Starting Relative Offset */
3018 WORD5 w5; /* Header control/status word */
3021 /* IOCB Command template for ELS_REQUEST64 */
3024 #ifdef __BIG_ENDIAN_BITFIELD
3025 uint32_t word4Rsvd:7;
3028 uint32_t word5Rsvd:8;
3029 uint32_t remoteID:24;
3030 #else /* __LITTLE_ENDIAN_BITFIELD */
3033 uint32_t word4Rsvd:7;
3034 uint32_t remoteID:24;
3035 uint32_t word5Rsvd:8;
3039 /* IOCB Command template for GEN_REQUEST64 */
3042 uint32_t xrsqRo; /* Starting Relative Offset */
3043 WORD5 w5; /* Header control/status word */
3046 /* IOCB Command template for RCV_ELS_REQ64 */
3048 struct ulp_bde64 elsReq;
3052 #ifdef __BIG_ENDIAN_BITFIELD
3053 uint32_t word5Rsvd:8;
3054 uint32_t remoteID:24;
3055 #else /* __LITTLE_ENDIAN_BITFIELD */
3056 uint32_t remoteID:24;
3057 uint32_t word5Rsvd:8;
3061 /* IOCB Command template for RCV_SEQ64 */
3063 struct ulp_bde64 elsReq;
3066 #ifdef __BIG_ENDIAN_BITFIELD
3076 #else /* __LITTLE_ENDIAN_BITFIELD */
3089 /* IOCB Command template for all 64 bit FCP Initiator commands */
3093 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3096 /* IOCB Command template for all 64 bit FCP Target commands */
3099 uint32_t fcpt_Offset;
3100 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3103 /* IOCB Command template for Async Status iocb commands */
3107 #ifdef __BIG_ENDIAN_BITFIELD
3108 uint16_t evt_code; /* High order bits word 5 */
3109 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3110 #else /* __LITTLE_ENDIAN_BITFIELD */
3111 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3112 uint16_t evt_code; /* Low order bits word 5 */
3115 #define ASYNC_TEMP_WARN 0x100
3116 #define ASYNC_TEMP_SAFE 0x101
3118 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3119 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3123 #ifdef __BIG_ENDIAN_BITFIELD
3126 #else /* __LITTLE_ENDIAN */
3130 uint32_t word10Rsvd;
3131 uint32_t acc_len; /* accumulated length */
3132 struct ulp_bde64 bde2;
3135 /* Structure used for a single HBQ entry */
3136 struct lpfc_hbq_entry {
3137 struct ulp_bde64 bde;
3138 uint32_t buffer_tag;
3141 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3143 struct lpfc_hbq_entry buff;
3146 } QUE_XRI64_CX_FIELDS;
3148 struct que_xri64cx_ext_fields {
3149 uint32_t iotag64_low;
3150 uint32_t iotag64_high;
3151 uint32_t ebde_count;
3153 struct lpfc_hbq_entry buff[5];
3156 #define LPFC_EXT_DATA_BDE_COUNT 3
3157 struct fcp_irw_ext {
3158 uint32_t io_tag64_low;
3159 uint32_t io_tag64_high;
3160 #ifdef __BIG_ENDIAN_BITFIELD
3165 #else /* __LITTLE_ENDIAN */
3172 struct ulp_bde64 rbde; /* response bde */
3173 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3174 uint8_t icd[32]; /* immediate command data (32 bytes) */
3177 typedef struct _IOCB { /* IOCB structure */
3179 GENERIC_RSP grsp; /* Generic response */
3180 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3181 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3182 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3183 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3184 A_MXRI64 amxri; /* abort multiple xri command overlay */
3185 GET_RPI getrpi; /* GET_RPI template */
3186 FCPI_FIELDS fcpi; /* FCP Initiator template */
3187 FCPT_FIELDS fcpt; /* FCP target template */
3189 /* SLI-2 structures */
3191 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3193 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3194 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3195 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3196 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3197 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3198 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3199 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
3200 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
3201 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
3203 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3207 #ifdef __BIG_ENDIAN_BITFIELD
3208 uint16_t ulpContext; /* High order bits word 6 */
3209 uint16_t ulpIoTag; /* Low order bits word 6 */
3210 #else /* __LITTLE_ENDIAN_BITFIELD */
3211 uint16_t ulpIoTag; /* Low order bits word 6 */
3212 uint16_t ulpContext; /* High order bits word 6 */
3216 #ifdef __BIG_ENDIAN_BITFIELD
3217 uint16_t ulpContext; /* High order bits word 6 */
3218 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3219 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3220 #else /* __LITTLE_ENDIAN_BITFIELD */
3221 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3222 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3223 uint16_t ulpContext; /* High order bits word 6 */
3227 #define ulpContext un1.t1.ulpContext
3228 #define ulpIoTag un1.t1.ulpIoTag
3229 #define ulpIoTag0 un1.t2.ulpIoTag0
3231 #ifdef __BIG_ENDIAN_BITFIELD
3232 uint32_t ulpTimeout:8;
3234 uint32_t ulpFCP2Rcvy:1;
3237 uint32_t ulpClass:3;
3238 uint32_t ulpCommand:8;
3239 uint32_t ulpStatus:4;
3240 uint32_t ulpBdeCount:2;
3242 uint32_t ulpOwner:1; /* Low order bit word 7 */
3243 #else /* __LITTLE_ENDIAN_BITFIELD */
3244 uint32_t ulpOwner:1; /* Low order bit word 7 */
3246 uint32_t ulpBdeCount:2;
3247 uint32_t ulpStatus:4;
3248 uint32_t ulpCommand:8;
3249 uint32_t ulpClass:3;
3252 uint32_t ulpFCP2Rcvy:1;
3254 uint32_t ulpTimeout:8;
3258 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3260 /* words 8-31 used for que_xri_cx iocb */
3261 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
3262 struct fcp_irw_ext fcp_ext;
3263 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3266 #define ulpCt_h ulpXS
3267 #define ulpCt_l ulpFCP2Rcvy
3269 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3270 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3271 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3272 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3273 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3274 #define PARM_NPIV_DID 3
3275 #define CLASS1 0 /* Class 1 */
3276 #define CLASS2 1 /* Class 2 */
3277 #define CLASS3 2 /* Class 3 */
3278 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3280 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3281 #define IOSTAT_FCP_RSP_ERROR 0x1
3282 #define IOSTAT_REMOTE_STOP 0x2
3283 #define IOSTAT_LOCAL_REJECT 0x3
3284 #define IOSTAT_NPORT_RJT 0x4
3285 #define IOSTAT_FABRIC_RJT 0x5
3286 #define IOSTAT_NPORT_BSY 0x6
3287 #define IOSTAT_FABRIC_BSY 0x7
3288 #define IOSTAT_INTERMED_RSP 0x8
3289 #define IOSTAT_LS_RJT 0x9
3290 #define IOSTAT_BA_RJT 0xA
3291 #define IOSTAT_RSVD1 0xB
3292 #define IOSTAT_RSVD2 0xC
3293 #define IOSTAT_RSVD3 0xD
3294 #define IOSTAT_RSVD4 0xE
3295 #define IOSTAT_NEED_BUFFER 0xF
3296 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3297 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3298 #define IOSTAT_CNT 0x11
3303 #define SLI1_SLIM_SIZE (4 * 1024)
3305 /* Up to 498 IOCBs will fit into 16k
3306 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3308 #define SLI2_SLIM_SIZE (64 * 1024)
3310 /* Maximum IOCBs that will fit in SLI2 slim */
3311 #define MAX_SLI2_IOCB 498
3312 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3313 (sizeof(MAILBOX_t) + sizeof(PCB_t)))
3315 /* HBQ entries are 4 words each = 4k */
3316 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3317 lpfc_sli_hbq_count())
3319 struct lpfc_sli2_slim {
3322 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3326 * This function checks PCI device to allow special handling for LC HBAs.
3329 * device : struct pci_dev 's device field
3335 lpfc_is_LC_HBA(unsigned short device)
3337 if ((device == PCI_DEVICE_ID_TFLY) ||
3338 (device == PCI_DEVICE_ID_PFLY) ||
3339 (device == PCI_DEVICE_ID_LP101) ||
3340 (device == PCI_DEVICE_ID_BMID) ||
3341 (device == PCI_DEVICE_ID_BSMB) ||
3342 (device == PCI_DEVICE_ID_ZMID) ||
3343 (device == PCI_DEVICE_ID_ZSMB) ||
3344 (device == PCI_DEVICE_ID_SAT_MID) ||
3345 (device == PCI_DEVICE_ID_SAT_SMB) ||
3346 (device == PCI_DEVICE_ID_RFLY))
3353 * Determine if an IOCB failed because of a link event or firmware reset.
3357 lpfc_error_lost_link(IOCB_t *iocbp)
3359 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3360 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3361 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3362 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3365 #define MENLO_TRANSPORT_TYPE 0xfe
3366 #define MENLO_CONTEXT 0
3368 #define MENLO_TIMEOUT 30
3369 #define SETVAR_MLOMNT 0x103107
3370 #define SETVAR_MLORST 0x103007