2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
18 * NVRAM support routines
22 * qla2x00_lock_nvram_access() -
26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
29 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
31 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
32 data = RD_REG_WORD(®->nvram);
33 while (data & NVR_BUSY) {
35 data = RD_REG_WORD(®->nvram);
39 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
40 RD_REG_WORD(®->u.isp2300.host_semaphore);
42 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
43 while ((data & BIT_0) == 0) {
46 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
47 RD_REG_WORD(®->u.isp2300.host_semaphore);
49 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
55 * qla2x00_unlock_nvram_access() -
59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
61 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
63 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
64 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
65 RD_REG_WORD(®->u.isp2300.host_semaphore);
70 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
71 * request routine to get the word from NVRAM.
73 * @addr: Address in NVRAM to read
75 * Returns the word read from nvram @addr.
78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
85 data = qla2x00_nvram_request(ha, nv_cmd);
91 * qla2x00_write_nvram_word() - Write NVRAM data.
93 * @addr: Address in NVRAM to write
94 * @data: word to program
97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
101 uint32_t nv_cmd, wait_cnt;
102 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
104 qla2x00_nv_write(ha, NVR_DATA_OUT);
105 qla2x00_nv_write(ha, 0);
106 qla2x00_nv_write(ha, 0);
108 for (word = 0; word < 8; word++)
109 qla2x00_nv_write(ha, NVR_DATA_OUT);
111 qla2x00_nv_deselect(ha);
114 nv_cmd = (addr << 16) | NV_WRITE_OP;
117 for (count = 0; count < 27; count++) {
119 qla2x00_nv_write(ha, NVR_DATA_OUT);
121 qla2x00_nv_write(ha, 0);
126 qla2x00_nv_deselect(ha);
128 /* Wait for NVRAM to become ready */
129 WRT_REG_WORD(®->nvram, NVR_SELECT);
130 RD_REG_WORD(®->nvram); /* PCI Posting. */
131 wait_cnt = NVR_WAIT_CNT;
134 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
135 __func__, ha->host_no));
139 word = RD_REG_WORD(®->nvram);
140 } while ((word & NVR_DATA_IN) == 0);
142 qla2x00_nv_deselect(ha);
145 qla2x00_nv_write(ha, NVR_DATA_OUT);
146 for (count = 0; count < 10; count++)
147 qla2x00_nv_write(ha, 0);
149 qla2x00_nv_deselect(ha);
153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
159 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
163 qla2x00_nv_write(ha, NVR_DATA_OUT);
164 qla2x00_nv_write(ha, 0);
165 qla2x00_nv_write(ha, 0);
167 for (word = 0; word < 8; word++)
168 qla2x00_nv_write(ha, NVR_DATA_OUT);
170 qla2x00_nv_deselect(ha);
173 nv_cmd = (addr << 16) | NV_WRITE_OP;
176 for (count = 0; count < 27; count++) {
178 qla2x00_nv_write(ha, NVR_DATA_OUT);
180 qla2x00_nv_write(ha, 0);
185 qla2x00_nv_deselect(ha);
187 /* Wait for NVRAM to become ready */
188 WRT_REG_WORD(®->nvram, NVR_SELECT);
189 RD_REG_WORD(®->nvram); /* PCI Posting. */
192 word = RD_REG_WORD(®->nvram);
194 ret = QLA_FUNCTION_FAILED;
197 } while ((word & NVR_DATA_IN) == 0);
199 qla2x00_nv_deselect(ha);
202 qla2x00_nv_write(ha, NVR_DATA_OUT);
203 for (count = 0; count < 10; count++)
204 qla2x00_nv_write(ha, 0);
206 qla2x00_nv_deselect(ha);
212 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
215 * @nv_cmd: NVRAM command
217 * Bit definitions for NVRAM command:
220 * Bit 25, 24 = opcode
221 * Bit 23-16 = address
222 * Bit 15-0 = write data
224 * Returns the word read from nvram @addr.
227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
230 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
234 /* Send command to NVRAM. */
236 for (cnt = 0; cnt < 11; cnt++) {
238 qla2x00_nv_write(ha, NVR_DATA_OUT);
240 qla2x00_nv_write(ha, 0);
244 /* Read data from NVRAM. */
245 for (cnt = 0; cnt < 16; cnt++) {
246 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
247 RD_REG_WORD(®->nvram); /* PCI Posting. */
250 reg_data = RD_REG_WORD(®->nvram);
251 if (reg_data & NVR_DATA_IN)
253 WRT_REG_WORD(®->nvram, NVR_SELECT);
254 RD_REG_WORD(®->nvram); /* PCI Posting. */
259 WRT_REG_WORD(®->nvram, NVR_DESELECT);
260 RD_REG_WORD(®->nvram); /* PCI Posting. */
267 * qla2x00_nv_write() - Clean NVRAM operations.
271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
273 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
275 WRT_REG_WORD(®->nvram, NVR_DESELECT);
276 RD_REG_WORD(®->nvram); /* PCI Posting. */
281 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
283 * @data: Serial interface selector
286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
288 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
290 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
291 RD_REG_WORD(®->nvram); /* PCI Posting. */
293 WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK |
295 RD_REG_WORD(®->nvram); /* PCI Posting. */
297 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
298 RD_REG_WORD(®->nvram); /* PCI Posting. */
303 * qla2x00_clear_nvram_protection() -
307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
310 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
311 uint32_t word, wait_cnt;
312 uint16_t wprot, wprot_old;
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
329 qla2x00_nv_deselect(ha);
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
338 qla2x00_nv_deselect(ha);
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
347 qla2x00_nv_deselect(ha);
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(®->nvram, NVR_SELECT);
351 RD_REG_WORD(®->nvram); /* PCI Posting. */
352 wait_cnt = NVR_WAIT_CNT;
355 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
356 "ready...\n", __func__,
361 word = RD_REG_WORD(®->nvram);
362 } while ((word & NVR_DATA_IN) == 0);
367 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
375 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
376 uint32_t word, wait_cnt;
378 if (stat != QLA_SUCCESS)
381 /* Set NVRAM write protection. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
389 qla2x00_nv_deselect(ha);
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
398 qla2x00_nv_deselect(ha);
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
407 qla2x00_nv_deselect(ha);
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(®->nvram, NVR_SELECT);
411 RD_REG_WORD(®->nvram); /* PCI Posting. */
412 wait_cnt = NVR_WAIT_CNT;
415 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
416 __func__, ha->host_no));
420 word = RD_REG_WORD(®->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
429 #define OPTROM_BURST_SIZE 0x1000
430 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
432 static inline uint32_t
433 flash_conf_to_access_addr(uint32_t faddr)
435 return FARX_ACCESS_FLASH_CONF | faddr;
438 static inline uint32_t
439 flash_data_to_access_addr(uint32_t faddr)
441 return FARX_ACCESS_FLASH_DATA | faddr;
444 static inline uint32_t
445 nvram_conf_to_access_addr(uint32_t naddr)
447 return FARX_ACCESS_NVRAM_CONF | naddr;
450 static inline uint32_t
451 nvram_data_to_access_addr(uint32_t naddr)
453 return FARX_ACCESS_NVRAM_DATA | naddr;
457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
461 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
463 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
464 /* Wait for READ cycle to complete. */
467 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
468 rval == QLA_SUCCESS; cnt--) {
472 rval = QLA_FUNCTION_TIMEOUT;
476 /* TODO: What happens if we time out? */
478 if (rval == QLA_SUCCESS)
479 data = RD_REG_DWORD(®->flash_data);
485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
490 /* Dword reads to flash. */
491 for (i = 0; i < dwords; i++, faddr++)
492 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
493 flash_data_to_access_addr(faddr)));
499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
503 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
505 WRT_REG_DWORD(®->flash_data, data);
506 RD_REG_DWORD(®->flash_data); /* PCI Posting. */
507 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
508 /* Wait for Write cycle to complete. */
510 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
511 rval == QLA_SUCCESS; cnt--) {
515 rval = QLA_FUNCTION_TIMEOUT;
522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
527 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
529 *flash_id = MSB(ids);
531 /* Check if man_id and flash_id are valid. */
532 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
533 /* Read information using 0x9f opcode
534 * Device ID, Mfg ID would be read in the format:
535 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
536 * Example: ATMEL 0x00 01 45 1F
537 * Extract MFG and Dev ID from last two bytes.
539 ids = qla24xx_read_flash_dword(ha,
540 flash_data_to_access_addr(0xd009f));
542 *flash_id = MSB(ids);
547 qla24xx_unprotect_flash(scsi_qla_host_t *ha)
549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
551 /* Enable flash write. */
552 WRT_REG_DWORD(®->ctrl_status,
553 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
554 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
556 /* Disable flash write-protection. */
557 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
558 /* Some flash parts need an additional zero-write to clear bits.*/
559 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
563 qla24xx_protect_flash(scsi_qla_host_t *ha)
566 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
568 /* Enable flash write-protection and wait for completion. */
569 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
570 for (cnt = 300; cnt &&
571 qla24xx_read_flash_dword(ha,
572 flash_conf_to_access_addr(0x005)) & BIT_0;
577 /* Disable flash write. */
578 WRT_REG_DWORD(®->ctrl_status,
579 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
580 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
584 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
588 uint32_t liter, miter;
589 uint32_t sec_mask, rest_addr, conf_addr;
590 uint32_t fdata, findex;
591 uint8_t man_id, flash_id;
592 dma_addr_t optrom_dma;
598 /* Prepare burst-capable write on supported ISPs. */
599 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
600 dwords > OPTROM_BURST_DWORDS) {
601 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
602 &optrom_dma, GFP_KERNEL);
604 qla_printk(KERN_DEBUG, ha,
605 "Unable to allocate memory for optrom burst write "
606 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
610 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
611 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
612 ha->host_no, man_id, flash_id));
614 conf_addr = flash_conf_to_access_addr(0x03d8);
616 case 0xbf: /* STT flash. */
617 if (flash_id == 0x8e) {
624 if (flash_id == 0x80)
625 conf_addr = flash_conf_to_access_addr(0x0352);
627 case 0x13: /* ST M25P80. */
631 case 0x1f: // Atmel 26DF081A
634 conf_addr = flash_conf_to_access_addr(0x0320);
637 /* Default to 64 kb sector size. */
643 qla24xx_unprotect_flash(ha);
645 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
646 if (man_id == 0x1f) {
648 fdata = findex & sec_mask;
651 fdata = (findex & sec_mask) << 2;
654 /* Are we at the beginning of a sector? */
655 if ((findex & rest_addr) == 0) {
656 /* Do sector unprotect at 4K boundry for Atmel part. */
658 qla24xx_write_flash_dword(ha,
659 flash_conf_to_access_addr(0x0339),
660 (fdata & 0xff00) | ((fdata << 16) &
661 0xff0000) | ((fdata >> 16) & 0xff));
662 ret = qla24xx_write_flash_dword(ha, conf_addr,
663 (fdata & 0xff00) |((fdata << 16) &
664 0xff0000) | ((fdata >> 16) & 0xff));
665 if (ret != QLA_SUCCESS) {
666 DEBUG9(printk("%s(%ld) Unable to flash "
667 "sector: address=%x.\n", __func__,
668 ha->host_no, faddr));
673 /* Go with burst-write. */
674 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
675 /* Copy data to DMA'ble buffer. */
676 for (miter = 0, s = optrom, d = dwptr;
677 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
678 *s = cpu_to_le32(*d);
680 ret = qla2x00_load_ram(ha, optrom_dma,
681 flash_data_to_access_addr(faddr),
682 OPTROM_BURST_DWORDS);
683 if (ret != QLA_SUCCESS) {
684 qla_printk(KERN_WARNING, ha,
685 "Unable to burst-write optrom segment "
686 "(%x/%x/%llx).\n", ret,
687 flash_data_to_access_addr(faddr),
688 (unsigned long long)optrom_dma);
689 qla_printk(KERN_WARNING, ha,
690 "Reverting to slow-write.\n");
692 dma_free_coherent(&ha->pdev->dev,
693 OPTROM_BURST_SIZE, optrom, optrom_dma);
696 liter += OPTROM_BURST_DWORDS - 1;
697 faddr += OPTROM_BURST_DWORDS - 1;
698 dwptr += OPTROM_BURST_DWORDS - 1;
703 ret = qla24xx_write_flash_dword(ha,
704 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
705 if (ret != QLA_SUCCESS) {
706 DEBUG9(printk("%s(%ld) Unable to program flash "
707 "address=%x data=%x.\n", __func__,
708 ha->host_no, faddr, *dwptr));
712 /* Do sector protect at 4K boundry for Atmel part. */
713 if (man_id == 0x1f &&
714 ((faddr & rest_addr) == rest_addr))
715 qla24xx_write_flash_dword(ha,
716 flash_conf_to_access_addr(0x0336),
717 (fdata & 0xff00) | ((fdata << 16) &
718 0xff0000) | ((fdata >> 16) & 0xff));
721 qla24xx_protect_flash(ha);
724 dma_free_coherent(&ha->pdev->dev,
725 OPTROM_BURST_SIZE, optrom, optrom_dma);
731 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
737 /* Word reads to NVRAM via registers. */
738 wptr = (uint16_t *)buf;
739 qla2x00_lock_nvram_access(ha);
740 for (i = 0; i < bytes >> 1; i++, naddr++)
741 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
743 qla2x00_unlock_nvram_access(ha);
749 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
755 /* Dword reads to flash. */
756 dwptr = (uint32_t *)buf;
757 for (i = 0; i < bytes >> 2; i++, naddr++)
758 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
759 nvram_data_to_access_addr(naddr)));
765 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
775 spin_lock_irqsave(&ha->hardware_lock, flags);
776 qla2x00_lock_nvram_access(ha);
778 /* Disable NVRAM write-protection. */
779 stat = qla2x00_clear_nvram_protection(ha);
781 wptr = (uint16_t *)buf;
782 for (i = 0; i < bytes >> 1; i++, naddr++) {
783 qla2x00_write_nvram_word(ha, naddr,
788 /* Enable NVRAM write-protection. */
789 qla2x00_set_nvram_protection(ha, stat);
791 qla2x00_unlock_nvram_access(ha);
792 spin_unlock_irqrestore(&ha->hardware_lock, flags);
798 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
804 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
809 spin_lock_irqsave(&ha->hardware_lock, flags);
810 /* Enable flash write. */
811 WRT_REG_DWORD(®->ctrl_status,
812 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
813 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
815 /* Disable NVRAM write-protection. */
816 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
818 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
821 /* Dword writes to flash. */
822 dwptr = (uint32_t *)buf;
823 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
824 ret = qla24xx_write_flash_dword(ha,
825 nvram_data_to_access_addr(naddr),
826 cpu_to_le32(*dwptr));
827 if (ret != QLA_SUCCESS) {
828 DEBUG9(printk("%s(%ld) Unable to program "
829 "nvram address=%x data=%x.\n", __func__,
830 ha->host_no, naddr, *dwptr));
835 /* Enable NVRAM write-protection. */
836 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
839 /* Disable flash write. */
840 WRT_REG_DWORD(®->ctrl_status,
841 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
842 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
843 spin_unlock_irqrestore(&ha->hardware_lock, flags);
849 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
855 /* Dword reads to flash. */
856 dwptr = (uint32_t *)buf;
857 for (i = 0; i < bytes >> 2; i++, naddr++)
858 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
859 flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr)));
865 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
868 #define RMW_BUFFER_SIZE (64 * 1024)
871 dbuf = vmalloc(RMW_BUFFER_SIZE);
873 return QLA_MEMORY_ALLOC_FAILED;
874 ha->isp_ops->read_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
876 memcpy(dbuf + (naddr << 2), buf, bytes);
877 ha->isp_ops->write_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
885 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
887 if (IS_QLA2322(ha)) {
888 /* Flip all colors. */
889 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
891 ha->beacon_color_state = 0;
892 *pflags = GPIO_LED_ALL_OFF;
895 ha->beacon_color_state = QLA_LED_ALL_ON;
896 *pflags = GPIO_LED_RGA_ON;
899 /* Flip green led only. */
900 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
902 ha->beacon_color_state = 0;
903 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
906 ha->beacon_color_state = QLA_LED_GRN_ON;
907 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
912 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
915 qla2x00_beacon_blink(struct scsi_qla_host *ha)
917 uint16_t gpio_enable;
919 uint16_t led_color = 0;
921 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
923 spin_lock_irqsave(&ha->hardware_lock, flags);
925 /* Save the Original GPIOE. */
926 if (ha->pio_address) {
927 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
928 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
930 gpio_enable = RD_REG_WORD(®->gpioe);
931 gpio_data = RD_REG_WORD(®->gpiod);
934 /* Set the modified gpio_enable values */
935 gpio_enable |= GPIO_LED_MASK;
937 if (ha->pio_address) {
938 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
940 WRT_REG_WORD(®->gpioe, gpio_enable);
941 RD_REG_WORD(®->gpioe);
944 qla2x00_flip_colors(ha, &led_color);
946 /* Clear out any previously set LED color. */
947 gpio_data &= ~GPIO_LED_MASK;
949 /* Set the new input LED color to GPIOD. */
950 gpio_data |= led_color;
952 /* Set the modified gpio_data values */
953 if (ha->pio_address) {
954 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
956 WRT_REG_WORD(®->gpiod, gpio_data);
957 RD_REG_WORD(®->gpiod);
960 spin_unlock_irqrestore(&ha->hardware_lock, flags);
964 qla2x00_beacon_on(struct scsi_qla_host *ha)
966 uint16_t gpio_enable;
969 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
971 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
972 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
974 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
975 qla_printk(KERN_WARNING, ha,
976 "Unable to update fw options (beacon on).\n");
977 return QLA_FUNCTION_FAILED;
981 spin_lock_irqsave(&ha->hardware_lock, flags);
982 if (ha->pio_address) {
983 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
984 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
986 gpio_enable = RD_REG_WORD(®->gpioe);
987 gpio_data = RD_REG_WORD(®->gpiod);
989 gpio_enable |= GPIO_LED_MASK;
991 /* Set the modified gpio_enable values. */
992 if (ha->pio_address) {
993 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
995 WRT_REG_WORD(®->gpioe, gpio_enable);
996 RD_REG_WORD(®->gpioe);
999 /* Clear out previously set LED colour. */
1000 gpio_data &= ~GPIO_LED_MASK;
1001 if (ha->pio_address) {
1002 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1004 WRT_REG_WORD(®->gpiod, gpio_data);
1005 RD_REG_WORD(®->gpiod);
1007 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1010 * Let the per HBA timer kick off the blinking process based on
1011 * the following flags. No need to do anything else now.
1013 ha->beacon_blink_led = 1;
1014 ha->beacon_color_state = 0;
1020 qla2x00_beacon_off(struct scsi_qla_host *ha)
1022 int rval = QLA_SUCCESS;
1024 ha->beacon_blink_led = 0;
1026 /* Set the on flag so when it gets flipped it will be off. */
1028 ha->beacon_color_state = QLA_LED_ALL_ON;
1030 ha->beacon_color_state = QLA_LED_GRN_ON;
1032 ha->isp_ops->beacon_blink(ha); /* This turns green LED off */
1034 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1035 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1037 rval = qla2x00_set_fw_options(ha, ha->fw_options);
1038 if (rval != QLA_SUCCESS)
1039 qla_printk(KERN_WARNING, ha,
1040 "Unable to update fw options (beacon off).\n");
1046 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1048 /* Flip all colors. */
1049 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1051 ha->beacon_color_state = 0;
1055 ha->beacon_color_state = QLA_LED_ALL_ON;
1056 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1061 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1063 uint16_t led_color = 0;
1065 unsigned long flags;
1066 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1068 /* Save the Original GPIOD. */
1069 spin_lock_irqsave(&ha->hardware_lock, flags);
1070 gpio_data = RD_REG_DWORD(®->gpiod);
1072 /* Enable the gpio_data reg for update. */
1073 gpio_data |= GPDX_LED_UPDATE_MASK;
1075 WRT_REG_DWORD(®->gpiod, gpio_data);
1076 gpio_data = RD_REG_DWORD(®->gpiod);
1078 /* Set the color bits. */
1079 qla24xx_flip_colors(ha, &led_color);
1081 /* Clear out any previously set LED color. */
1082 gpio_data &= ~GPDX_LED_COLOR_MASK;
1084 /* Set the new input LED color to GPIOD. */
1085 gpio_data |= led_color;
1087 /* Set the modified gpio_data values. */
1088 WRT_REG_DWORD(®->gpiod, gpio_data);
1089 gpio_data = RD_REG_DWORD(®->gpiod);
1090 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1094 qla24xx_beacon_on(struct scsi_qla_host *ha)
1097 unsigned long flags;
1098 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1100 if (ha->beacon_blink_led == 0) {
1101 /* Enable firmware for update */
1102 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1104 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1105 return QLA_FUNCTION_FAILED;
1107 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1109 qla_printk(KERN_WARNING, ha,
1110 "Unable to update fw options (beacon on).\n");
1111 return QLA_FUNCTION_FAILED;
1114 spin_lock_irqsave(&ha->hardware_lock, flags);
1115 gpio_data = RD_REG_DWORD(®->gpiod);
1117 /* Enable the gpio_data reg for update. */
1118 gpio_data |= GPDX_LED_UPDATE_MASK;
1119 WRT_REG_DWORD(®->gpiod, gpio_data);
1120 RD_REG_DWORD(®->gpiod);
1122 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1125 /* So all colors blink together. */
1126 ha->beacon_color_state = 0;
1128 /* Let the per HBA timer kick off the blinking process. */
1129 ha->beacon_blink_led = 1;
1135 qla24xx_beacon_off(struct scsi_qla_host *ha)
1138 unsigned long flags;
1139 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1141 ha->beacon_blink_led = 0;
1142 ha->beacon_color_state = QLA_LED_ALL_ON;
1144 ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */
1146 /* Give control back to firmware. */
1147 spin_lock_irqsave(&ha->hardware_lock, flags);
1148 gpio_data = RD_REG_DWORD(®->gpiod);
1150 /* Disable the gpio_data reg for update. */
1151 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1152 WRT_REG_DWORD(®->gpiod, gpio_data);
1153 RD_REG_DWORD(®->gpiod);
1154 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1156 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1158 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1159 qla_printk(KERN_WARNING, ha,
1160 "Unable to update fw options (beacon off).\n");
1161 return QLA_FUNCTION_FAILED;
1164 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1165 qla_printk(KERN_WARNING, ha,
1166 "Unable to get fw options (beacon off).\n");
1167 return QLA_FUNCTION_FAILED;
1175 * Flash support routines
1179 * qla2x00_flash_enable() - Setup flash for reading and writing.
1183 qla2x00_flash_enable(scsi_qla_host_t *ha)
1186 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1188 data = RD_REG_WORD(®->ctrl_status);
1189 data |= CSR_FLASH_ENABLE;
1190 WRT_REG_WORD(®->ctrl_status, data);
1191 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1195 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1199 qla2x00_flash_disable(scsi_qla_host_t *ha)
1202 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1204 data = RD_REG_WORD(®->ctrl_status);
1205 data &= ~(CSR_FLASH_ENABLE);
1206 WRT_REG_WORD(®->ctrl_status, data);
1207 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1211 * qla2x00_read_flash_byte() - Reads a byte from flash
1213 * @addr: Address in flash to read
1215 * A word is read from the chip, but, only the lower byte is valid.
1217 * Returns the byte read from flash @addr.
1220 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1223 uint16_t bank_select;
1224 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1226 bank_select = RD_REG_WORD(®->ctrl_status);
1228 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1229 /* Specify 64K address range: */
1230 /* clear out Module Select and Flash Address bits [19:16]. */
1231 bank_select &= ~0xf8;
1232 bank_select |= addr >> 12 & 0xf0;
1233 bank_select |= CSR_FLASH_64K_BANK;
1234 WRT_REG_WORD(®->ctrl_status, bank_select);
1235 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1237 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1238 data = RD_REG_WORD(®->flash_data);
1240 return (uint8_t)data;
1243 /* Setup bit 16 of flash address. */
1244 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1245 bank_select |= CSR_FLASH_64K_BANK;
1246 WRT_REG_WORD(®->ctrl_status, bank_select);
1247 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1248 } else if (((addr & BIT_16) == 0) &&
1249 (bank_select & CSR_FLASH_64K_BANK)) {
1250 bank_select &= ~(CSR_FLASH_64K_BANK);
1251 WRT_REG_WORD(®->ctrl_status, bank_select);
1252 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1255 /* Always perform IO mapped accesses to the FLASH registers. */
1256 if (ha->pio_address) {
1259 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1261 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1264 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1265 } while (data != data2);
1267 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1268 data = qla2x00_debounce_register(®->flash_data);
1271 return (uint8_t)data;
1275 * qla2x00_write_flash_byte() - Write a byte to flash
1277 * @addr: Address in flash to write
1278 * @data: Data to write
1281 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1283 uint16_t bank_select;
1284 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1286 bank_select = RD_REG_WORD(®->ctrl_status);
1287 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1288 /* Specify 64K address range: */
1289 /* clear out Module Select and Flash Address bits [19:16]. */
1290 bank_select &= ~0xf8;
1291 bank_select |= addr >> 12 & 0xf0;
1292 bank_select |= CSR_FLASH_64K_BANK;
1293 WRT_REG_WORD(®->ctrl_status, bank_select);
1294 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1296 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1297 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1298 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1299 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1304 /* Setup bit 16 of flash address. */
1305 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1306 bank_select |= CSR_FLASH_64K_BANK;
1307 WRT_REG_WORD(®->ctrl_status, bank_select);
1308 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1309 } else if (((addr & BIT_16) == 0) &&
1310 (bank_select & CSR_FLASH_64K_BANK)) {
1311 bank_select &= ~(CSR_FLASH_64K_BANK);
1312 WRT_REG_WORD(®->ctrl_status, bank_select);
1313 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1316 /* Always perform IO mapped accesses to the FLASH registers. */
1317 if (ha->pio_address) {
1318 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1319 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1321 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1322 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1323 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1324 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1329 * qla2x00_poll_flash() - Polls flash for completion.
1331 * @addr: Address in flash to poll
1332 * @poll_data: Data to be polled
1333 * @man_id: Flash manufacturer ID
1334 * @flash_id: Flash ID
1336 * This function polls the device until bit 7 of what is read matches data
1337 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1338 * out (a fatal error). The flash book recommeds reading bit 7 again after
1339 * reading bit 5 as a 1.
1341 * Returns 0 on success, else non-zero.
1344 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1345 uint8_t man_id, uint8_t flash_id)
1353 /* Wait for 30 seconds for command to finish. */
1355 for (cnt = 3000000; cnt; cnt--) {
1356 flash_data = qla2x00_read_flash_byte(ha, addr);
1357 if ((flash_data & BIT_7) == poll_data) {
1362 if (man_id != 0x40 && man_id != 0xda) {
1363 if ((flash_data & BIT_5) && cnt > 2)
1374 * qla2x00_program_flash_address() - Programs a flash address
1376 * @addr: Address in flash to program
1377 * @data: Data to be written in flash
1378 * @man_id: Flash manufacturer ID
1379 * @flash_id: Flash ID
1381 * Returns 0 on success, else non-zero.
1384 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1385 uint8_t man_id, uint8_t flash_id)
1387 /* Write Program Command Sequence. */
1388 if (IS_OEM_001(ha)) {
1389 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1390 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1391 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1392 qla2x00_write_flash_byte(ha, addr, data);
1394 if (man_id == 0xda && flash_id == 0xc1) {
1395 qla2x00_write_flash_byte(ha, addr, data);
1399 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1400 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1401 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1402 qla2x00_write_flash_byte(ha, addr, data);
1408 /* Wait for write to complete. */
1409 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1413 * qla2x00_erase_flash() - Erase the flash.
1415 * @man_id: Flash manufacturer ID
1416 * @flash_id: Flash ID
1418 * Returns 0 on success, else non-zero.
1421 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1423 /* Individual Sector Erase Command Sequence */
1424 if (IS_OEM_001(ha)) {
1425 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1426 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1427 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1428 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1429 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1430 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1432 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1433 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1434 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1435 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1436 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1437 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1442 /* Wait for erase to complete. */
1443 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1447 * qla2x00_erase_flash_sector() - Erase a flash sector.
1449 * @addr: Flash sector to erase
1450 * @sec_mask: Sector address mask
1451 * @man_id: Flash manufacturer ID
1452 * @flash_id: Flash ID
1454 * Returns 0 on success, else non-zero.
1457 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1458 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1460 /* Individual Sector Erase Command Sequence */
1461 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1462 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1463 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1464 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1465 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1466 if (man_id == 0x1f && flash_id == 0x13)
1467 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1469 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1473 /* Wait for erase to complete. */
1474 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1478 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1479 * @man_id: Flash manufacturer ID
1480 * @flash_id: Flash ID
1483 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1486 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1487 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1488 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1489 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1490 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1491 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1492 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1493 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1497 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1500 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1501 uint32_t midpoint, ilength;
1504 midpoint = length / 2;
1506 WRT_REG_WORD(®->nvram, 0);
1507 RD_REG_WORD(®->nvram);
1508 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1509 if (ilength == midpoint) {
1510 WRT_REG_WORD(®->nvram, NVR_SELECT);
1511 RD_REG_WORD(®->nvram);
1513 data = qla2x00_read_flash_byte(ha, saddr);
1522 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1525 unsigned long flags;
1526 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1529 scsi_block_requests(ha->host);
1530 ha->isp_ops->disable_intrs(ha);
1531 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1534 spin_lock_irqsave(&ha->hardware_lock, flags);
1535 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
1536 RD_REG_WORD(®->hccr);
1537 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1538 for (cnt = 0; cnt < 30000; cnt++) {
1539 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
1546 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1550 qla2x00_resume_hba(struct scsi_qla_host *ha)
1553 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1554 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1555 qla2xxx_wake_dpc(ha);
1556 qla2x00_wait_for_hba_online(ha);
1557 scsi_unblock_requests(ha->host);
1561 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1562 uint32_t offset, uint32_t length)
1564 uint32_t addr, midpoint;
1566 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1569 qla2x00_suspend_hba(ha);
1572 midpoint = ha->optrom_size / 2;
1574 qla2x00_flash_enable(ha);
1575 WRT_REG_WORD(®->nvram, 0);
1576 RD_REG_WORD(®->nvram); /* PCI Posting. */
1577 for (addr = offset, data = buf; addr < length; addr++, data++) {
1578 if (addr == midpoint) {
1579 WRT_REG_WORD(®->nvram, NVR_SELECT);
1580 RD_REG_WORD(®->nvram); /* PCI Posting. */
1583 *data = qla2x00_read_flash_byte(ha, addr);
1585 qla2x00_flash_disable(ha);
1588 qla2x00_resume_hba(ha);
1594 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1595 uint32_t offset, uint32_t length)
1599 uint8_t man_id, flash_id, sec_number, data;
1601 uint32_t addr, liter, sec_mask, rest_addr;
1602 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1605 qla2x00_suspend_hba(ha);
1610 /* Reset ISP chip. */
1611 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
1612 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1614 /* Go with write. */
1615 qla2x00_flash_enable(ha);
1616 do { /* Loop once to provide quick error exit */
1617 /* Structure of flash memory based on manufacturer */
1618 if (IS_OEM_001(ha)) {
1619 /* OEM variant with special flash part. */
1620 man_id = flash_id = 0;
1625 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1627 case 0x20: /* ST flash. */
1628 if (flash_id == 0xd2 || flash_id == 0xe3) {
1630 * ST m29w008at part - 64kb sector size with
1631 * 32kb,8kb,8kb,16kb sectors at memory address
1639 * ST m29w010b part - 16kb sector size
1640 * Default to 16kb sectors
1645 case 0x40: /* Mostel flash. */
1646 /* Mostel v29c51001 part - 512 byte sector size. */
1650 case 0xbf: /* SST flash. */
1651 /* SST39sf10 part - 4kb sector size. */
1655 case 0xda: /* Winbond flash. */
1656 /* Winbond W29EE011 part - 256 byte sector size. */
1660 case 0xc2: /* Macronix flash. */
1661 /* 64k sector size. */
1662 if (flash_id == 0x38 || flash_id == 0x4f) {
1667 /* Fall through... */
1669 case 0x1f: /* Atmel flash. */
1670 /* 512k sector size. */
1671 if (flash_id == 0x13) {
1672 rest_addr = 0x7fffffff;
1673 sec_mask = 0x80000000;
1676 /* Fall through... */
1678 case 0x01: /* AMD flash. */
1679 if (flash_id == 0x38 || flash_id == 0x40 ||
1681 /* Am29LV081 part - 64kb sector size. */
1682 /* Am29LV002BT part - 64kb sector size. */
1686 } else if (flash_id == 0x3e) {
1688 * Am29LV008b part - 64kb sector size with
1689 * 32kb,8kb,8kb,16kb sector at memory address
1695 } else if (flash_id == 0x20 || flash_id == 0x6e) {
1697 * Am29LV010 part or AM29f010 - 16kb sector
1703 } else if (flash_id == 0x6d) {
1704 /* Am29LV001 part - 8kb sector size. */
1710 /* Default to 16 kb sector size. */
1717 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1718 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1719 rval = QLA_FUNCTION_FAILED;
1724 for (addr = offset, liter = 0; liter < length; liter++,
1727 /* Are we at the beginning of a sector? */
1728 if ((addr & rest_addr) == 0) {
1729 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1730 if (addr >= 0x10000UL) {
1731 if (((addr >> 12) & 0xf0) &&
1733 flash_id == 0x3e) ||
1735 flash_id == 0xd2))) {
1737 if (sec_number == 1) {
1758 } else if (addr == ha->optrom_size / 2) {
1759 WRT_REG_WORD(®->nvram, NVR_SELECT);
1760 RD_REG_WORD(®->nvram);
1763 if (flash_id == 0xda && man_id == 0xc1) {
1764 qla2x00_write_flash_byte(ha, 0x5555,
1766 qla2x00_write_flash_byte(ha, 0x2aaa,
1768 qla2x00_write_flash_byte(ha, 0x5555,
1770 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1772 if (qla2x00_erase_flash_sector(ha,
1773 addr, sec_mask, man_id,
1775 rval = QLA_FUNCTION_FAILED;
1778 if (man_id == 0x01 && flash_id == 0x6d)
1783 if (man_id == 0x01 && flash_id == 0x6d) {
1784 if (sec_number == 1 &&
1785 addr == (rest_addr - 1)) {
1788 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1794 if (qla2x00_program_flash_address(ha, addr, data,
1795 man_id, flash_id)) {
1796 rval = QLA_FUNCTION_FAILED;
1802 qla2x00_flash_disable(ha);
1805 qla2x00_resume_hba(ha);
1811 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1812 uint32_t offset, uint32_t length)
1815 scsi_block_requests(ha->host);
1816 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1819 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1822 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1823 scsi_unblock_requests(ha->host);
1829 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1830 uint32_t offset, uint32_t length)
1835 scsi_block_requests(ha->host);
1836 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1838 /* Go with write. */
1839 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1842 /* Resume HBA -- RISC reset needed. */
1843 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1844 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1845 qla2xxx_wake_dpc(ha);
1846 qla2x00_wait_for_hba_online(ha);
1847 scsi_unblock_requests(ha->host);
1853 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1854 uint32_t offset, uint32_t length)
1857 dma_addr_t optrom_dma;
1860 uint32_t faddr, left, burst;
1864 if (length < OPTROM_BURST_SIZE)
1867 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1868 &optrom_dma, GFP_KERNEL);
1870 qla_printk(KERN_DEBUG, ha,
1871 "Unable to allocate memory for optrom burst read "
1872 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1878 faddr = offset >> 2;
1880 burst = OPTROM_BURST_DWORDS;
1885 rval = qla2x00_dump_ram(ha, optrom_dma,
1886 flash_data_to_access_addr(faddr), burst);
1888 qla_printk(KERN_WARNING, ha,
1889 "Unable to burst-read optrom segment "
1890 "(%x/%x/%llx).\n", rval,
1891 flash_data_to_access_addr(faddr),
1892 (unsigned long long)optrom_dma);
1893 qla_printk(KERN_WARNING, ha,
1894 "Reverting to slow-read.\n");
1896 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1897 optrom, optrom_dma);
1901 memcpy(pbuf, optrom, burst * 4);
1908 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
1914 return qla24xx_read_optrom_data(ha, buf, offset, length);
1918 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1920 * @pcids: Pointer to the FCODE PCI data structure
1922 * The process of retrieving the FCODE version information is at best
1923 * described as interesting.
1925 * Within the first 100h bytes of the image an ASCII string is present
1926 * which contains several pieces of information including the FCODE
1927 * version. Unfortunately it seems the only reliable way to retrieve
1928 * the version is by scanning for another sentinel within the string,
1929 * the FCODE build date:
1931 * ... 2.00.02 10/17/02 ...
1933 * Returns QLA_SUCCESS on successful retrieval of version.
1936 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
1938 int ret = QLA_FUNCTION_FAILED;
1939 uint32_t istart, iend, iter, vend;
1940 uint8_t do_next, rbyte, *vbyte;
1942 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1944 /* Skip the PCI data structure. */
1946 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
1947 qla2x00_read_flash_byte(ha, pcids + 0x0A));
1948 iend = istart + 0x100;
1950 /* Scan for the sentinel date string...eeewww. */
1953 while ((iter < iend) && !do_next) {
1955 if (qla2x00_read_flash_byte(ha, iter) == '/') {
1956 if (qla2x00_read_flash_byte(ha, iter + 2) ==
1959 else if (qla2x00_read_flash_byte(ha,
1967 /* Backtrack to previous ' ' (space). */
1969 while ((iter > istart) && !do_next) {
1971 if (qla2x00_read_flash_byte(ha, iter) == ' ')
1978 * Mark end of version tag, and find previous ' ' (space) or
1979 * string length (recent FCODE images -- major hack ahead!!!).
1983 while ((iter > istart) && !do_next) {
1985 rbyte = qla2x00_read_flash_byte(ha, iter);
1986 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
1992 /* Mark beginning of version tag, and copy data. */
1994 if ((vend - iter) &&
1995 ((vend - iter) < sizeof(ha->fcode_revision))) {
1996 vbyte = ha->fcode_revision;
1997 while (iter <= vend) {
1998 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2005 if (ret != QLA_SUCCESS)
2006 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2010 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2012 int ret = QLA_SUCCESS;
2013 uint8_t code_type, last_image;
2014 uint32_t pcihdr, pcids;
2018 if (!ha->pio_address || !mbuf)
2019 return QLA_FUNCTION_FAILED;
2021 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2022 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2023 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2024 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2026 qla2x00_flash_enable(ha);
2028 /* Begin with first PCI expansion ROM header. */
2032 /* Verify PCI expansion ROM header. */
2033 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2034 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2036 DEBUG2(printk("scsi(%ld): No matching ROM "
2037 "signature.\n", ha->host_no));
2038 ret = QLA_FUNCTION_FAILED;
2042 /* Locate PCI data structure. */
2044 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2045 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2047 /* Validate signature of PCI data structure. */
2048 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2049 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2050 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2051 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2052 /* Incorrect header. */
2053 DEBUG2(printk("%s(): PCI data struct not found "
2054 "pcir_adr=%x.\n", __func__, pcids));
2055 ret = QLA_FUNCTION_FAILED;
2060 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2061 switch (code_type) {
2062 case ROM_CODE_TYPE_BIOS:
2063 /* Intel x86, PC-AT compatible. */
2064 ha->bios_revision[0] =
2065 qla2x00_read_flash_byte(ha, pcids + 0x12);
2066 ha->bios_revision[1] =
2067 qla2x00_read_flash_byte(ha, pcids + 0x13);
2068 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2069 ha->bios_revision[1], ha->bios_revision[0]));
2071 case ROM_CODE_TYPE_FCODE:
2072 /* Open Firmware standard for PCI (FCode). */
2074 qla2x00_get_fcode_version(ha, pcids);
2076 case ROM_CODE_TYPE_EFI:
2077 /* Extensible Firmware Interface (EFI). */
2078 ha->efi_revision[0] =
2079 qla2x00_read_flash_byte(ha, pcids + 0x12);
2080 ha->efi_revision[1] =
2081 qla2x00_read_flash_byte(ha, pcids + 0x13);
2082 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2083 ha->efi_revision[1], ha->efi_revision[0]));
2086 DEBUG2(printk("%s(): Unrecognized code type %x at "
2087 "pcids %x.\n", __func__, code_type, pcids));
2091 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2093 /* Locate next PCI expansion ROM. */
2094 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2095 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2096 } while (!last_image);
2098 if (IS_QLA2322(ha)) {
2099 /* Read firmware image information. */
2100 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2102 memset(dbyte, 0, 8);
2103 dcode = (uint16_t *)dbyte;
2105 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
2107 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2108 __func__, ha->host_no));
2109 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2111 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2112 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2113 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2115 DEBUG2(printk("%s(): Unrecognized fw revision at "
2116 "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
2118 /* values are in big endian */
2119 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2120 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2121 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2125 qla2x00_flash_disable(ha);
2131 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2133 int ret = QLA_SUCCESS;
2134 uint32_t pcihdr, pcids;
2137 uint8_t code_type, last_image;
2141 return QLA_FUNCTION_FAILED;
2143 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2144 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2145 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2146 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2150 /* Begin with first PCI expansion ROM header. */
2154 /* Verify PCI expansion ROM header. */
2155 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2156 bcode = mbuf + (pcihdr % 4);
2157 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2159 DEBUG2(printk("scsi(%ld): No matching ROM "
2160 "signature.\n", ha->host_no));
2161 ret = QLA_FUNCTION_FAILED;
2165 /* Locate PCI data structure. */
2166 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2168 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2169 bcode = mbuf + (pcihdr % 4);
2171 /* Validate signature of PCI data structure. */
2172 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2173 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2174 /* Incorrect header. */
2175 DEBUG2(printk("%s(): PCI data struct not found "
2176 "pcir_adr=%x.\n", __func__, pcids));
2177 ret = QLA_FUNCTION_FAILED;
2182 code_type = bcode[0x14];
2183 switch (code_type) {
2184 case ROM_CODE_TYPE_BIOS:
2185 /* Intel x86, PC-AT compatible. */
2186 ha->bios_revision[0] = bcode[0x12];
2187 ha->bios_revision[1] = bcode[0x13];
2188 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2189 ha->bios_revision[1], ha->bios_revision[0]));
2191 case ROM_CODE_TYPE_FCODE:
2192 /* Open Firmware standard for PCI (FCode). */
2193 ha->fcode_revision[0] = bcode[0x12];
2194 ha->fcode_revision[1] = bcode[0x13];
2195 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2196 ha->fcode_revision[1], ha->fcode_revision[0]));
2198 case ROM_CODE_TYPE_EFI:
2199 /* Extensible Firmware Interface (EFI). */
2200 ha->efi_revision[0] = bcode[0x12];
2201 ha->efi_revision[1] = bcode[0x13];
2202 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2203 ha->efi_revision[1], ha->efi_revision[0]));
2206 DEBUG2(printk("%s(): Unrecognized code type %x at "
2207 "pcids %x.\n", __func__, code_type, pcids));
2211 last_image = bcode[0x15] & BIT_7;
2213 /* Locate next PCI expansion ROM. */
2214 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2215 } while (!last_image);
2217 /* Read firmware image information. */
2218 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2221 qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2222 for (i = 0; i < 4; i++)
2223 dcode[i] = be32_to_cpu(dcode[i]);
2225 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2226 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2227 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2229 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2230 __func__, FA_RISC_CODE_ADDR));
2232 ha->fw_revision[0] = dcode[0];
2233 ha->fw_revision[1] = dcode[1];
2234 ha->fw_revision[2] = dcode[2];
2235 ha->fw_revision[3] = dcode[3];
2242 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata)
2244 uint32_t d[2], faddr;
2246 /* Locate first empty entry. */
2248 if (ha->hw_event_ptr >=
2249 ha->hw_event_start + FA_HW_EVENT_SIZE) {
2250 DEBUG2(qla_printk(KERN_WARNING, ha,
2251 "HW event -- Log Full!\n"));
2252 return QLA_MEMORY_ALLOC_FAILED;
2255 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2);
2256 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2257 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2258 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2259 d[1] == __constant_cpu_to_le32(0xffffffff)) {
2260 qla24xx_unprotect_flash(ha);
2262 qla24xx_write_flash_dword(ha, faddr++,
2263 cpu_to_le32(jiffies));
2264 qla24xx_write_flash_dword(ha, faddr++, 0);
2265 qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2266 qla24xx_write_flash_dword(ha, faddr++, *fdata);
2268 qla24xx_protect_flash(ha);
2276 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1,
2277 uint16_t d2, uint16_t d3)
2279 #define QMARK(a, b, c, d) \
2280 cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2283 uint32_t marker[2], fdata[4];
2285 if (ha->hw_event_start == 0)
2286 return QLA_FUNCTION_FAILED;
2288 DEBUG2(qla_printk(KERN_WARNING, ha,
2289 "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2291 /* If marker not already found, locate or write. */
2292 if (!ha->flags.hw_event_marker_found) {
2293 /* Create marker. */
2294 marker[0] = QMARK('L', ha->fw_major_version,
2295 ha->fw_minor_version, ha->fw_subminor_version);
2296 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2297 QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2299 /* Locate marker. */
2300 ha->hw_event_ptr = ha->hw_event_start;
2302 qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr,
2304 if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2305 fdata[1] == __constant_cpu_to_le32(0xffffffff))
2307 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2308 if (ha->hw_event_ptr >=
2309 ha->hw_event_start + FA_HW_EVENT_SIZE) {
2310 DEBUG2(qla_printk(KERN_WARNING, ha,
2311 "HW event -- Log Full!\n"));
2312 return QLA_MEMORY_ALLOC_FAILED;
2314 if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2315 ha->flags.hw_event_marker_found = 1;
2319 /* No marker, write it. */
2320 if (!ha->flags.hw_event_marker_found) {
2321 rval = qla2xxx_hw_event_store(ha, marker);
2322 if (rval != QLA_SUCCESS) {
2323 DEBUG2(qla_printk(KERN_WARNING, ha,
2324 "HW event -- Failed marker write=%x.!\n",
2328 ha->flags.hw_event_marker_found = 1;
2333 fdata[0] = cpu_to_le32(code << 16 | d1);
2334 fdata[1] = cpu_to_le32(d2 << 16 | d3);
2335 rval = qla2xxx_hw_event_store(ha, fdata);
2336 if (rval != QLA_SUCCESS) {
2337 DEBUG2(qla_printk(KERN_WARNING, ha,
2338 "HW event -- Failed error write=%x.!\n",