2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.04"
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
76 PDC_RESET = (1 << 11), /* HDMA reset */
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI,
83 struct pdc_port_priv {
88 struct pdc_host_priv {
92 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
93 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
94 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
95 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
96 static void pdc_eng_timeout(struct ata_port *ap);
97 static int pdc_port_start(struct ata_port *ap);
98 static void pdc_port_stop(struct ata_port *ap);
99 static void pdc_pata_phy_reset(struct ata_port *ap);
100 static void pdc_sata_phy_reset(struct ata_port *ap);
101 static void pdc_qc_prep(struct ata_queued_cmd *qc);
102 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
103 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104 static void pdc_irq_clear(struct ata_port *ap);
105 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
106 static void pdc_host_stop(struct ata_host_set *host_set);
109 static struct scsi_host_template pdc_ata_sht = {
110 .module = THIS_MODULE,
112 .ioctl = ata_scsi_ioctl,
113 .queuecommand = ata_scsi_queuecmd,
114 .can_queue = ATA_DEF_QUEUE,
115 .this_id = ATA_SHT_THIS_ID,
116 .sg_tablesize = LIBATA_MAX_PRD,
117 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
118 .emulated = ATA_SHT_EMULATED,
119 .use_clustering = ATA_SHT_USE_CLUSTERING,
120 .proc_name = DRV_NAME,
121 .dma_boundary = ATA_DMA_BOUNDARY,
122 .slave_configure = ata_scsi_slave_config,
123 .bios_param = ata_std_bios_param,
126 static const struct ata_port_operations pdc_sata_ops = {
127 .port_disable = ata_port_disable,
128 .tf_load = pdc_tf_load_mmio,
129 .tf_read = ata_tf_read,
130 .check_status = ata_check_status,
131 .exec_command = pdc_exec_command_mmio,
132 .dev_select = ata_std_dev_select,
134 .phy_reset = pdc_sata_phy_reset,
136 .qc_prep = pdc_qc_prep,
137 .qc_issue = pdc_qc_issue_prot,
138 .eng_timeout = pdc_eng_timeout,
139 .irq_handler = pdc_interrupt,
140 .irq_clear = pdc_irq_clear,
142 .scr_read = pdc_sata_scr_read,
143 .scr_write = pdc_sata_scr_write,
144 .port_start = pdc_port_start,
145 .port_stop = pdc_port_stop,
146 .host_stop = pdc_host_stop,
149 static const struct ata_port_operations pdc_pata_ops = {
150 .port_disable = ata_port_disable,
151 .tf_load = pdc_tf_load_mmio,
152 .tf_read = ata_tf_read,
153 .check_status = ata_check_status,
154 .exec_command = pdc_exec_command_mmio,
155 .dev_select = ata_std_dev_select,
157 .phy_reset = pdc_pata_phy_reset,
159 .qc_prep = pdc_qc_prep,
160 .qc_issue = pdc_qc_issue_prot,
161 .eng_timeout = pdc_eng_timeout,
162 .irq_handler = pdc_interrupt,
163 .irq_clear = pdc_irq_clear,
165 .port_start = pdc_port_start,
166 .port_stop = pdc_port_stop,
167 .host_stop = pdc_host_stop,
170 static const struct ata_port_info pdc_port_info[] = {
174 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
175 .pio_mask = 0x1f, /* pio0-4 */
176 .mwdma_mask = 0x07, /* mwdma0-2 */
177 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
178 .port_ops = &pdc_sata_ops,
184 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
185 .pio_mask = 0x1f, /* pio0-4 */
186 .mwdma_mask = 0x07, /* mwdma0-2 */
187 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
188 .port_ops = &pdc_sata_ops,
194 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
195 .pio_mask = 0x1f, /* pio0-4 */
196 .mwdma_mask = 0x07, /* mwdma0-2 */
197 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
198 .port_ops = &pdc_pata_ops,
204 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
205 .pio_mask = 0x1f, /* pio0-4 */
206 .mwdma_mask = 0x07, /* mwdma0-2 */
207 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
208 .port_ops = &pdc_sata_ops,
214 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
215 .pio_mask = 0x1f, /* pio0-4 */
216 .mwdma_mask = 0x07, /* mwdma0-2 */
217 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
218 .port_ops = &pdc_sata_ops,
224 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
225 .pio_mask = 0x1f, /* pio0-4 */
226 .mwdma_mask = 0x07, /* mwdma0-2 */
227 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
228 .port_ops = &pdc_sata_ops,
232 static const struct pci_device_id pdc_ata_pci_tbl[] = {
233 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
235 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
237 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
239 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
241 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
243 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
245 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
247 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
249 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
252 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
254 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
256 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
258 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
270 { } /* terminate list */
274 static struct pci_driver pdc_ata_pci_driver = {
276 .id_table = pdc_ata_pci_tbl,
277 .probe = pdc_ata_init_one,
278 .remove = ata_pci_remove_one,
282 static int pdc_port_start(struct ata_port *ap)
284 struct device *dev = ap->host_set->dev;
285 struct pdc_port_priv *pp;
288 rc = ata_port_start(ap);
292 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
298 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
304 ap->private_data = pp;
316 static void pdc_port_stop(struct ata_port *ap)
318 struct device *dev = ap->host_set->dev;
319 struct pdc_port_priv *pp = ap->private_data;
321 ap->private_data = NULL;
322 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
328 static void pdc_host_stop(struct ata_host_set *host_set)
330 struct pdc_host_priv *hp = host_set->private_data;
332 ata_pci_host_stop(host_set);
338 static void pdc_reset_port(struct ata_port *ap)
340 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
344 for (i = 11; i > 0; i--) {
357 readl(mmio); /* flush */
360 static void pdc_sata_phy_reset(struct ata_port *ap)
366 static void pdc_pata_phy_reset(struct ata_port *ap)
368 /* FIXME: add cable detect. Don't assume 40-pin cable */
369 ap->cbl = ATA_CBL_PATA40;
370 ap->udma_mask &= ATA_UDMA_MASK_40C;
377 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
379 if (sc_reg > SCR_CONTROL)
381 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
385 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
388 if (sc_reg > SCR_CONTROL)
390 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
393 static void pdc_qc_prep(struct ata_queued_cmd *qc)
395 struct pdc_port_priv *pp = qc->ap->private_data;
400 switch (qc->tf.protocol) {
405 case ATA_PROT_NODATA:
406 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
407 qc->dev->devno, pp->pkt);
409 if (qc->tf.flags & ATA_TFLAG_LBA48)
410 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
412 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
414 pdc_pkt_footer(&qc->tf, pp->pkt, i);
422 static void pdc_eng_timeout(struct ata_port *ap)
424 struct ata_host_set *host_set = ap->host_set;
426 struct ata_queued_cmd *qc;
431 spin_lock_irqsave(&host_set->lock, flags);
433 qc = ata_qc_from_tag(ap, ap->active_tag);
435 switch (qc->tf.protocol) {
437 case ATA_PROT_NODATA:
438 ata_port_printk(ap, KERN_ERR, "command timeout\n");
439 drv_stat = ata_wait_idle(ap);
440 qc->err_mask |= __ac_err_mask(drv_stat);
444 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
446 ata_port_printk(ap, KERN_ERR,
447 "unknown timeout, cmd 0x%x stat 0x%x\n",
448 qc->tf.command, drv_stat);
450 qc->err_mask |= ac_err_mask(drv_stat);
454 spin_unlock_irqrestore(&host_set->lock, flags);
455 ata_eh_qc_complete(qc);
459 static inline unsigned int pdc_host_intr( struct ata_port *ap,
460 struct ata_queued_cmd *qc)
462 unsigned int handled = 0;
464 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
467 if (tmp & PDC_ERR_MASK) {
468 qc->err_mask |= AC_ERR_DEV;
472 switch (qc->tf.protocol) {
474 case ATA_PROT_NODATA:
475 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
481 ap->stats.idle_irq++;
488 static void pdc_irq_clear(struct ata_port *ap)
490 struct ata_host_set *host_set = ap->host_set;
491 void __iomem *mmio = host_set->mmio_base;
493 readl(mmio + PDC_INT_SEQMASK);
496 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
498 struct ata_host_set *host_set = dev_instance;
502 unsigned int handled = 0;
503 void __iomem *mmio_base;
507 if (!host_set || !host_set->mmio_base) {
508 VPRINTK("QUICK EXIT\n");
512 mmio_base = host_set->mmio_base;
514 /* reading should also clear interrupts */
515 mask = readl(mmio_base + PDC_INT_SEQMASK);
517 if (mask == 0xffffffff) {
518 VPRINTK("QUICK EXIT 2\n");
522 spin_lock(&host_set->lock);
524 mask &= 0xffff; /* only 16 tags possible */
526 VPRINTK("QUICK EXIT 3\n");
530 writel(mask, mmio_base + PDC_INT_SEQMASK);
532 for (i = 0; i < host_set->n_ports; i++) {
533 VPRINTK("port %u\n", i);
534 ap = host_set->ports[i];
535 tmp = mask & (1 << (i + 1));
537 !(ap->flags & (ATA_FLAG_DISABLED | ATA_FLAG_NOINTR))) {
538 struct ata_queued_cmd *qc;
540 qc = ata_qc_from_tag(ap, ap->active_tag);
541 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
542 handled += pdc_host_intr(ap, qc);
549 spin_unlock(&host_set->lock);
550 return IRQ_RETVAL(handled);
553 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
555 struct ata_port *ap = qc->ap;
556 struct pdc_port_priv *pp = ap->private_data;
557 unsigned int port_no = ap->port_no;
558 u8 seq = (u8) (port_no + 1);
560 VPRINTK("ENTER, ap %p\n", ap);
562 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
563 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
566 wmb(); /* flush PRD, pkt writes */
567 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
568 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
571 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
573 switch (qc->tf.protocol) {
575 case ATA_PROT_NODATA:
576 pdc_packet_start(qc);
579 case ATA_PROT_ATAPI_DMA:
587 return ata_qc_issue_prot(qc);
590 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
592 WARN_ON (tf->protocol == ATA_PROT_DMA ||
593 tf->protocol == ATA_PROT_NODATA);
598 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
600 WARN_ON (tf->protocol == ATA_PROT_DMA ||
601 tf->protocol == ATA_PROT_NODATA);
602 ata_exec_command(ap, tf);
606 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
608 port->cmd_addr = base;
609 port->data_addr = base;
611 port->error_addr = base + 0x4;
612 port->nsect_addr = base + 0x8;
613 port->lbal_addr = base + 0xc;
614 port->lbam_addr = base + 0x10;
615 port->lbah_addr = base + 0x14;
616 port->device_addr = base + 0x18;
618 port->status_addr = base + 0x1c;
619 port->altstatus_addr =
620 port->ctl_addr = base + 0x38;
624 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
626 void __iomem *mmio = pe->mmio_base;
627 struct pdc_host_priv *hp = pe->private_data;
628 int hotplug_offset = hp->hotplug_offset;
632 * Except for the hotplug stuff, this is voodoo from the
633 * Promise driver. Label this entire section
634 * "TODO: figure out why we do this"
637 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
638 tmp = readl(mmio + PDC_FLASH_CTL);
639 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
640 writel(tmp, mmio + PDC_FLASH_CTL);
642 /* clear plug/unplug flags for all ports */
643 tmp = readl(mmio + hotplug_offset);
644 writel(tmp | 0xff, mmio + hotplug_offset);
646 /* mask plug/unplug ints */
647 tmp = readl(mmio + hotplug_offset);
648 writel(tmp | 0xff0000, mmio + hotplug_offset);
650 /* reduce TBG clock to 133 Mhz. */
651 tmp = readl(mmio + PDC_TBG_MODE);
652 tmp &= ~0x30000; /* clear bit 17, 16*/
653 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
654 writel(tmp, mmio + PDC_TBG_MODE);
656 readl(mmio + PDC_TBG_MODE); /* flush */
659 /* adjust slew rate control register. */
660 tmp = readl(mmio + PDC_SLEW_CTL);
661 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
662 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
663 writel(tmp, mmio + PDC_SLEW_CTL);
666 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
668 static int printed_version;
669 struct ata_probe_ent *probe_ent = NULL;
670 struct pdc_host_priv *hp;
672 void __iomem *mmio_base;
673 unsigned int board_idx = (unsigned int) ent->driver_data;
674 int pci_dev_busy = 0;
677 if (!printed_version++)
678 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
680 rc = pci_enable_device(pdev);
684 rc = pci_request_regions(pdev, DRV_NAME);
690 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
692 goto err_out_regions;
693 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
695 goto err_out_regions;
697 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
698 if (probe_ent == NULL) {
700 goto err_out_regions;
703 probe_ent->dev = pci_dev_to_dev(pdev);
704 INIT_LIST_HEAD(&probe_ent->node);
706 mmio_base = pci_iomap(pdev, 3, 0);
707 if (mmio_base == NULL) {
709 goto err_out_free_ent;
711 base = (unsigned long) mmio_base;
713 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
716 goto err_out_free_ent;
719 /* Set default hotplug offset */
720 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
721 probe_ent->private_data = hp;
723 probe_ent->sht = pdc_port_info[board_idx].sht;
724 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
725 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
726 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
727 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
728 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
730 probe_ent->irq = pdev->irq;
731 probe_ent->irq_flags = SA_SHIRQ;
732 probe_ent->mmio_base = mmio_base;
734 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
735 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
737 probe_ent->port[0].scr_addr = base + 0x400;
738 probe_ent->port[1].scr_addr = base + 0x500;
740 /* notice 4-port boards */
743 /* Override hotplug offset for SATAII150 */
744 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
747 probe_ent->n_ports = 4;
749 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
750 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
752 probe_ent->port[2].scr_addr = base + 0x600;
753 probe_ent->port[3].scr_addr = base + 0x700;
756 /* Override hotplug offset for SATAII150 */
757 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
760 probe_ent->n_ports = 2;
763 probe_ent->n_ports = 2;
766 probe_ent->n_ports = 4;
768 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
769 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
771 probe_ent->port[2].scr_addr = base + 0x600;
772 probe_ent->port[3].scr_addr = base + 0x700;
779 pci_set_master(pdev);
781 /* initialize adapter */
782 pdc_host_init(board_idx, probe_ent);
784 /* FIXME: Need any other frees than hp? */
785 if (!ata_device_add(probe_ent))
795 pci_release_regions(pdev);
798 pci_disable_device(pdev);
803 static int __init pdc_ata_init(void)
805 return pci_module_init(&pdc_ata_pci_driver);
809 static void __exit pdc_ata_exit(void)
811 pci_unregister_driver(&pdc_ata_pci_driver);
815 MODULE_AUTHOR("Jeff Garzik");
816 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
817 MODULE_LICENSE("GPL");
818 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
819 MODULE_VERSION(DRV_VERSION);
821 module_init(pdc_ata_init);
822 module_exit(pdc_ata_exit);