2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support
9 * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make
10 * those work. Enabling those shouldn't be difficult. Basic
11 * structure is all there (in libata-dev tree). If you have any
12 * information about this hardware, please contact me or linux-ide.
13 * Info is needed on...
15 * - How to issue tagged commands and turn on sactive on issue accordingly.
16 * - Where to put an ATAPI command and how to tell the device to send it.
17 * - How to enable/use 64bit.
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2, or (at your option) any
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
27 * General Public License for more details.
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/blkdev.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/dma-mapping.h>
38 #include <scsi/scsi_host.h>
40 #include <linux/libata.h>
43 #define DRV_NAME "sata_sil24"
44 #define DRV_VERSION "0.21" /* Silicon Image's preview driver was 0.10 */
49 * Port request block (PRB) 32 bytes
59 * Scatter gather entry (SGE) 16 bytes
70 struct sil24_port_multiplier {
77 * Global controller registers (128 bytes @ BAR0)
80 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
84 HOST_BIST_CTRL = 0x50,
85 HOST_BIST_PTRN = 0x54,
86 HOST_BIST_STAT = 0x58,
87 HOST_MEM_BIST_STAT = 0x5c,
88 HOST_FLASH_CMD = 0x70,
90 HOST_FLASH_DATA = 0x74,
91 HOST_TRANSITION_DETECT = 0x75,
92 HOST_GPIO_CTRL = 0x76,
93 HOST_I2C_ADDR = 0x78, /* 32 bit */
95 HOST_I2C_XFER_CNT = 0x7e,
98 /* HOST_SLOT_STAT bits */
99 HOST_SSTAT_ATTN = (1 << 31),
103 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
105 PORT_REGS_SIZE = 0x2000,
106 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
108 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
110 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
111 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
112 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
113 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
114 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
115 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
116 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
117 PORT_CMD_ERR = 0x1024, /* command error number */
118 PORT_FIS_CFG = 0x1028,
119 PORT_FIFO_THRES = 0x102c,
121 PORT_DECODE_ERR_CNT = 0x1040,
122 PORT_DECODE_ERR_THRESH = 0x1042,
123 PORT_CRC_ERR_CNT = 0x1044,
124 PORT_CRC_ERR_THRESH = 0x1046,
125 PORT_HSHK_ERR_CNT = 0x1048,
126 PORT_HSHK_ERR_THRESH = 0x104a,
128 PORT_PHY_CFG = 0x1050,
129 PORT_SLOT_STAT = 0x1800,
130 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
131 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
132 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
133 PORT_SCONTROL = 0x1f00,
134 PORT_SSTATUS = 0x1f04,
135 PORT_SERROR = 0x1f08,
136 PORT_SACTIVE = 0x1f0c,
138 /* PORT_CTRL_STAT bits */
139 PORT_CS_PORT_RST = (1 << 0), /* port reset */
140 PORT_CS_DEV_RST = (1 << 1), /* device reset */
141 PORT_CS_INIT = (1 << 2), /* port initialize */
142 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
143 PORT_CS_RESUME = (1 << 6), /* port resume */
144 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
145 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
146 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
148 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
149 /* bits[11:0] are masked */
150 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
151 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
152 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
153 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
154 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
155 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
156 PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */
157 PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
195 SGE_TRM = (1 << 31), /* Last SGE in chain */
196 PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */
202 IRQ_STAT_4PORTS = 0xf,
205 struct sil24_cmd_block {
206 struct sil24_prb prb;
207 struct sil24_sge sge[LIBATA_MAX_PRD];
213 * The preview driver always returned 0 for status. We emulate it
214 * here from the previous interrupt.
216 struct sil24_port_priv {
217 struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */
218 dma_addr_t cmd_block_dma; /* DMA base addr for them */
221 /* ap->host_set->private_data */
222 struct sil24_host_priv {
223 void *host_base; /* global controller control (128 bytes @BAR0) */
224 void *port_base; /* port registers (4 * 8192 bytes @BAR2) */
227 static u8 sil24_check_status(struct ata_port *ap);
228 static u8 sil24_check_err(struct ata_port *ap);
229 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
230 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
231 static void sil24_phy_reset(struct ata_port *ap);
232 static void sil24_qc_prep(struct ata_queued_cmd *qc);
233 static int sil24_qc_issue(struct ata_queued_cmd *qc);
234 static void sil24_irq_clear(struct ata_port *ap);
235 static void sil24_eng_timeout(struct ata_port *ap);
236 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
237 static int sil24_port_start(struct ata_port *ap);
238 static void sil24_port_stop(struct ata_port *ap);
239 static void sil24_host_stop(struct ata_host_set *host_set);
240 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
242 static struct pci_device_id sil24_pci_tbl[] = {
243 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
244 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
247 static struct pci_driver sil24_pci_driver = {
249 .id_table = sil24_pci_tbl,
250 .probe = sil24_init_one,
251 .remove = ata_pci_remove_one, /* safe? */
254 static Scsi_Host_Template sil24_sht = {
255 .module = THIS_MODULE,
257 .ioctl = ata_scsi_ioctl,
258 .queuecommand = ata_scsi_queuecmd,
259 .eh_strategy_handler = ata_scsi_error,
260 .can_queue = ATA_DEF_QUEUE,
261 .this_id = ATA_SHT_THIS_ID,
262 .sg_tablesize = LIBATA_MAX_PRD,
263 .max_sectors = ATA_MAX_SECTORS,
264 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
265 .emulated = ATA_SHT_EMULATED,
266 .use_clustering = ATA_SHT_USE_CLUSTERING,
267 .proc_name = DRV_NAME,
268 .dma_boundary = ATA_DMA_BOUNDARY,
269 .slave_configure = ata_scsi_slave_config,
270 .bios_param = ata_std_bios_param,
271 .ordered_flush = 1, /* NCQ not supported yet */
274 static struct ata_port_operations sil24_ops = {
275 .port_disable = ata_port_disable,
277 .check_status = sil24_check_status,
278 .check_altstatus = sil24_check_status,
279 .check_err = sil24_check_err,
280 .dev_select = ata_noop_dev_select,
282 .phy_reset = sil24_phy_reset,
284 .qc_prep = sil24_qc_prep,
285 .qc_issue = sil24_qc_issue,
287 .eng_timeout = sil24_eng_timeout,
289 .irq_handler = sil24_interrupt,
290 .irq_clear = sil24_irq_clear,
292 .scr_read = sil24_scr_read,
293 .scr_write = sil24_scr_write,
295 .port_start = sil24_port_start,
296 .port_stop = sil24_port_stop,
297 .host_stop = sil24_host_stop,
300 static struct ata_port_info sil24_port_info[] = {
304 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
305 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
307 .pio_mask = 0x1f, /* pio0-4 */
308 .mwdma_mask = 0x07, /* mwdma0-2 */
309 .udma_mask = 0x3f, /* udma0-5 */
310 .port_ops = &sil24_ops,
315 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
316 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
318 .pio_mask = 0x1f, /* pio0-4 */
319 .mwdma_mask = 0x07, /* mwdma0-2 */
320 .udma_mask = 0x3f, /* udma0-5 */
321 .port_ops = &sil24_ops,
325 static u8 sil24_check_status(struct ata_port *ap)
330 static u8 sil24_check_err(struct ata_port *ap)
335 static int sil24_scr_map[] = {
342 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
344 void *scr_addr = (void *)ap->ioaddr.scr_addr;
345 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
347 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
348 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
353 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
355 void *scr_addr = (void *)ap->ioaddr.scr_addr;
356 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
358 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
359 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
363 static void sil24_phy_reset(struct ata_port *ap)
365 __sata_phy_reset(ap);
367 * No ATAPI yet. Just unconditionally indicate ATA device.
368 * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA
369 * and libata core will ignore the device.
371 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
372 ap->device[0].class = ATA_DEV_ATA;
375 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
376 struct sil24_cmd_block *cb)
378 struct scatterlist *sg = qc->sg;
379 struct sil24_sge *sge = cb->sge;
382 for (i = 0; i < qc->n_elem; i++, sg++, sge++) {
383 sge->addr = cpu_to_le64(sg_dma_address(sg));
384 sge->cnt = cpu_to_le32(sg_dma_len(sg));
386 sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM);
390 static void sil24_qc_prep(struct ata_queued_cmd *qc)
392 struct ata_port *ap = qc->ap;
393 struct sil24_port_priv *pp = ap->private_data;
394 struct sil24_cmd_block *cb = pp->cmd_block + qc->tag;
395 struct sil24_prb *prb = &cb->prb;
397 switch (qc->tf.protocol) {
400 case ATA_PROT_NODATA:
403 /* ATAPI isn't supported yet */
407 ata_tf_to_fis(&qc->tf, prb->fis, 0);
409 if (qc->flags & ATA_QCFLAG_DMAMAP)
410 sil24_fill_sg(qc, cb);
413 static int sil24_qc_issue(struct ata_queued_cmd *qc)
415 struct ata_port *ap = qc->ap;
416 void *port = (void *)ap->ioaddr.cmd_addr;
417 struct sil24_port_priv *pp = ap->private_data;
418 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
420 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
424 static void sil24_irq_clear(struct ata_port *ap)
429 static int __sil24_reset_controller(void *port)
434 /* Reset controller state. Is this correct? */
435 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
436 readl(port + PORT_CTRL_STAT); /* sync */
439 for (cnt = 0; cnt < 1000; cnt++) {
441 tmp = readl(port + PORT_CTRL_STAT);
442 if (!(tmp & PORT_CS_DEV_RST))
446 if (tmp & PORT_CS_DEV_RST)
451 static void sil24_reset_controller(struct ata_port *ap)
453 printk(KERN_NOTICE DRV_NAME
454 " ata%u: resetting controller...\n", ap->id);
455 if (__sil24_reset_controller((void *)ap->ioaddr.cmd_addr))
456 printk(KERN_ERR DRV_NAME
457 " ata%u: failed to reset controller\n", ap->id);
460 static void sil24_eng_timeout(struct ata_port *ap)
462 struct ata_queued_cmd *qc;
464 qc = ata_qc_from_tag(ap, ap->active_tag);
466 printk(KERN_ERR "ata%u: BUG: tiemout without command\n",
472 * hack alert! We cannot use the supplied completion
473 * function from inside the ->eh_strategy_handler() thread.
474 * libata is the only user of ->eh_strategy_handler() in
475 * any kernel, so the default scsi_done() assumes it is
476 * not being called from the SCSI EH.
478 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
479 qc->scsidone = scsi_finish_command;
480 ata_qc_complete(qc, ATA_ERR);
482 sil24_reset_controller(ap);
485 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
487 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
488 void *port = (void *)ap->ioaddr.cmd_addr;
489 u32 irq_stat, cmd_err, sstatus, serror;
491 irq_stat = readl(port + PORT_IRQ_STAT);
492 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
494 if (!(irq_stat & PORT_IRQ_ERROR)) {
495 /* ignore non-completion, non-error irqs for now */
496 printk(KERN_WARNING DRV_NAME
497 "ata%u: non-error exception irq (irq_stat %x)\n",
502 cmd_err = readl(port + PORT_CMD_ERR);
503 sstatus = readl(port + PORT_SSTATUS);
504 serror = readl(port + PORT_SERROR);
506 writel(serror, port + PORT_SERROR);
508 printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n"
509 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
510 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
513 ata_qc_complete(qc, ATA_ERR);
515 sil24_reset_controller(ap);
518 static inline void sil24_host_intr(struct ata_port *ap)
520 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
521 void *port = (void *)ap->ioaddr.cmd_addr;
524 slot_stat = readl(port + PORT_SLOT_STAT);
525 if (!(slot_stat & HOST_SSTAT_ATTN)) {
527 ata_qc_complete(qc, 0);
529 sil24_error_intr(ap, slot_stat);
532 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
534 struct ata_host_set *host_set = dev_instance;
535 struct sil24_host_priv *hpriv = host_set->private_data;
536 unsigned handled = 0;
540 status = readl(hpriv->host_base + HOST_IRQ_STAT);
542 if (status == 0xffffffff) {
543 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
544 "PCI fault or device removal?\n");
548 if (!(status & IRQ_STAT_4PORTS))
551 spin_lock(&host_set->lock);
553 for (i = 0; i < host_set->n_ports; i++)
554 if (status & (1 << i)) {
555 struct ata_port *ap = host_set->ports[i];
556 if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
557 sil24_host_intr(host_set->ports[i]);
560 printk(KERN_ERR DRV_NAME
561 ": interrupt from disabled port %d\n", i);
564 spin_unlock(&host_set->lock);
566 return IRQ_RETVAL(handled);
569 static int sil24_port_start(struct ata_port *ap)
571 struct device *dev = ap->host_set->dev;
572 struct sil24_port_priv *pp;
573 struct sil24_cmd_block *cb;
574 size_t cb_size = sizeof(*cb);
577 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
580 memset(pp, 0, sizeof(*pp));
582 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
587 memset(cb, 0, cb_size);
590 pp->cmd_block_dma = cb_dma;
592 ap->private_data = pp;
597 static void sil24_port_stop(struct ata_port *ap)
599 struct device *dev = ap->host_set->dev;
600 struct sil24_port_priv *pp = ap->private_data;
601 size_t cb_size = sizeof(*pp->cmd_block);
603 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
607 static void sil24_host_stop(struct ata_host_set *host_set)
609 struct sil24_host_priv *hpriv = host_set->private_data;
611 iounmap(hpriv->host_base);
612 iounmap(hpriv->port_base);
616 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
618 static int printed_version = 0;
619 unsigned int board_id = (unsigned int)ent->driver_data;
620 struct ata_probe_ent *probe_ent = NULL;
621 struct sil24_host_priv *hpriv = NULL;
622 void *host_base = NULL, *port_base = NULL;
625 if (!printed_version++)
626 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
628 rc = pci_enable_device(pdev);
632 rc = pci_request_regions(pdev, DRV_NAME);
637 /* ioremap mmio registers */
638 host_base = ioremap(pci_resource_start(pdev, 0),
639 pci_resource_len(pdev, 0));
642 port_base = ioremap(pci_resource_start(pdev, 2),
643 pci_resource_len(pdev, 2));
647 /* allocate & init probe_ent and hpriv */
648 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
652 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
656 memset(probe_ent, 0, sizeof(*probe_ent));
657 probe_ent->dev = pci_dev_to_dev(pdev);
658 INIT_LIST_HEAD(&probe_ent->node);
660 probe_ent->sht = sil24_port_info[board_id].sht;
661 probe_ent->host_flags = sil24_port_info[board_id].host_flags;
662 probe_ent->pio_mask = sil24_port_info[board_id].pio_mask;
663 probe_ent->udma_mask = sil24_port_info[board_id].udma_mask;
664 probe_ent->port_ops = sil24_port_info[board_id].port_ops;
665 probe_ent->n_ports = (board_id == BID_SIL3124) ? 4 : 2;
667 probe_ent->irq = pdev->irq;
668 probe_ent->irq_flags = SA_SHIRQ;
669 probe_ent->mmio_base = port_base;
670 probe_ent->private_data = hpriv;
672 memset(hpriv, 0, sizeof(*hpriv));
673 hpriv->host_base = host_base;
674 hpriv->port_base = port_base;
677 * Configure the device
680 * FIXME: This device is certainly 64-bit capable. We just
681 * don't know how to use it. After fixing 32bit activation in
682 * this function, enable 64bit masks here.
684 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
686 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
690 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
692 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
698 writel(0, host_base + HOST_FLASH_CMD);
700 /* Mask interrupts during initialization */
701 writel(0, host_base + HOST_CTRL);
703 for (i = 0; i < probe_ent->n_ports; i++) {
704 void *port = port_base + i * PORT_REGS_SIZE;
705 unsigned long portu = (unsigned long)port;
709 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
710 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
712 ata_std_ports(&probe_ent->port[i]);
714 /* Initial PHY setting */
715 writel(0x20c, port + PORT_PHY_CFG);
718 tmp = readl(port + PORT_CTRL_STAT);
719 if (tmp & PORT_CS_PORT_RST) {
720 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
721 readl(port + PORT_CTRL_STAT); /* sync */
722 for (cnt = 0; cnt < 10; cnt++) {
724 tmp = readl(port + PORT_CTRL_STAT);
725 if (!(tmp & PORT_CS_PORT_RST))
728 if (tmp & PORT_CS_PORT_RST)
729 printk(KERN_ERR DRV_NAME
730 "(%s): failed to clear port RST\n",
734 /* Zero error counters. */
735 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
736 writel(0x8000, port + PORT_CRC_ERR_THRESH);
737 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
738 writel(0x0000, port + PORT_DECODE_ERR_CNT);
739 writel(0x0000, port + PORT_CRC_ERR_CNT);
740 writel(0x0000, port + PORT_HSHK_ERR_CNT);
742 /* FIXME: 32bit activation? */
743 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
744 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
746 /* Configure interrupts */
747 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
748 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS,
749 port + PORT_IRQ_ENABLE_SET);
751 /* Clear interrupts */
752 writel(0x0fff0fff, port + PORT_IRQ_STAT);
753 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
755 /* Clear port multiplier enable and resume bits */
756 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
759 if (__sil24_reset_controller(port))
760 printk(KERN_ERR DRV_NAME
761 "(%s): failed to reset controller\n",
765 /* Turn on interrupts */
766 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
768 pci_set_master(pdev);
770 /* FIXME: check ata_device_add return value */
771 ata_device_add(probe_ent);
783 pci_release_regions(pdev);
785 pci_disable_device(pdev);
789 static int __init sil24_init(void)
791 return pci_module_init(&sil24_pci_driver);
794 static void __exit sil24_exit(void)
796 pci_unregister_driver(&sil24_pci_driver);
799 MODULE_AUTHOR("Tejun Heo");
800 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
801 MODULE_LICENSE("GPL");
802 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
804 module_init(sil24_init);
805 module_exit(sil24_exit);