1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
3 * linux/drivers/serial/sh-sci.h
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
13 #include <linux/serial_core.h>
16 #if defined(__H8300H__) || defined(__H8300S__)
18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
19 #include <asm/regs306x.h>
21 #if defined(CONFIG_H8S2678)
22 #include <asm/regs267x.h>
26 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
27 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7709)
30 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
31 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
32 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
34 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
35 # define SCIF0 0xA4400000
36 # define SCIF2 0xA4410000
37 # define SCSMR_Ir 0xA44A0000
38 # define IRDA_SCIF SCIF0
39 # define SCPCR 0xA4000116
40 # define SCPDR 0xA4000136
42 /* Set the clock source,
43 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
44 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
46 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48 #elif defined(CONFIG_SH_RTS7751R2D)
49 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
50 # define SCIF_ORER 0x0001 /* overrun error bit */
51 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
53 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
54 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
55 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
56 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
57 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
58 defined(CONFIG_CPU_SUBTYPE_SH7751R)
59 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
60 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
61 # define SCIF_ORER 0x0001 /* overrun error bit */
62 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
63 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
64 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
66 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
67 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
68 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
69 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
70 # define SCIF_ORER 0x0001 /* overrun error bit */
71 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
73 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
74 # define SCPCR 0xA4050116 /* 16 bit SCIF */
75 # define SCPDR 0xA4050136 /* 16 bit SCIF */
76 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
78 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
79 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
81 # define SCIF_ORER 0x0001 /* overrun error bit */
82 # define PACR 0xa4050100
83 # define PBCR 0xa4050102
84 # define SCSCR_INIT(port) 0x3B
86 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
87 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
88 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
89 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
90 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
91 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
93 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
94 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
95 # define SCSPTR0 SCPDR0
96 # define SCIF_ORER 0x0001 /* overrun error bit */
97 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
99 # define PORT_PSCR 0xA405011E
100 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
101 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
102 # define SCIF_ORER 0x0001 /* overrun error bit */
103 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
105 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
106 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
107 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
108 # define SCIF_ORER 0x0001 /* overrun error bit */
109 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
111 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
112 # include <asm/hardware.h>
113 # define SCIF_BASE_ADDR 0x01030000
114 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
115 # define SCIF_PTR2_OFFS 0x0000020
116 # define SCIF_LSR2_OFFS 0x0000024
117 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
118 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
119 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
122 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
123 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
125 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
126 #elif defined(CONFIG_H8S2678)
127 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
129 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
130 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
131 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
132 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
133 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
134 # define SCIF_ORER 0x0001 /* overrun error bit */
135 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
137 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
138 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
139 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
140 # define SCIF_ORER 0x0001 /* Overrun error bit */
141 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
143 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
144 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
145 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
146 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
147 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
148 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
149 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
150 # define SCIF_OPER 0x0001 /* Overrun error bit */
151 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
153 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
154 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
155 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
156 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
157 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
158 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
160 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
161 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
162 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
163 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
164 # define SCIF_ORER 0x0001 /* overrun error bit */
165 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
167 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
168 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
169 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
170 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
171 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
172 # define SCIF_ORER 0x0001 /* Overrun error bit */
173 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
176 # error CPU subtype not defined
180 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
181 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
182 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
183 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
184 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
186 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
187 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
192 defined(CONFIG_CPU_SUBTYPE_SHX3)
193 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
195 #define SCI_CTRL_FLAGS_REIE 0
197 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
200 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
203 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
206 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
212 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
215 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
218 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
224 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
225 #define SCIF_ORER 0x0200
226 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
227 #define SCIF_RFDC_MASK 0x007f
228 #define SCIF_TXROOM_MAX 64
230 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
231 #define SCIF_RFDC_MASK 0x001f
232 #define SCIF_TXROOM_MAX 16
235 #if defined(SCI_ONLY)
236 # define SCxSR_TEND(port) SCI_TEND
237 # define SCxSR_ERRORS(port) SCI_ERRORS
238 # define SCxSR_RDxF(port) SCI_RDRF
239 # define SCxSR_TDxE(port) SCI_TDRE
240 # define SCxSR_ORER(port) SCI_ORER
241 # define SCxSR_FER(port) SCI_FER
242 # define SCxSR_PER(port) SCI_PER
243 # define SCxSR_BRK(port) 0x00
244 # define SCxSR_RDxF_CLEAR(port) 0xbc
245 # define SCxSR_ERROR_CLEAR(port) 0xc4
246 # define SCxSR_TDxE_CLEAR(port) 0x78
247 # define SCxSR_BREAK_CLEAR(port) 0xc4
248 #elif defined(SCIF_ONLY)
249 # define SCxSR_TEND(port) SCIF_TEND
250 # define SCxSR_ERRORS(port) SCIF_ERRORS
251 # define SCxSR_RDxF(port) SCIF_RDF
252 # define SCxSR_TDxE(port) SCIF_TDFE
253 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
254 # define SCxSR_ORER(port) SCIF_ORER
256 # define SCxSR_ORER(port) 0x0000
258 # define SCxSR_FER(port) SCIF_FER
259 # define SCxSR_PER(port) SCIF_PER
260 # define SCxSR_BRK(port) SCIF_BRK
261 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
262 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
263 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
264 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
265 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
267 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
268 # define SCxSR_RDxF_CLEAR(port) 0x00fc
269 # define SCxSR_ERROR_CLEAR(port) 0x0073
270 # define SCxSR_TDxE_CLEAR(port) 0x00df
271 # define SCxSR_BREAK_CLEAR(port) 0x00e3
274 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
275 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
276 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
277 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
278 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
279 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
280 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
281 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
282 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
283 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
284 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
285 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
289 #define SCFCR_RFRST 0x0002
290 #define SCFCR_TFRST 0x0004
291 #define SCFCR_TCRST 0x4000
292 #define SCFCR_MCE 0x0008
294 #define SCI_MAJOR 204
295 #define SCI_MINOR_START 8
297 /* Generic serial flags */
298 #define SCI_RX_THROTTLE 0x0000001
300 #define SCI_MAGIC 0xbabeface
303 * Events are used to schedule things to happen at timer-interrupt
304 * time, instead of at rs interrupt time.
306 #define SCI_EVENT_WRITE_WAKEUP 0
308 #define SCI_IN(size, offset) \
309 unsigned int addr = port->mapbase + (offset); \
311 return ctrl_inb(addr); \
313 return ctrl_inw(addr); \
315 #define SCI_OUT(size, offset, value) \
316 unsigned int addr = port->mapbase + (offset); \
318 ctrl_outb(value, addr); \
320 ctrl_outw(value, addr); \
323 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
324 static inline unsigned int sci_##name##_in(struct uart_port *port) \
326 if (port->type == PORT_SCI) { \
327 SCI_IN(sci_size, sci_offset) \
329 SCI_IN(scif_size, scif_offset); \
332 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
334 if (port->type == PORT_SCI) { \
335 SCI_OUT(sci_size, sci_offset, value) \
337 SCI_OUT(scif_size, scif_offset, value); \
341 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
342 static inline unsigned int sci_##name##_in(struct uart_port *port) \
344 SCI_IN(scif_size, scif_offset); \
346 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
348 SCI_OUT(scif_size, scif_offset, value); \
351 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
352 static inline unsigned int sci_##name##_in(struct uart_port* port) \
354 SCI_IN(sci_size, sci_offset); \
356 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
358 SCI_OUT(sci_size, sci_offset, value); \
361 #ifdef CONFIG_CPU_SH3
362 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
363 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
364 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
365 h8_sci_offset, h8_sci_size) \
366 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
367 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
368 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
369 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
370 defined(CONFIG_CPU_SUBTYPE_SH7705)
371 #define SCIF_FNS(name, scif_offset, scif_size) \
372 CPU_SCIF_FNS(name, scif_offset, scif_size)
374 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
375 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
376 h8_sci_offset, h8_sci_size) \
377 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
378 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
379 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
381 #elif defined(__H8300H__) || defined(__H8300S__)
382 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
383 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
384 h8_sci_offset, h8_sci_size) \
385 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
386 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
388 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
389 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
390 h8_sci_offset, h8_sci_size) \
391 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
392 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
393 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
396 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
397 defined(CONFIG_CPU_SUBTYPE_SH7705)
399 SCIF_FNS(SCSMR, 0x00, 16)
400 SCIF_FNS(SCBRR, 0x04, 8)
401 SCIF_FNS(SCSCR, 0x08, 16)
402 SCIF_FNS(SCTDSR, 0x0c, 8)
403 SCIF_FNS(SCFER, 0x10, 16)
404 SCIF_FNS(SCxSR, 0x14, 16)
405 SCIF_FNS(SCFCR, 0x18, 16)
406 SCIF_FNS(SCFDR, 0x1c, 16)
407 SCIF_FNS(SCxTDR, 0x20, 8)
408 SCIF_FNS(SCxRDR, 0x24, 8)
409 SCIF_FNS(SCLSR, 0x24, 16)
411 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
412 /* name off sz off sz off sz off sz off sz*/
413 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
414 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
415 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
416 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
417 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
418 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
419 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
420 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
421 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
422 defined(CONFIG_CPU_SUBTYPE_SH7785)
423 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
424 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
425 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
426 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
427 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
429 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
430 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
431 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
434 #define sci_in(port, reg) sci_##reg##_in(port)
435 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
437 /* H8/300 series SCI pins assignment */
438 #if defined(__H8300H__) || defined(__H8300S__)
439 static const struct __attribute__((packed)) {
440 int port; /* GPIO port no */
441 unsigned short rx,tx; /* GPIO bit no */
442 } h8300_sci_pins[] = {
443 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
445 .port = H8300_GPIO_P9,
450 .port = H8300_GPIO_P9,
455 .port = H8300_GPIO_PB,
459 #elif defined(CONFIG_H8S2678)
461 .port = H8300_GPIO_P3,
466 .port = H8300_GPIO_P3,
471 .port = H8300_GPIO_P5,
479 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
480 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
481 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
482 defined(CONFIG_CPU_SUBTYPE_SH7709)
483 static inline int sci_rxd_in(struct uart_port *port)
485 if (port->mapbase == 0xfffffe80)
486 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
487 if (port->mapbase == 0xa4000150)
488 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
489 if (port->mapbase == 0xa4000140)
490 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
493 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
494 static inline int sci_rxd_in(struct uart_port *port)
496 if (port->mapbase == SCIF0)
497 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
498 if (port->mapbase == SCIF2)
499 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
502 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
503 static inline int sci_rxd_in(struct uart_port *port)
505 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
507 static inline void set_sh771x_scif_pfc(struct uart_port *port)
509 if (port->mapbase == 0xA4400000){
510 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
511 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
514 if (port->mapbase == 0xA4410000){
515 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
520 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
521 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
522 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
523 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
524 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
525 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
526 defined(CONFIG_CPU_SUBTYPE_SH4_202)
527 static inline int sci_rxd_in(struct uart_port *port)
530 if (port->mapbase == 0xffe00000)
531 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
534 if (port->mapbase == 0xffe80000)
535 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
539 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
540 static inline int sci_rxd_in(struct uart_port *port)
542 if (port->mapbase == 0xfe600000)
543 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
544 if (port->mapbase == 0xfe610000)
545 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
546 if (port->mapbase == 0xfe620000)
547 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
550 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
551 static inline int sci_rxd_in(struct uart_port *port)
553 if (port->mapbase == 0xa4430000)
554 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
557 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
558 static inline int sci_rxd_in(struct uart_port *port)
560 if (port->mapbase == 0xffe00000)
561 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
562 if (port->mapbase == 0xffe10000)
563 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
564 if (port->mapbase == 0xffe20000)
565 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
566 if (port->mapbase == 0xffe30000)
567 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
570 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
571 static inline int sci_rxd_in(struct uart_port *port)
573 if (port->mapbase == 0xffe00000)
574 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
577 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
578 static inline int sci_rxd_in(struct uart_port *port)
580 if (port->mapbase == 0xffe00000)
581 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
583 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
586 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
587 static inline int sci_rxd_in(struct uart_port *port)
589 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
591 #elif defined(__H8300H__) || defined(__H8300S__)
592 static inline int sci_rxd_in(struct uart_port *port)
594 int ch = (port->mapbase - SMR0) >> 3;
595 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
597 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
598 static inline int sci_rxd_in(struct uart_port *port)
600 if (port->mapbase == 0xff923000)
601 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
602 if (port->mapbase == 0xff924000)
603 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
604 if (port->mapbase == 0xff925000)
605 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
608 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
609 static inline int sci_rxd_in(struct uart_port *port)
611 if (port->mapbase == 0xffe00000)
612 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
613 if (port->mapbase == 0xffe10000)
614 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
617 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
618 static inline int sci_rxd_in(struct uart_port *port)
620 if (port->mapbase == 0xffea0000)
621 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
622 if (port->mapbase == 0xffeb0000)
623 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
624 if (port->mapbase == 0xffec0000)
625 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
626 if (port->mapbase == 0xffed0000)
627 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
628 if (port->mapbase == 0xffee0000)
629 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
630 if (port->mapbase == 0xffef0000)
631 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
634 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
635 static inline int sci_rxd_in(struct uart_port *port)
637 if (port->mapbase == 0xfffe8000)
638 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xfffe8800)
640 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
641 if (port->mapbase == 0xfffe9000)
642 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
643 if (port->mapbase == 0xfffe9800)
644 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
647 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
648 static inline int sci_rxd_in(struct uart_port *port)
650 if (port->mapbase == 0xf8400000)
651 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xf8410000)
653 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
654 if (port->mapbase == 0xf8420000)
655 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
658 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
659 static inline int sci_rxd_in(struct uart_port *port)
661 if (port->mapbase == 0xffc30000)
662 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
663 if (port->mapbase == 0xffc40000)
664 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
665 if (port->mapbase == 0xffc50000)
666 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
667 if (port->mapbase == 0xffc60000)
668 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
673 * Values for the BitRate Register (SCBRR)
675 * The values are actually divisors for a frequency which can
676 * be internal to the SH3 (14.7456MHz) or derived from an external
677 * clock source. This driver assumes the internal clock is used;
678 * to support using an external clock source, config options or
679 * possibly command-line options would need to be added.
681 * Also, to support speeds below 2400 (why?) the lower 2 bits of
682 * the SCSMR register would also need to be set to non-zero values.
684 * -- Greg Banks 27Feb2000
686 * Answer: The SCBRR register is only eight bits, and the value in
687 * it gets larger with lower baud rates. At around 2400 (depending on
688 * the peripherial module clock) you run out of bits. However the
689 * lower two bits of SCSMR allow the module clock to be divided down,
690 * scaling the value which is needed in SCBRR.
692 * -- Stuart Menefy - 23 May 2000
694 * I meant, why would anyone bother with bitrates below 2400.
696 * -- Greg Banks - 7Jul2000
698 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
699 * tape reader as a console!
701 * -- Mitch Davis - 15 Jul 2000
704 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
705 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
706 defined(CONFIG_CPU_SUBTYPE_SH7785)
707 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
708 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
709 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
710 #elif defined(__H8300H__) || defined(__H8300S__)
711 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
712 #elif defined(CONFIG_SUPERH64)
713 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
714 #else /* Generic SH */
715 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)