2 * File: drivers/spi/bfin5xx_spi.c
4 * Bryan Wu <bryan.wu@analog.com>
6 * Luke Yang (Analog Devices Inc.)
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
17 * Copyright 2004-2007 Analog Devices Inc.
19 * This program is free software ; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation ; either version 2, or (at your option)
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program ; see the file COPYING.
31 * If not, write to the Free Software Foundation,
32 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 #include <linux/init.h>
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/device.h>
40 #include <linux/ioport.h>
41 #include <linux/irq.h>
42 #include <linux/errno.h>
43 #include <linux/interrupt.h>
44 #include <linux/platform_device.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/spi/spi.h>
47 #include <linux/workqueue.h>
50 #include <asm/portmux.h>
51 #include <asm/bfin5xx_spi.h>
53 MODULE_AUTHOR("Bryan Wu, Luke Yang");
54 MODULE_DESCRIPTION("Blackfin BF5xx SPI Contoller Driver");
55 MODULE_LICENSE("GPL");
57 #define DRV_NAME "bfin-spi-master"
58 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
60 #define DEFINE_SPI_REG(reg, off) \
61 static inline u16 read_##reg(void) \
62 { return bfin_read16(SPI0_REGBASE + off); } \
63 static inline void write_##reg(u16 v) \
64 {bfin_write16(SPI0_REGBASE + off, v); }
66 DEFINE_SPI_REG(CTRL, 0x00)
67 DEFINE_SPI_REG(FLAG, 0x04)
68 DEFINE_SPI_REG(STAT, 0x08)
69 DEFINE_SPI_REG(TDBR, 0x0C)
70 DEFINE_SPI_REG(RDBR, 0x10)
71 DEFINE_SPI_REG(BAUD, 0x14)
72 DEFINE_SPI_REG(SHAW, 0x18)
73 #define START_STATE ((void*)0)
74 #define RUNNING_STATE ((void*)1)
75 #define DONE_STATE ((void*)2)
76 #define ERROR_STATE ((void*)-1)
77 #define QUEUE_RUNNING 0
78 #define QUEUE_STOPPED 1
82 /* Driver model hookup */
83 struct platform_device *pdev;
85 /* SPI framework hookup */
86 struct spi_master *master;
89 struct bfin5xx_spi_master *master_info;
91 /* Driver message queue */
92 struct workqueue_struct *workqueue;
93 struct work_struct pump_messages;
95 struct list_head queue;
99 /* Message Transfer pump */
100 struct tasklet_struct pump_transfers;
102 /* Current message transfer state info */
103 struct spi_message *cur_msg;
104 struct spi_transfer *cur_transfer;
105 struct chip_data *cur_chip;
119 void (*write) (struct driver_data *);
120 void (*read) (struct driver_data *);
121 void (*duplex) (struct driver_data *);
130 u8 chip_select_requested;
132 u8 width; /* 0 or 1 */
134 u8 bits_per_word; /* 8 or 16 */
135 u8 cs_change_per_word;
137 void (*write) (struct driver_data *);
138 void (*read) (struct driver_data *);
139 void (*duplex) (struct driver_data *);
142 static void bfin_spi_enable(struct driver_data *drv_data)
147 write_CTRL(cr | BIT_CTL_ENABLE);
150 static void bfin_spi_disable(struct driver_data *drv_data)
155 write_CTRL(cr & (~BIT_CTL_ENABLE));
158 /* Caculate the SPI_BAUD register value based on input HZ */
159 static u16 hz_to_spi_baud(u32 speed_hz)
161 u_long sclk = get_sclk();
162 u16 spi_baud = (sclk / (2 * speed_hz));
164 if ((sclk % (2 * speed_hz)) > 0)
170 static int flush(struct driver_data *drv_data)
172 unsigned long limit = loops_per_jiffy << 1;
174 /* wait for stop and clear stat */
175 while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
178 write_STAT(BIT_STAT_CLR);
183 /* Chip select operation functions for cs_change flag */
184 static void cs_active(struct chip_data *chip)
186 u16 flag = read_FLAG();
189 flag &= ~(chip->flag << 8);
194 static void cs_deactive(struct chip_data *chip)
196 u16 flag = read_FLAG();
198 flag |= (chip->flag << 8);
203 #define MAX_SPI0_SSEL 7
205 /* stop controller and re-config current chip*/
206 static int restore_state(struct driver_data *drv_data)
208 struct chip_data *chip = drv_data->cur_chip;
210 u16 ssel[MAX_SPI0_SSEL] = {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
211 P_SPI0_SSEL4, P_SPI0_SSEL5,
212 P_SPI0_SSEL6, P_SPI0_SSEL7,};
214 /* Clear status and disable clock */
215 write_STAT(BIT_STAT_CLR);
216 bfin_spi_disable(drv_data);
217 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
219 /* Load the registers */
220 write_CTRL(chip->ctl_reg);
221 write_BAUD(chip->baud);
224 if (!chip->chip_select_requested) {
225 int i = chip->chip_select_num;
227 dev_dbg(&drv_data->pdev->dev, "chip select number is %d\n", i);
229 if ((i > 0) && (i <= MAX_SPI0_SSEL))
230 ret = peripheral_request(ssel[i-1], DRV_NAME);
232 chip->chip_select_requested = 1;
236 dev_dbg(&drv_data->pdev->dev,
237 ": request chip select number %d failed\n",
238 chip->chip_select_num);
243 /* used to kick off transfer in rx mode */
244 static unsigned short dummy_read(void)
251 static void null_writer(struct driver_data *drv_data)
253 u8 n_bytes = drv_data->n_bytes;
255 while (drv_data->tx < drv_data->tx_end) {
257 while ((read_STAT() & BIT_STAT_TXS))
259 drv_data->tx += n_bytes;
263 static void null_reader(struct driver_data *drv_data)
265 u8 n_bytes = drv_data->n_bytes;
268 while (drv_data->rx < drv_data->rx_end) {
269 while (!(read_STAT() & BIT_STAT_RXS))
272 drv_data->rx += n_bytes;
276 static void u8_writer(struct driver_data *drv_data)
278 dev_dbg(&drv_data->pdev->dev,
279 "cr8-s is 0x%x\n", read_STAT());
280 while (drv_data->tx < drv_data->tx_end) {
281 write_TDBR(*(u8 *) (drv_data->tx));
282 while (read_STAT() & BIT_STAT_TXS)
287 /* poll for SPI completion before returning */
288 while (!(read_STAT() & BIT_STAT_SPIF))
292 static void u8_cs_chg_writer(struct driver_data *drv_data)
294 struct chip_data *chip = drv_data->cur_chip;
296 while (drv_data->tx < drv_data->tx_end) {
299 write_TDBR(*(u8 *) (drv_data->tx));
300 while (read_STAT() & BIT_STAT_TXS)
302 while (!(read_STAT() & BIT_STAT_SPIF))
306 if (chip->cs_chg_udelay)
307 udelay(chip->cs_chg_udelay);
314 static void u8_reader(struct driver_data *drv_data)
316 dev_dbg(&drv_data->pdev->dev,
317 "cr-8 is 0x%x\n", read_STAT());
319 /* clear TDBR buffer before read(else it will be shifted out) */
324 while (drv_data->rx < drv_data->rx_end - 1) {
325 while (!(read_STAT() & BIT_STAT_RXS))
327 *(u8 *) (drv_data->rx) = read_RDBR();
331 while (!(read_STAT() & BIT_STAT_RXS))
333 *(u8 *) (drv_data->rx) = read_SHAW();
337 static void u8_cs_chg_reader(struct driver_data *drv_data)
339 struct chip_data *chip = drv_data->cur_chip;
341 while (drv_data->rx < drv_data->rx_end) {
344 read_RDBR(); /* kick off */
345 while (!(read_STAT() & BIT_STAT_RXS))
347 while (!(read_STAT() & BIT_STAT_SPIF))
349 *(u8 *) (drv_data->rx) = read_SHAW();
352 if (chip->cs_chg_udelay)
353 udelay(chip->cs_chg_udelay);
360 static void u8_duplex(struct driver_data *drv_data)
362 /* in duplex mode, clk is triggered by writing of TDBR */
363 while (drv_data->rx < drv_data->rx_end) {
364 write_TDBR(*(u8 *) (drv_data->tx));
365 while (!(read_STAT() & BIT_STAT_SPIF))
367 while (!(read_STAT() & BIT_STAT_RXS))
369 *(u8 *) (drv_data->rx) = read_RDBR();
375 static void u8_cs_chg_duplex(struct driver_data *drv_data)
377 struct chip_data *chip = drv_data->cur_chip;
379 while (drv_data->rx < drv_data->rx_end) {
383 write_TDBR(*(u8 *) (drv_data->tx));
384 while (!(read_STAT() & BIT_STAT_SPIF))
386 while (!(read_STAT() & BIT_STAT_RXS))
388 *(u8 *) (drv_data->rx) = read_RDBR();
391 if (chip->cs_chg_udelay)
392 udelay(chip->cs_chg_udelay);
399 static void u16_writer(struct driver_data *drv_data)
401 dev_dbg(&drv_data->pdev->dev,
402 "cr16 is 0x%x\n", read_STAT());
404 while (drv_data->tx < drv_data->tx_end) {
405 write_TDBR(*(u16 *) (drv_data->tx));
406 while ((read_STAT() & BIT_STAT_TXS))
411 /* poll for SPI completion before returning */
412 while (!(read_STAT() & BIT_STAT_SPIF))
416 static void u16_cs_chg_writer(struct driver_data *drv_data)
418 struct chip_data *chip = drv_data->cur_chip;
420 while (drv_data->tx < drv_data->tx_end) {
423 write_TDBR(*(u16 *) (drv_data->tx));
424 while ((read_STAT() & BIT_STAT_TXS))
426 while (!(read_STAT() & BIT_STAT_SPIF))
430 if (chip->cs_chg_udelay)
431 udelay(chip->cs_chg_udelay);
437 static void u16_reader(struct driver_data *drv_data)
439 dev_dbg(&drv_data->pdev->dev,
440 "cr-16 is 0x%x\n", read_STAT());
443 while (drv_data->rx < (drv_data->rx_end - 2)) {
444 while (!(read_STAT() & BIT_STAT_RXS))
446 *(u16 *) (drv_data->rx) = read_RDBR();
450 while (!(read_STAT() & BIT_STAT_RXS))
452 *(u16 *) (drv_data->rx) = read_SHAW();
456 static void u16_cs_chg_reader(struct driver_data *drv_data)
458 struct chip_data *chip = drv_data->cur_chip;
460 while (drv_data->rx < drv_data->rx_end) {
463 read_RDBR(); /* kick off */
464 while (!(read_STAT() & BIT_STAT_RXS))
466 while (!(read_STAT() & BIT_STAT_SPIF))
468 *(u16 *) (drv_data->rx) = read_SHAW();
471 if (chip->cs_chg_udelay)
472 udelay(chip->cs_chg_udelay);
478 static void u16_duplex(struct driver_data *drv_data)
480 /* in duplex mode, clk is triggered by writing of TDBR */
481 while (drv_data->tx < drv_data->tx_end) {
482 write_TDBR(*(u16 *) (drv_data->tx));
483 while (!(read_STAT() & BIT_STAT_SPIF))
485 while (!(read_STAT() & BIT_STAT_RXS))
487 *(u16 *) (drv_data->rx) = read_RDBR();
493 static void u16_cs_chg_duplex(struct driver_data *drv_data)
495 struct chip_data *chip = drv_data->cur_chip;
497 while (drv_data->tx < drv_data->tx_end) {
500 write_TDBR(*(u16 *) (drv_data->tx));
501 while (!(read_STAT() & BIT_STAT_SPIF))
503 while (!(read_STAT() & BIT_STAT_RXS))
505 *(u16 *) (drv_data->rx) = read_RDBR();
508 if (chip->cs_chg_udelay)
509 udelay(chip->cs_chg_udelay);
516 /* test if ther is more transfer to be done */
517 static void *next_transfer(struct driver_data *drv_data)
519 struct spi_message *msg = drv_data->cur_msg;
520 struct spi_transfer *trans = drv_data->cur_transfer;
522 /* Move to next transfer */
523 if (trans->transfer_list.next != &msg->transfers) {
524 drv_data->cur_transfer =
525 list_entry(trans->transfer_list.next,
526 struct spi_transfer, transfer_list);
527 return RUNNING_STATE;
533 * caller already set message->status;
534 * dma and pio irqs are blocked give finished message back
536 static void giveback(struct driver_data *drv_data)
538 struct chip_data *chip = drv_data->cur_chip;
539 struct spi_transfer *last_transfer;
541 struct spi_message *msg;
543 spin_lock_irqsave(&drv_data->lock, flags);
544 msg = drv_data->cur_msg;
545 drv_data->cur_msg = NULL;
546 drv_data->cur_transfer = NULL;
547 drv_data->cur_chip = NULL;
548 queue_work(drv_data->workqueue, &drv_data->pump_messages);
549 spin_unlock_irqrestore(&drv_data->lock, flags);
551 last_transfer = list_entry(msg->transfers.prev,
552 struct spi_transfer, transfer_list);
556 /* disable chip select signal. And not stop spi in autobuffer mode */
557 if (drv_data->tx_dma != 0xFFFF) {
559 bfin_spi_disable(drv_data);
562 if (!drv_data->cs_change)
566 msg->complete(msg->context);
569 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
571 struct driver_data *drv_data = (struct driver_data *)dev_id;
572 struct spi_message *msg = drv_data->cur_msg;
573 struct chip_data *chip = drv_data->cur_chip;
575 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
576 clear_dma_irqstat(CH_SPI);
578 /* Wait for DMA to complete */
579 while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN)
583 * wait for the last transaction shifted out. HRM states:
584 * at this point there may still be data in the SPI DMA FIFO waiting
585 * to be transmitted ... software needs to poll TXS in the SPI_STAT
586 * register until it goes low for 2 successive reads
588 if (drv_data->tx != NULL) {
589 while ((bfin_read_SPI_STAT() & TXS) ||
590 (bfin_read_SPI_STAT() & TXS))
594 while (!(bfin_read_SPI_STAT() & SPIF))
597 bfin_spi_disable(drv_data);
599 msg->actual_length += drv_data->len_in_bytes;
601 if (drv_data->cs_change)
604 /* Move to next transfer */
605 msg->state = next_transfer(drv_data);
607 /* Schedule transfer tasklet */
608 tasklet_schedule(&drv_data->pump_transfers);
610 /* free the irq handler before next transfer */
611 dev_dbg(&drv_data->pdev->dev,
612 "disable dma channel irq%d\n",
614 dma_disable_irq(CH_SPI);
619 static void pump_transfers(unsigned long data)
621 struct driver_data *drv_data = (struct driver_data *)data;
622 struct spi_message *message = NULL;
623 struct spi_transfer *transfer = NULL;
624 struct spi_transfer *previous = NULL;
625 struct chip_data *chip = NULL;
627 u16 cr, dma_width, dma_config;
628 u32 tranf_success = 1;
630 /* Get current state information */
631 message = drv_data->cur_msg;
632 transfer = drv_data->cur_transfer;
633 chip = drv_data->cur_chip;
636 * if msg is error or done, report it back using complete() callback
639 /* Handle for abort */
640 if (message->state == ERROR_STATE) {
641 message->status = -EIO;
646 /* Handle end of message */
647 if (message->state == DONE_STATE) {
653 /* Delay if requested at end of transfer */
654 if (message->state == RUNNING_STATE) {
655 previous = list_entry(transfer->transfer_list.prev,
656 struct spi_transfer, transfer_list);
657 if (previous->delay_usecs)
658 udelay(previous->delay_usecs);
661 /* Setup the transfer state based on the type of transfer */
662 if (flush(drv_data) == 0) {
663 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
664 message->status = -EIO;
669 if (transfer->tx_buf != NULL) {
670 drv_data->tx = (void *)transfer->tx_buf;
671 drv_data->tx_end = drv_data->tx + transfer->len;
672 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
673 transfer->tx_buf, drv_data->tx_end);
678 if (transfer->rx_buf != NULL) {
679 drv_data->rx = transfer->rx_buf;
680 drv_data->rx_end = drv_data->rx + transfer->len;
681 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
682 transfer->rx_buf, drv_data->rx_end);
687 drv_data->rx_dma = transfer->rx_dma;
688 drv_data->tx_dma = transfer->tx_dma;
689 drv_data->len_in_bytes = transfer->len;
690 drv_data->cs_change = transfer->cs_change;
693 if (width == CFG_SPI_WORDSIZE16) {
694 drv_data->len = (transfer->len) >> 1;
696 drv_data->len = transfer->len;
698 drv_data->write = drv_data->tx ? chip->write : null_writer;
699 drv_data->read = drv_data->rx ? chip->read : null_reader;
700 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
701 dev_dbg(&drv_data->pdev->dev, "transfer: ",
702 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
703 drv_data->write, chip->write, null_writer);
705 /* speed and width has been set on per message */
706 message->state = RUNNING_STATE;
709 /* restore spi status for each spi transfer */
710 if (transfer->speed_hz) {
711 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
713 write_BAUD(chip->baud);
717 dev_dbg(&drv_data->pdev->dev,
718 "now pumping a transfer: width is %d, len is %d\n",
719 width, transfer->len);
722 * Try to map dma buffer and do a dma transfer if
723 * successful use different way to r/w according to
724 * drv_data->cur_chip->enable_dma
726 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
728 write_STAT(BIT_STAT_CLR);
730 clear_dma_irqstat(CH_SPI);
731 bfin_spi_disable(drv_data);
733 /* config dma channel */
734 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
735 if (width == CFG_SPI_WORDSIZE16) {
736 set_dma_x_count(CH_SPI, drv_data->len);
737 set_dma_x_modify(CH_SPI, 2);
738 dma_width = WDSIZE_16;
740 set_dma_x_count(CH_SPI, drv_data->len);
741 set_dma_x_modify(CH_SPI, 1);
742 dma_width = WDSIZE_8;
745 /* set transfer width,direction. And enable spi */
746 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
748 /* dirty hack for autobuffer DMA mode */
749 if (drv_data->tx_dma == 0xFFFF) {
750 dev_dbg(&drv_data->pdev->dev,
751 "doing autobuffer DMA out.\n");
753 /* no irq in autobuffer mode */
755 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
756 set_dma_config(CH_SPI, dma_config);
757 set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
759 write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
760 (CFG_SPI_ENABLE << 14));
762 /* just return here, there can only be one transfer in this mode */
768 /* In dma mode, rx or tx must be NULL in one transfer */
769 if (drv_data->rx != NULL) {
770 /* set transfer mode, and enable SPI */
771 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
773 /* disable SPI before write to TDBR */
774 write_CTRL(cr & ~BIT_CTL_ENABLE);
776 /* clear tx reg soformer data is not shifted out */
779 set_dma_x_count(CH_SPI, drv_data->len);
782 dma_enable_irq(CH_SPI);
783 dma_config = (WNR | RESTART | dma_width | DI_EN);
784 set_dma_config(CH_SPI, dma_config);
785 set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx);
789 CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
791 /* set transfer mode, and enable SPI */
793 } else if (drv_data->tx != NULL) {
794 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
797 dma_enable_irq(CH_SPI);
798 dma_config = (RESTART | dma_width | DI_EN);
799 set_dma_config(CH_SPI, dma_config);
800 set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
803 write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
804 (CFG_SPI_ENABLE << 14));
808 /* IO mode write then read */
809 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
811 write_STAT(BIT_STAT_CLR);
813 if (drv_data->tx != NULL && drv_data->rx != NULL) {
814 /* full duplex mode */
815 BUG_ON((drv_data->tx_end - drv_data->tx) !=
816 (drv_data->rx_end - drv_data->rx));
817 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
818 cr |= CFG_SPI_WRITE | (width << 8) |
819 (CFG_SPI_ENABLE << 14);
820 dev_dbg(&drv_data->pdev->dev,
821 "IO duplex: cr is 0x%x\n", cr);
825 drv_data->duplex(drv_data);
827 if (drv_data->tx != drv_data->tx_end)
829 } else if (drv_data->tx != NULL) {
830 /* write only half duplex */
831 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
832 cr |= CFG_SPI_WRITE | (width << 8) |
833 (CFG_SPI_ENABLE << 14);
834 dev_dbg(&drv_data->pdev->dev,
835 "IO write: cr is 0x%x\n", cr);
839 drv_data->write(drv_data);
841 if (drv_data->tx != drv_data->tx_end)
843 } else if (drv_data->rx != NULL) {
844 /* read only half duplex */
845 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
846 cr |= CFG_SPI_READ | (width << 8) |
847 (CFG_SPI_ENABLE << 14);
848 dev_dbg(&drv_data->pdev->dev,
849 "IO read: cr is 0x%x\n", cr);
853 drv_data->read(drv_data);
854 if (drv_data->rx != drv_data->rx_end)
858 if (!tranf_success) {
859 dev_dbg(&drv_data->pdev->dev,
860 "IO write error!\n");
861 message->state = ERROR_STATE;
863 /* Update total byte transfered */
864 message->actual_length += drv_data->len;
866 if (drv_data->cs_change)
869 /* Move to next transfer of this msg */
870 message->state = next_transfer(drv_data);
873 /* Schedule next transfer tasklet */
874 tasklet_schedule(&drv_data->pump_transfers);
879 /* pop a msg from queue and kick off real transfer */
880 static void pump_messages(struct work_struct *work)
882 struct driver_data *drv_data;
885 drv_data = container_of(work, struct driver_data, pump_messages);
887 /* Lock queue and check for queue work */
888 spin_lock_irqsave(&drv_data->lock, flags);
889 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
890 /* pumper kicked off but no work to do */
892 spin_unlock_irqrestore(&drv_data->lock, flags);
896 /* Make sure we are not already running a message */
897 if (drv_data->cur_msg) {
898 spin_unlock_irqrestore(&drv_data->lock, flags);
902 /* Extract head of queue */
903 drv_data->cur_msg = list_entry(drv_data->queue.next,
904 struct spi_message, queue);
906 /* Setup the SSP using the per chip configuration */
907 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
908 if (restore_state(drv_data)) {
909 spin_unlock_irqrestore(&drv_data->lock, flags);
913 list_del_init(&drv_data->cur_msg->queue);
915 /* Initial message state */
916 drv_data->cur_msg->state = START_STATE;
917 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
918 struct spi_transfer, transfer_list);
920 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
921 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
922 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
923 drv_data->cur_chip->ctl_reg);
925 dev_dbg(&drv_data->pdev->dev,
926 "the first transfer len is %d\n",
927 drv_data->cur_transfer->len);
929 /* Mark as busy and launch transfers */
930 tasklet_schedule(&drv_data->pump_transfers);
933 spin_unlock_irqrestore(&drv_data->lock, flags);
937 * got a msg to transfer, queue it in drv_data->queue.
938 * And kick off message pumper
940 static int transfer(struct spi_device *spi, struct spi_message *msg)
942 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
945 spin_lock_irqsave(&drv_data->lock, flags);
947 if (drv_data->run == QUEUE_STOPPED) {
948 spin_unlock_irqrestore(&drv_data->lock, flags);
952 msg->actual_length = 0;
953 msg->status = -EINPROGRESS;
954 msg->state = START_STATE;
956 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
957 list_add_tail(&msg->queue, &drv_data->queue);
959 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
960 queue_work(drv_data->workqueue, &drv_data->pump_messages);
962 spin_unlock_irqrestore(&drv_data->lock, flags);
967 /* first setup for new devices */
968 static int setup(struct spi_device *spi)
970 struct bfin5xx_spi_chip *chip_info = NULL;
971 struct chip_data *chip;
972 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
975 /* Abort device setup if requested features are not supported */
976 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
977 dev_err(&spi->dev, "requested mode not fully supported\n");
981 /* Zero (the default) here means 8 bits */
982 if (!spi->bits_per_word)
983 spi->bits_per_word = 8;
985 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
988 /* Only alloc (or use chip_info) on first setup */
989 chip = spi_get_ctldata(spi);
991 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
995 chip->enable_dma = 0;
996 chip_info = spi->controller_data;
999 /* chip_info isn't always needed */
1001 /* Make sure people stop trying to set fields via ctl_reg
1002 * when they should actually be using common SPI framework.
1003 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1004 * Not sure if a user actually needs/uses any of these,
1005 * but let's assume (for now) they do.
1007 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1008 dev_err(&spi->dev, "do not set bits in ctl_reg "
1009 "that the SPI framework manages\n");
1013 chip->enable_dma = chip_info->enable_dma != 0
1014 && drv_data->master_info->enable_dma;
1015 chip->ctl_reg = chip_info->ctl_reg;
1016 chip->bits_per_word = chip_info->bits_per_word;
1017 chip->cs_change_per_word = chip_info->cs_change_per_word;
1018 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1021 /* translate common spi framework into our register */
1022 if (spi->mode & SPI_CPOL)
1023 chip->ctl_reg |= CPOL;
1024 if (spi->mode & SPI_CPHA)
1025 chip->ctl_reg |= CPHA;
1026 if (spi->mode & SPI_LSB_FIRST)
1027 chip->ctl_reg |= LSBF;
1028 /* we dont support running in slave mode (yet?) */
1029 chip->ctl_reg |= MSTR;
1032 * if any one SPI chip is registered and wants DMA, request the
1033 * DMA channel for it
1035 if (chip->enable_dma && !dma_requested) {
1036 /* register dma irq handler */
1037 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) {
1039 "Unable to request BlackFin SPI DMA channel\n");
1042 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data)
1044 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1047 dma_disable_irq(CH_SPI);
1052 * Notice: for blackfin, the speed_hz is the value of register
1053 * SPI_BAUD, not the real baudrate
1055 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1056 spi_flg = ~(1 << (spi->chip_select));
1057 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1058 chip->chip_select_num = spi->chip_select;
1060 switch (chip->bits_per_word) {
1063 chip->width = CFG_SPI_WORDSIZE8;
1064 chip->read = chip->cs_change_per_word ?
1065 u8_cs_chg_reader : u8_reader;
1066 chip->write = chip->cs_change_per_word ?
1067 u8_cs_chg_writer : u8_writer;
1068 chip->duplex = chip->cs_change_per_word ?
1069 u8_cs_chg_duplex : u8_duplex;
1074 chip->width = CFG_SPI_WORDSIZE16;
1075 chip->read = chip->cs_change_per_word ?
1076 u16_cs_chg_reader : u16_reader;
1077 chip->write = chip->cs_change_per_word ?
1078 u16_cs_chg_writer : u16_writer;
1079 chip->duplex = chip->cs_change_per_word ?
1080 u16_cs_chg_duplex : u16_duplex;
1084 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1085 chip->bits_per_word);
1090 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1091 spi->modalias, chip->width, chip->enable_dma);
1092 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1093 chip->ctl_reg, chip->flag);
1095 spi_set_ctldata(spi, chip);
1101 * callback for spi framework.
1102 * clean driver specific data
1104 static void cleanup(struct spi_device *spi)
1106 struct chip_data *chip = spi_get_ctldata(spi);
1111 static inline int init_queue(struct driver_data *drv_data)
1113 INIT_LIST_HEAD(&drv_data->queue);
1114 spin_lock_init(&drv_data->lock);
1116 drv_data->run = QUEUE_STOPPED;
1119 /* init transfer tasklet */
1120 tasklet_init(&drv_data->pump_transfers,
1121 pump_transfers, (unsigned long)drv_data);
1123 /* init messages workqueue */
1124 INIT_WORK(&drv_data->pump_messages, pump_messages);
1125 drv_data->workqueue =
1126 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1127 if (drv_data->workqueue == NULL)
1133 static inline int start_queue(struct driver_data *drv_data)
1135 unsigned long flags;
1137 spin_lock_irqsave(&drv_data->lock, flags);
1139 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1140 spin_unlock_irqrestore(&drv_data->lock, flags);
1144 drv_data->run = QUEUE_RUNNING;
1145 drv_data->cur_msg = NULL;
1146 drv_data->cur_transfer = NULL;
1147 drv_data->cur_chip = NULL;
1148 spin_unlock_irqrestore(&drv_data->lock, flags);
1150 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1155 static inline int stop_queue(struct driver_data *drv_data)
1157 unsigned long flags;
1158 unsigned limit = 500;
1161 spin_lock_irqsave(&drv_data->lock, flags);
1164 * This is a bit lame, but is optimized for the common execution path.
1165 * A wait_queue on the drv_data->busy could be used, but then the common
1166 * execution path (pump_messages) would be required to call wake_up or
1167 * friends on every SPI message. Do this instead
1169 drv_data->run = QUEUE_STOPPED;
1170 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1171 spin_unlock_irqrestore(&drv_data->lock, flags);
1173 spin_lock_irqsave(&drv_data->lock, flags);
1176 if (!list_empty(&drv_data->queue) || drv_data->busy)
1179 spin_unlock_irqrestore(&drv_data->lock, flags);
1184 static inline int destroy_queue(struct driver_data *drv_data)
1188 status = stop_queue(drv_data);
1192 destroy_workqueue(drv_data->workqueue);
1197 static int setup_pin_mux(int action)
1200 u16 pin_req[] = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0};
1203 if (peripheral_request_list(pin_req, DRV_NAME))
1206 peripheral_free_list(pin_req);
1212 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1214 struct device *dev = &pdev->dev;
1215 struct bfin5xx_spi_master *platform_info;
1216 struct spi_master *master;
1217 struct driver_data *drv_data = 0;
1220 platform_info = dev->platform_data;
1222 /* Allocate master with space for drv_data */
1223 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1225 dev_err(&pdev->dev, "can not alloc spi_master\n");
1229 if (setup_pin_mux(1)) {
1230 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1234 drv_data = spi_master_get_devdata(master);
1235 drv_data->master = master;
1236 drv_data->master_info = platform_info;
1237 drv_data->pdev = pdev;
1239 master->bus_num = pdev->id;
1240 master->num_chipselect = platform_info->num_chipselect;
1241 master->cleanup = cleanup;
1242 master->setup = setup;
1243 master->transfer = transfer;
1245 /* Initial and start queue */
1246 status = init_queue(drv_data);
1248 dev_err(&pdev->dev, "problem initializing queue\n");
1249 goto out_error_queue_alloc;
1251 status = start_queue(drv_data);
1253 dev_err(&pdev->dev, "problem starting queue\n");
1254 goto out_error_queue_alloc;
1257 /* Register with the SPI framework */
1258 platform_set_drvdata(pdev, drv_data);
1259 status = spi_register_master(master);
1261 dev_err(&pdev->dev, "problem registering spi master\n");
1262 goto out_error_queue_alloc;
1264 dev_dbg(&pdev->dev, "controller probe successfully\n");
1267 out_error_queue_alloc:
1268 destroy_queue(drv_data);
1270 spi_master_put(master);
1275 /* stop hardware and remove the driver */
1276 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1278 struct driver_data *drv_data = platform_get_drvdata(pdev);
1284 /* Remove the queue */
1285 status = destroy_queue(drv_data);
1289 /* Disable the SSP at the peripheral and SOC level */
1290 bfin_spi_disable(drv_data);
1293 if (drv_data->master_info->enable_dma) {
1294 if (dma_channel_active(CH_SPI))
1298 /* Disconnect from the SPI framework */
1299 spi_unregister_master(drv_data->master);
1303 /* Prevent double remove */
1304 platform_set_drvdata(pdev, NULL);
1310 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1312 struct driver_data *drv_data = platform_get_drvdata(pdev);
1315 status = stop_queue(drv_data);
1320 bfin_spi_disable(drv_data);
1325 static int bfin5xx_spi_resume(struct platform_device *pdev)
1327 struct driver_data *drv_data = platform_get_drvdata(pdev);
1330 /* Enable the SPI interface */
1331 bfin_spi_enable(drv_data);
1333 /* Start the queue running */
1334 status = start_queue(drv_data);
1336 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1343 #define bfin5xx_spi_suspend NULL
1344 #define bfin5xx_spi_resume NULL
1345 #endif /* CONFIG_PM */
1347 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1348 static struct platform_driver bfin5xx_spi_driver = {
1350 .name = "bfin-spi-master",
1351 .owner = THIS_MODULE,
1353 .suspend = bfin5xx_spi_suspend,
1354 .resume = bfin5xx_spi_resume,
1355 .remove = __devexit_p(bfin5xx_spi_remove),
1358 static int __init bfin5xx_spi_init(void)
1360 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1362 module_init(bfin5xx_spi_init);
1364 static void __exit bfin5xx_spi_exit(void)
1366 platform_driver_unregister(&bfin5xx_spi_driver);
1368 module_exit(bfin5xx_spi_exit);