2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 #include <linux/config.h>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/acpi.h>
20 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
21 #define UHCI_USBCMD 0 /* command register */
22 #define UHCI_USBINTR 4 /* interrupt register */
23 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
24 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
25 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
26 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
27 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
28 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
29 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
31 #define OHCI_CONTROL 0x04
32 #define OHCI_CMDSTATUS 0x08
33 #define OHCI_INTRSTATUS 0x0c
34 #define OHCI_INTRENABLE 0x10
35 #define OHCI_INTRDISABLE 0x14
36 #define OHCI_OCR (1 << 3) /* ownership change request */
37 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
38 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
39 #define OHCI_INTR_OC (1 << 30) /* ownership change */
41 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
42 #define EHCI_USBCMD 0 /* command register */
43 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
44 #define EHCI_USBSTS 4 /* status register */
45 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
46 #define EHCI_USBINTR 8 /* interrupt register */
47 #define EHCI_USBLEGSUP 0 /* legacy support register */
48 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
49 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
50 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
51 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
55 * Make sure the controller is completely inactive, unable to
56 * generate interrupts or do DMA.
58 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
60 /* Turn off PIRQ enable and SMI enable. (This also turns off the
61 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
63 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
65 /* Reset the HC - this will force us to get a
66 * new notification of any already connected
67 * ports due to the virtual disconnect that it
70 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
73 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
74 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
76 /* Just to be safe, disable interrupt requests and
77 * make sure the controller is stopped.
79 outw(0, base + UHCI_USBINTR);
80 outw(0, base + UHCI_USBCMD);
82 EXPORT_SYMBOL_GPL(uhci_reset_hc);
85 * Initialize a controller that was newly discovered or has just been
86 * resumed. In either case we can't be sure of its previous state.
88 * Returns: 1 if the controller was reset, 0 otherwise.
90 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
93 unsigned int cmd, intr;
96 * When restarting a suspended controller, we expect all the
97 * settings to be the same as we left them:
99 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
100 * Controller is stopped and configured with EGSM set;
101 * No interrupts enabled except possibly Resume Detect.
103 * If any of these conditions are violated we do a complete reset.
105 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
106 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
107 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
108 __FUNCTION__, legsup);
112 cmd = inw(base + UHCI_USBCMD);
113 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
114 !(cmd & UHCI_USBCMD_EGSM)) {
115 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
120 intr = inw(base + UHCI_USBINTR);
121 if (intr & (~UHCI_USBINTR_RESUME)) {
122 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
129 dev_dbg(&pdev->dev, "Performing full reset\n");
130 uhci_reset_hc(pdev, base);
133 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
135 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
138 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
141 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
142 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
144 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
146 unsigned long base = 0;
149 if (!pio_enabled(pdev))
152 for (i = 0; i < PCI_ROM_RESOURCE; i++)
153 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
154 base = pci_resource_start(pdev, i);
159 uhci_check_and_reset_hc(pdev, base);
162 static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
164 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
167 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
173 if (!mmio_resource_enabled(pdev, 0))
176 base = ioremap_nocache(pci_resource_start(pdev, 0),
177 pci_resource_len(pdev, 0));
178 if (base == NULL) return;
180 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
182 control = readl(base + OHCI_CONTROL);
183 if (control & OHCI_CTRL_IR) {
184 wait_time = 500; /* arbitrary; 5 seconds */
185 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
186 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
187 while (wait_time > 0 &&
188 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
193 printk(KERN_WARNING "%s %s: BIOS handoff "
194 "failed (BIOS bug ?)\n",
195 pdev->dev.bus_id, "OHCI");
197 /* reset controller, preserving RWC */
198 writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL);
205 writel(~(u32)0, base + OHCI_INTRDISABLE);
206 writel(~(u32)0, base + OHCI_INTRSTATUS);
211 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
213 int wait_time, delta;
214 void __iomem *base, *op_reg_base;
216 u8 offset, cap_length;
219 if (!mmio_resource_enabled(pdev, 0))
222 base = ioremap_nocache(pci_resource_start(pdev, 0),
223 pci_resource_len(pdev, 0));
224 if (base == NULL) return;
226 cap_length = readb(base);
227 op_reg_base = base + cap_length;
229 /* EHCI 0.96 and later may have "extended capabilities"
230 * spec section 5.1 explains the bios handoff, e.g. for
231 * booting from USB disk or using a usb keyboard
233 hcc_params = readl(base + EHCI_HCC_PARAMS);
234 offset = (hcc_params >> 8) & 0xff;
235 while (offset && count--) {
239 pci_read_config_dword(pdev, offset, &cap);
240 switch (cap & 0xff) {
241 case 1: /* BIOS/SMM/... handoff support */
242 if ((cap & EHCI_USBLEGSUP_BIOS)) {
243 pr_debug("%s %s: BIOS handoff\n",
244 pdev->dev.bus_id, "EHCI");
246 /* BIOS workaround (?): be sure the
247 * pre-Linux code receives the SMI
249 pci_read_config_dword(pdev,
250 offset + EHCI_USBLEGCTLSTS,
252 pci_write_config_dword(pdev,
253 offset + EHCI_USBLEGCTLSTS,
254 val | EHCI_USBLEGCTLSTS_SOOE);
257 /* always say Linux will own the hardware
258 * by setting EHCI_USBLEGSUP_OS.
260 pci_write_config_byte(pdev, offset + 3, 1);
262 /* if boot firmware now owns EHCI, spin till
266 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
269 pci_read_config_dword(pdev, offset, &cap);
272 if (cap & EHCI_USBLEGSUP_BIOS) {
273 /* well, possibly buggy BIOS... try to shut
274 * it down, and hope nothing goes too wrong
276 printk(KERN_WARNING "%s %s: BIOS handoff "
277 "failed (BIOS bug ?)\n",
278 pdev->dev.bus_id, "EHCI");
279 pci_write_config_byte(pdev, offset + 2, 0);
282 /* just in case, always disable EHCI SMIs */
283 pci_write_config_dword(pdev,
284 offset + EHCI_USBLEGCTLSTS,
287 case 0: /* illegal reserved capability */
291 printk(KERN_WARNING "%s %s: unrecognized "
293 pdev->dev.bus_id, "EHCI",
297 offset = (cap >> 8) & 0xff;
300 printk(KERN_DEBUG "%s %s: capability loop?\n",
301 pdev->dev.bus_id, "EHCI");
304 * halt EHCI & disable its interrupts in any case
306 val = readl(op_reg_base + EHCI_USBSTS);
307 if ((val & EHCI_USBSTS_HALTED) == 0) {
308 val = readl(op_reg_base + EHCI_USBCMD);
309 val &= ~EHCI_USBCMD_RUN;
310 writel(val, op_reg_base + EHCI_USBCMD);
315 writel(0x3f, op_reg_base + EHCI_USBSTS);
318 val = readl(op_reg_base + EHCI_USBSTS);
319 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
322 } while (wait_time > 0);
324 writel(0, op_reg_base + EHCI_USBINTR);
325 writel(0x3f, op_reg_base + EHCI_USBSTS);
334 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
336 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
337 quirk_usb_handoff_uhci(pdev);
338 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
339 quirk_usb_handoff_ohci(pdev);
340 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
341 quirk_usb_disable_ehci(pdev);
343 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);