4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
41 #include "intelfbhw.h"
44 int min_m, max_m, min_m1, max_m1;
45 int min_m2, max_m2, min_n, max_n;
46 int min_p, max_p, min_p1, max_p1;
47 int min_vco, max_vco, p_transition_clk, ref_clk;
48 int p_inc_lo, p_inc_hi;
55 static struct pll_min_max plls[PLLS_MAX] = {
59 930000, 1400000, 165000, 48000,
65 1400000, 2800000, 200000, 96000,
70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
76 switch (pdev->device) {
77 case PCI_DEVICE_ID_INTEL_830M:
78 dinfo->name = "Intel(R) 830M";
79 dinfo->chipset = INTEL_830M;
81 dinfo->pll_index = PLLS_I8xx;
83 case PCI_DEVICE_ID_INTEL_845G:
84 dinfo->name = "Intel(R) 845G";
85 dinfo->chipset = INTEL_845G;
87 dinfo->pll_index = PLLS_I8xx;
89 case PCI_DEVICE_ID_INTEL_85XGM:
92 dinfo->pll_index = PLLS_I8xx;
93 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
94 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
95 INTEL_85X_VARIANT_MASK) {
96 case INTEL_VAR_855GME:
97 dinfo->name = "Intel(R) 855GME";
98 dinfo->chipset = INTEL_855GME;
100 case INTEL_VAR_855GM:
101 dinfo->name = "Intel(R) 855GM";
102 dinfo->chipset = INTEL_855GM;
104 case INTEL_VAR_852GME:
105 dinfo->name = "Intel(R) 852GME";
106 dinfo->chipset = INTEL_852GME;
108 case INTEL_VAR_852GM:
109 dinfo->name = "Intel(R) 852GM";
110 dinfo->chipset = INTEL_852GM;
113 dinfo->name = "Intel(R) 852GM/855GM";
114 dinfo->chipset = INTEL_85XGM;
118 case PCI_DEVICE_ID_INTEL_865G:
119 dinfo->name = "Intel(R) 865G";
120 dinfo->chipset = INTEL_865G;
122 dinfo->pll_index = PLLS_I8xx;
124 case PCI_DEVICE_ID_INTEL_915G:
125 dinfo->name = "Intel(R) 915G";
126 dinfo->chipset = INTEL_915G;
128 dinfo->pll_index = PLLS_I9xx;
130 case PCI_DEVICE_ID_INTEL_915GM:
131 dinfo->name = "Intel(R) 915GM";
132 dinfo->chipset = INTEL_915GM;
134 dinfo->pll_index = PLLS_I9xx;
136 case PCI_DEVICE_ID_INTEL_945G:
137 dinfo->name = "Intel(R) 945G";
138 dinfo->chipset = INTEL_945G;
140 dinfo->pll_index = PLLS_I9xx;
142 case PCI_DEVICE_ID_INTEL_945GM:
143 dinfo->name = "Intel(R) 945GM";
144 dinfo->chipset = INTEL_945GM;
146 dinfo->pll_index = PLLS_I9xx;
154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
157 struct pci_dev *bridge_dev;
161 if (!pdev || !aperture_size || !stolen_size)
164 /* Find the bridge device. It is always 0:0.0 */
165 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
166 ERR_MSG("cannot find bridge device\n");
170 /* Get the fb aperture size and "stolen" memory amount. */
172 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
173 switch (pdev->device) {
174 case PCI_DEVICE_ID_INTEL_915G:
175 case PCI_DEVICE_ID_INTEL_915GM:
176 case PCI_DEVICE_ID_INTEL_945G:
177 case PCI_DEVICE_ID_INTEL_945GM:
178 /* 915 and 945 chipsets support a 256MB aperture.
179 Aperture size is determined by inspected the
180 base address of the aperture. */
181 if (pci_resource_start(pdev, 2) & 0x08000000)
182 *aperture_size = MB(128);
184 *aperture_size = MB(256);
187 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
188 *aperture_size = MB(64);
190 *aperture_size = MB(128);
194 /* Stolen memory size is reduced by the GTT and the popup.
195 GTT is 1K per MB of aperture size, and popup is 4K. */
196 stolen_overhead = (*aperture_size / MB(1)) + 4;
197 switch(pdev->device) {
198 case PCI_DEVICE_ID_INTEL_830M:
199 case PCI_DEVICE_ID_INTEL_845G:
200 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
201 case INTEL_830_GMCH_GMS_STOLEN_512:
202 *stolen_size = KB(512) - KB(stolen_overhead);
204 case INTEL_830_GMCH_GMS_STOLEN_1024:
205 *stolen_size = MB(1) - KB(stolen_overhead);
207 case INTEL_830_GMCH_GMS_STOLEN_8192:
208 *stolen_size = MB(8) - KB(stolen_overhead);
210 case INTEL_830_GMCH_GMS_LOCAL:
211 ERR_MSG("only local memory found\n");
213 case INTEL_830_GMCH_GMS_DISABLED:
214 ERR_MSG("video memory is disabled\n");
217 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
218 tmp & INTEL_830_GMCH_GMS_MASK);
223 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
224 case INTEL_855_GMCH_GMS_STOLEN_1M:
225 *stolen_size = MB(1) - KB(stolen_overhead);
227 case INTEL_855_GMCH_GMS_STOLEN_4M:
228 *stolen_size = MB(4) - KB(stolen_overhead);
230 case INTEL_855_GMCH_GMS_STOLEN_8M:
231 *stolen_size = MB(8) - KB(stolen_overhead);
233 case INTEL_855_GMCH_GMS_STOLEN_16M:
234 *stolen_size = MB(16) - KB(stolen_overhead);
236 case INTEL_855_GMCH_GMS_STOLEN_32M:
237 *stolen_size = MB(32) - KB(stolen_overhead);
239 case INTEL_915G_GMCH_GMS_STOLEN_48M:
240 *stolen_size = MB(48) - KB(stolen_overhead);
242 case INTEL_915G_GMCH_GMS_STOLEN_64M:
243 *stolen_size = MB(64) - KB(stolen_overhead);
245 case INTEL_855_GMCH_GMS_DISABLED:
246 ERR_MSG("video memory is disabled\n");
249 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
250 tmp & INTEL_855_GMCH_GMS_MASK);
257 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
261 if (INREG(LVDS) & PORT_ENABLE)
263 if (INREG(DVOA) & PORT_ENABLE)
265 if (INREG(DVOB) & PORT_ENABLE)
267 if (INREG(DVOC) & PORT_ENABLE)
274 intelfbhw_dvo_to_string(int dvo)
278 else if (dvo & DVOB_PORT)
280 else if (dvo & DVOC_PORT)
282 else if (dvo & LVDS_PORT)
290 intelfbhw_validate_mode(struct intelfb_info *dinfo,
291 struct fb_var_screeninfo *var)
297 DBG_MSG("intelfbhw_validate_mode\n");
300 bytes_per_pixel = var->bits_per_pixel / 8;
301 if (bytes_per_pixel == 3)
304 /* Check if enough video memory. */
305 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
306 if (tmp > dinfo->fb.size) {
307 WRN_MSG("Not enough video ram for mode "
308 "(%d KByte vs %d KByte).\n",
309 BtoKB(tmp), BtoKB(dinfo->fb.size));
313 /* Check if x/y limits are OK. */
314 if (var->xres - 1 > HACTIVE_MASK) {
315 WRN_MSG("X resolution too large (%d vs %d).\n",
316 var->xres, HACTIVE_MASK + 1);
319 if (var->yres - 1 > VACTIVE_MASK) {
320 WRN_MSG("Y resolution too large (%d vs %d).\n",
321 var->yres, VACTIVE_MASK + 1);
325 /* Check for interlaced/doublescan modes. */
326 if (var->vmode & FB_VMODE_INTERLACED) {
327 WRN_MSG("Mode is interlaced.\n");
330 if (var->vmode & FB_VMODE_DOUBLE) {
331 WRN_MSG("Mode is double-scan.\n");
335 /* Check if clock is OK. */
336 tmp = 1000000000 / var->pixclock;
337 if (tmp < MIN_CLOCK) {
338 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
339 (tmp + 500) / 1000, MIN_CLOCK / 1000);
342 if (tmp > MAX_CLOCK) {
343 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
344 (tmp + 500) / 1000, MAX_CLOCK / 1000);
352 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
354 struct intelfb_info *dinfo = GET_DINFO(info);
355 u32 offset, xoffset, yoffset;
358 DBG_MSG("intelfbhw_pan_display\n");
361 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
362 yoffset = var->yoffset;
364 if ((xoffset + var->xres > var->xres_virtual) ||
365 (yoffset + var->yres > var->yres_virtual))
368 offset = (yoffset * dinfo->pitch) +
369 (xoffset * var->bits_per_pixel) / 8;
371 offset += dinfo->fb.offset << 12;
373 OUTREG(DSPABASE, offset);
378 /* Blank the screen. */
380 intelfbhw_do_blank(int blank, struct fb_info *info)
382 struct intelfb_info *dinfo = GET_DINFO(info);
386 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
389 /* Turn plane A on or off */
390 tmp = INREG(DSPACNTR);
392 tmp &= ~DISPPLANE_PLANE_ENABLE;
394 tmp |= DISPPLANE_PLANE_ENABLE;
395 OUTREG(DSPACNTR, tmp);
397 tmp = INREG(DSPABASE);
398 OUTREG(DSPABASE, tmp);
400 /* Turn off/on the HW cursor */
402 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
404 if (dinfo->cursor_on) {
406 intelfbhw_cursor_hide(dinfo);
408 intelfbhw_cursor_show(dinfo);
410 dinfo->cursor_on = 1;
412 dinfo->cursor_blanked = blank;
415 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
417 case FB_BLANK_UNBLANK:
418 case FB_BLANK_NORMAL:
421 case FB_BLANK_VSYNC_SUSPEND:
424 case FB_BLANK_HSYNC_SUSPEND:
427 case FB_BLANK_POWERDOWN:
438 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
439 unsigned red, unsigned green, unsigned blue,
443 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
444 regno, red, green, blue);
447 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
448 PALETTE_A : PALETTE_B;
450 OUTREG(palette_reg + (regno << 2),
451 (red << PALETTE_8_RED_SHIFT) |
452 (green << PALETTE_8_GREEN_SHIFT) |
453 (blue << PALETTE_8_BLUE_SHIFT));
458 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
464 DBG_MSG("intelfbhw_read_hw_state\n");
470 /* Read in as much of the HW state as possible. */
471 hw->vga0_divisor = INREG(VGA0_DIVISOR);
472 hw->vga1_divisor = INREG(VGA1_DIVISOR);
473 hw->vga_pd = INREG(VGAPD);
474 hw->dpll_a = INREG(DPLL_A);
475 hw->dpll_b = INREG(DPLL_B);
476 hw->fpa0 = INREG(FPA0);
477 hw->fpa1 = INREG(FPA1);
478 hw->fpb0 = INREG(FPB0);
479 hw->fpb1 = INREG(FPB1);
485 /* This seems to be a problem with the 852GM/855GM */
486 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
487 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
488 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
495 hw->htotal_a = INREG(HTOTAL_A);
496 hw->hblank_a = INREG(HBLANK_A);
497 hw->hsync_a = INREG(HSYNC_A);
498 hw->vtotal_a = INREG(VTOTAL_A);
499 hw->vblank_a = INREG(VBLANK_A);
500 hw->vsync_a = INREG(VSYNC_A);
501 hw->src_size_a = INREG(SRC_SIZE_A);
502 hw->bclrpat_a = INREG(BCLRPAT_A);
503 hw->htotal_b = INREG(HTOTAL_B);
504 hw->hblank_b = INREG(HBLANK_B);
505 hw->hsync_b = INREG(HSYNC_B);
506 hw->vtotal_b = INREG(VTOTAL_B);
507 hw->vblank_b = INREG(VBLANK_B);
508 hw->vsync_b = INREG(VSYNC_B);
509 hw->src_size_b = INREG(SRC_SIZE_B);
510 hw->bclrpat_b = INREG(BCLRPAT_B);
515 hw->adpa = INREG(ADPA);
516 hw->dvoa = INREG(DVOA);
517 hw->dvob = INREG(DVOB);
518 hw->dvoc = INREG(DVOC);
519 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
520 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
521 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
522 hw->lvds = INREG(LVDS);
527 hw->pipe_a_conf = INREG(PIPEACONF);
528 hw->pipe_b_conf = INREG(PIPEBCONF);
529 hw->disp_arb = INREG(DISPARB);
534 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
535 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
536 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
537 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
542 for (i = 0; i < 4; i++) {
543 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
544 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
550 hw->cursor_size = INREG(CURSOR_SIZE);
555 hw->disp_a_ctrl = INREG(DSPACNTR);
556 hw->disp_b_ctrl = INREG(DSPBCNTR);
557 hw->disp_a_base = INREG(DSPABASE);
558 hw->disp_b_base = INREG(DSPBBASE);
559 hw->disp_a_stride = INREG(DSPASTRIDE);
560 hw->disp_b_stride = INREG(DSPBSTRIDE);
565 hw->vgacntrl = INREG(VGACNTRL);
570 hw->add_id = INREG(ADD_ID);
575 for (i = 0; i < 7; i++) {
576 hw->swf0x[i] = INREG(SWF00 + (i << 2));
577 hw->swf1x[i] = INREG(SWF10 + (i << 2));
579 hw->swf3x[i] = INREG(SWF30 + (i << 2));
582 for (i = 0; i < 8; i++)
583 hw->fence[i] = INREG(FENCE + (i << 2));
585 hw->instpm = INREG(INSTPM);
586 hw->mem_mode = INREG(MEM_MODE);
587 hw->fw_blc_0 = INREG(FW_BLC_0);
588 hw->fw_blc_1 = INREG(FW_BLC_1);
590 hw->hwstam = INREG16(HWSTAM);
591 hw->ier = INREG16(IER);
592 hw->iir = INREG16(IIR);
593 hw->imr = INREG16(IMR);
599 static int calc_vclock3(int index, int m, int n, int p)
601 if (p == 0 || n == 0)
603 return plls[index].ref_clk * m / n / p;
606 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
608 struct pll_min_max *pll = &plls[index];
611 m = (5 * (m1 + 2)) + (m2 + 2);
613 vco = pll->ref_clk * m / n;
615 if (index == PLLS_I8xx) {
616 p = ((p1 + 2) * (1 << (p2 + 1)));
618 p = ((p1) * (p2 ? 5 : 10));
624 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
628 if (IS_I9XX(dinfo)) {
629 if (dpll & DPLL_P1_FORCE_DIV2)
632 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
636 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
638 if (dpll & DPLL_P1_FORCE_DIV2)
641 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
642 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
651 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
654 int i, m1, m2, n, p1, p2;
655 int index = dinfo->pll_index;
656 DBG_MSG("intelfbhw_print_hw_state\n");
660 /* Read in as much of the HW state as possible. */
661 printk("hw state dump start\n");
662 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
663 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
664 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
665 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
666 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
667 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
669 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
671 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
673 printk(" VGA0: clock is %d\n",
674 calc_vclock(index, m1, m2, n, p1, p2, 0));
676 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
677 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
678 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
680 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
681 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
683 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
685 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
686 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
687 printk(" FPA0: 0x%08x\n", hw->fpa0);
688 printk(" FPA1: 0x%08x\n", hw->fpa1);
689 printk(" FPB0: 0x%08x\n", hw->fpb0);
690 printk(" FPB1: 0x%08x\n", hw->fpb1);
692 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
693 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
694 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
696 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
698 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
700 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
702 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
703 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
704 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
706 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
708 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
710 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
713 printk(" PALETTE_A:\n");
714 for (i = 0; i < PALETTE_8_ENTRIES)
715 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
716 printk(" PALETTE_B:\n");
717 for (i = 0; i < PALETTE_8_ENTRIES)
718 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
721 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
722 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
723 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
724 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
725 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
726 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
727 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
728 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
729 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
730 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
731 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
732 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
733 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
734 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
735 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
736 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
738 printk(" ADPA: 0x%08x\n", hw->adpa);
739 printk(" DVOA: 0x%08x\n", hw->dvoa);
740 printk(" DVOB: 0x%08x\n", hw->dvob);
741 printk(" DVOC: 0x%08x\n", hw->dvoc);
742 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
743 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
744 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
745 printk(" LVDS: 0x%08x\n", hw->lvds);
747 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
748 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
749 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
751 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
752 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
753 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
754 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
756 printk(" CURSOR_A_PALETTE: ");
757 for (i = 0; i < 4; i++) {
758 printk("0x%08x", hw->cursor_a_palette[i]);
763 printk(" CURSOR_B_PALETTE: ");
764 for (i = 0; i < 4; i++) {
765 printk("0x%08x", hw->cursor_b_palette[i]);
771 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
773 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
774 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
775 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
776 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
777 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
778 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
780 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
781 printk(" ADD_ID: 0x%08x\n", hw->add_id);
783 for (i = 0; i < 7; i++) {
784 printk(" SWF0%d 0x%08x\n", i,
787 for (i = 0; i < 7; i++) {
788 printk(" SWF1%d 0x%08x\n", i,
791 for (i = 0; i < 3; i++) {
792 printk(" SWF3%d 0x%08x\n", i,
795 for (i = 0; i < 8; i++)
796 printk(" FENCE%d 0x%08x\n", i,
799 printk(" INSTPM 0x%08x\n", hw->instpm);
800 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
801 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
802 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
804 printk(" HWSTAM 0x%04x\n", hw->hwstam);
805 printk(" IER 0x%04x\n", hw->ier);
806 printk(" IIR 0x%04x\n", hw->iir);
807 printk(" IMR 0x%04x\n", hw->imr);
808 printk("hw state dump end\n");
814 /* Split the M parameter into M1 and M2. */
816 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
820 struct pll_min_max *pll = &plls[index];
822 /* no point optimising too much - brute force m */
823 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
824 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
825 testm = (5 * (m1 + 2)) + (m2 + 2);
827 *retm1 = (unsigned int)m1;
828 *retm2 = (unsigned int)m2;
836 /* Split the P parameter into P1 and P2. */
838 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
841 struct pll_min_max *pll = &plls[index];
843 if (index == PLLS_I9xx) {
844 p2 = (p % 10) ? 1 : 0;
846 p1 = p / (p2 ? 5 : 10);
848 *retp1 = (unsigned int)p1;
849 *retp2 = (unsigned int)p2;
857 p1 = (p / (1 << (p2 + 1))) - 2;
858 if (p % 4 == 0 && p1 < pll->min_p1) {
860 p1 = (p / (1 << (p2 + 1))) - 2;
862 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
863 (p1 + 2) * (1 << (p2 + 1)) != p) {
866 *retp1 = (unsigned int)p1;
867 *retp2 = (unsigned int)p2;
873 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
874 u32 *retp2, u32 *retclock)
876 u32 m1, m2, n, p1, p2, n1, testm;
877 u32 f_vco, p, p_best = 0, m, f_out = 0;
878 u32 err_max, err_target, err_best = 10000000;
879 u32 n_best = 0, m_best = 0, f_best, f_err;
880 u32 p_min, p_max, p_inc, div_max;
881 struct pll_min_max *pll = &plls[index];
883 /* Accept 0.5% difference, but aim for 0.1% */
884 err_max = 5 * clock / 1000;
885 err_target = clock / 1000;
887 DBG_MSG("Clock is %d\n", clock);
889 div_max = pll->max_vco / clock;
891 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
893 p_max = ROUND_DOWN_TO(div_max, p_inc);
894 if (p_min < pll->min_p)
896 if (p_max > pll->max_p)
899 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
903 if (splitp(index, p, &p1, &p2)) {
904 WRN_MSG("cannot split p = %d\n", p);
912 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
917 for (testm = m - 1; testm <= m; testm++) {
918 f_out = calc_vclock3(index, m, n, p);
919 if (splitm(index, testm, &m1, &m2)) {
920 WRN_MSG("cannot split m = %d\n", m);
925 f_err = clock - f_out;
926 else/* slightly bias the error for bigger clocks */
927 f_err = f_out - clock + 1;
929 if (f_err < err_best) {
938 } while ((n <= pll->max_n) && (f_out >= clock));
940 } while ((p <= p_max));
943 WRN_MSG("cannot find parameters for clock %d\n", clock);
949 splitm(index, m, &m1, &m2);
950 splitp(index, p, &p1, &p2);
953 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
954 "f: %d (%d), VCO: %d\n",
955 m, m1, m2, n, n1, p, p1, p2,
956 calc_vclock3(index, m, n, p),
957 calc_vclock(index, m1, m2, n1, p1, p2, 0),
958 calc_vclock3(index, m, n, p) * p);
964 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
969 static __inline__ int
970 check_overflow(u32 value, u32 limit, const char *description)
973 WRN_MSG("%s value %d exceeds limit %d\n",
974 description, value, limit);
980 /* It is assumed that hw is filled in with the initial state information. */
982 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
983 struct fb_var_screeninfo *var)
986 u32 *dpll, *fp0, *fp1;
987 u32 m1, m2, n, p1, p2, clock_target, clock;
988 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
989 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
990 u32 vsync_pol, hsync_pol;
991 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
992 u32 stride_alignment;
994 DBG_MSG("intelfbhw_mode_to_hw\n");
997 hw->vgacntrl |= VGA_DISABLE;
999 /* Check whether pipe A or pipe B is enabled. */
1000 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1002 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1005 /* Set which pipe's registers will be set. */
1006 if (pipe == PIPE_B) {
1016 ss = &hw->src_size_b;
1017 pipe_conf = &hw->pipe_b_conf;
1028 ss = &hw->src_size_a;
1029 pipe_conf = &hw->pipe_a_conf;
1032 /* Use ADPA register for sync control. */
1033 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1036 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1037 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1038 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1039 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1040 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1041 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1042 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1043 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1045 /* Connect correct pipe to the analog port DAC */
1046 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1047 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1049 /* Set DPMS state to D0 (on) */
1050 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1051 hw->adpa |= ADPA_DPMS_D0;
1053 hw->adpa |= ADPA_DAC_ENABLE;
1055 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1056 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1057 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1059 /* Desired clock in kHz */
1060 clock_target = 1000000000 / var->pixclock;
1062 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1063 &n, &p1, &p2, &clock)) {
1064 WRN_MSG("calc_pll_params failed\n");
1068 /* Check for overflow. */
1069 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1071 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1073 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1075 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1077 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1080 *dpll &= ~DPLL_P1_FORCE_DIV2;
1081 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1082 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1084 if (IS_I9XX(dinfo)) {
1085 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1086 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1088 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1091 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1092 (m1 << FP_M1_DIVISOR_SHIFT) |
1093 (m2 << FP_M2_DIVISOR_SHIFT);
1096 hw->dvob &= ~PORT_ENABLE;
1097 hw->dvoc &= ~PORT_ENABLE;
1099 /* Use display plane A. */
1100 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1101 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1102 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1103 switch (intelfb_var_to_depth(var)) {
1105 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1108 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1111 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1114 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1117 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1118 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1120 /* Set CRTC registers. */
1121 hactive = var->xres;
1122 hsync_start = hactive + var->right_margin;
1123 hsync_end = hsync_start + var->hsync_len;
1124 htotal = hsync_end + var->left_margin;
1125 hblank_start = hactive;
1126 hblank_end = htotal;
1128 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1129 hactive, hsync_start, hsync_end, htotal, hblank_start,
1132 vactive = var->yres;
1133 vsync_start = vactive + var->lower_margin;
1134 vsync_end = vsync_start + var->vsync_len;
1135 vtotal = vsync_end + var->upper_margin;
1136 vblank_start = vactive;
1137 vblank_end = vtotal;
1138 vblank_end = vsync_end + 1;
1140 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1141 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1144 /* Adjust for register values, and check for overflow. */
1146 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1149 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1152 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1155 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1158 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1161 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1165 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1168 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1171 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1174 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1177 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1180 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1183 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1184 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1185 (hblank_end << HSYNCEND_SHIFT);
1186 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1188 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1189 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1190 (vblank_end << VSYNCEND_SHIFT);
1191 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1192 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1193 (vactive << SRC_SIZE_VERT_SHIFT);
1195 hw->disp_a_stride = dinfo->pitch;
1196 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1198 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1199 var->xoffset * var->bits_per_pixel / 8;
1201 hw->disp_a_base += dinfo->fb.offset << 12;
1203 /* Check stride alignment. */
1204 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1206 if (hw->disp_a_stride % stride_alignment != 0) {
1207 WRN_MSG("display stride %d has bad alignment %d\n",
1208 hw->disp_a_stride, stride_alignment);
1212 /* Set the palette to 8-bit mode. */
1213 *pipe_conf &= ~PIPECONF_GAMMA;
1217 /* Program a (non-VGA) video mode. */
1219 intelfbhw_program_mode(struct intelfb_info *dinfo,
1220 const struct intelfb_hwstate *hw, int blank)
1224 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1225 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1226 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1227 u32 hsync_reg, htotal_reg, hblank_reg;
1228 u32 vsync_reg, vtotal_reg, vblank_reg;
1230 u32 count, tmp_val[3];
1232 /* Assume single pipe, display plane A, analog CRT. */
1235 DBG_MSG("intelfbhw_program_mode\n");
1239 tmp = INREG(VGACNTRL);
1241 OUTREG(VGACNTRL, tmp);
1243 /* Check whether pipe A or pipe B is enabled. */
1244 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1246 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1251 if (pipe == PIPE_B) {
1255 pipe_conf = &hw->pipe_b_conf;
1262 ss = &hw->src_size_b;
1266 pipe_conf_reg = PIPEBCONF;
1267 hsync_reg = HSYNC_B;
1268 htotal_reg = HTOTAL_B;
1269 hblank_reg = HBLANK_B;
1270 vsync_reg = VSYNC_B;
1271 vtotal_reg = VTOTAL_B;
1272 vblank_reg = VBLANK_B;
1273 src_size_reg = SRC_SIZE_B;
1278 pipe_conf = &hw->pipe_a_conf;
1285 ss = &hw->src_size_a;
1289 pipe_conf_reg = PIPEACONF;
1290 hsync_reg = HSYNC_A;
1291 htotal_reg = HTOTAL_A;
1292 hblank_reg = HBLANK_A;
1293 vsync_reg = VSYNC_A;
1294 vtotal_reg = VTOTAL_A;
1295 vblank_reg = VBLANK_A;
1296 src_size_reg = SRC_SIZE_A;
1300 tmp = INREG(pipe_conf_reg);
1301 tmp &= ~PIPECONF_ENABLE;
1302 OUTREG(pipe_conf_reg, tmp);
1306 tmp_val[count%3] = INREG(0x70000);
1307 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1311 if (count % 200 == 0) {
1312 tmp = INREG(pipe_conf_reg);
1313 tmp &= ~PIPECONF_ENABLE;
1314 OUTREG(pipe_conf_reg, tmp);
1316 } while(count < 2000);
1318 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1320 /* Disable planes A and B. */
1321 tmp = INREG(DSPACNTR);
1322 tmp &= ~DISPPLANE_PLANE_ENABLE;
1323 OUTREG(DSPACNTR, tmp);
1324 tmp = INREG(DSPBCNTR);
1325 tmp &= ~DISPPLANE_PLANE_ENABLE;
1326 OUTREG(DSPBCNTR, tmp);
1328 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1331 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1332 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1333 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1337 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1338 tmp |= ADPA_DPMS_D3;
1341 /* do some funky magic - xyzzy */
1342 OUTREG(0x61204, 0xabcd0000);
1345 tmp = INREG(dpll_reg);
1346 dpll_reg &= ~DPLL_VCO_ENABLE;
1347 OUTREG(dpll_reg, tmp);
1349 /* Set PLL parameters */
1350 OUTREG(fp0_reg, *fp0);
1351 OUTREG(fp1_reg, *fp1);
1354 OUTREG(dpll_reg, *dpll);
1357 OUTREG(DVOB, hw->dvob);
1358 OUTREG(DVOC, hw->dvoc);
1360 /* undo funky magic */
1361 OUTREG(0x61204, 0x00000000);
1364 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1365 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1367 /* Set pipe parameters */
1368 OUTREG(hsync_reg, *hs);
1369 OUTREG(hblank_reg, *hb);
1370 OUTREG(htotal_reg, *ht);
1371 OUTREG(vsync_reg, *vs);
1372 OUTREG(vblank_reg, *vb);
1373 OUTREG(vtotal_reg, *vt);
1374 OUTREG(src_size_reg, *ss);
1377 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1381 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1382 tmp |= ADPA_DPMS_D0;
1385 /* setup display plane */
1386 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1388 * i830M errata: the display plane must be enabled
1389 * to allow writes to the other bits in the plane
1392 tmp = INREG(DSPACNTR);
1393 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1394 tmp |= DISPPLANE_PLANE_ENABLE;
1395 OUTREG(DSPACNTR, tmp);
1397 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1402 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1403 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1404 OUTREG(DSPABASE, hw->disp_a_base);
1408 tmp = INREG(DSPACNTR);
1409 tmp |= DISPPLANE_PLANE_ENABLE;
1410 OUTREG(DSPACNTR, tmp);
1411 OUTREG(DSPABASE, hw->disp_a_base);
1417 /* forward declarations */
1418 static void refresh_ring(struct intelfb_info *dinfo);
1419 static void reset_state(struct intelfb_info *dinfo);
1420 static void do_flush(struct intelfb_info *dinfo);
1423 wait_ring(struct intelfb_info *dinfo, int n)
1427 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1430 DBG_MSG("wait_ring: %d\n", n);
1433 end = jiffies + (HZ * 3);
1434 while (dinfo->ring_space < n) {
1435 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1436 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1437 dinfo->ring_space = dinfo->ring_head
1438 - (dinfo->ring_tail + RING_MIN_FREE);
1440 dinfo->ring_space = (dinfo->ring.size +
1442 - (dinfo->ring_tail + RING_MIN_FREE);
1443 if (dinfo->ring_head != last_head) {
1444 end = jiffies + (HZ * 3);
1445 last_head = dinfo->ring_head;
1448 if (time_before(end, jiffies)) {
1452 refresh_ring(dinfo);
1454 end = jiffies + (HZ * 3);
1457 WRN_MSG("ring buffer : space: %d wanted %d\n",
1458 dinfo->ring_space, n);
1459 WRN_MSG("lockup - turning off hardware "
1461 dinfo->ring_lockup = 1;
1471 do_flush(struct intelfb_info *dinfo) {
1473 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1479 intelfbhw_do_sync(struct intelfb_info *dinfo)
1482 DBG_MSG("intelfbhw_do_sync\n");
1489 * Send a flush, then wait until the ring is empty. This is what
1490 * the XFree86 driver does, and actually it doesn't seem a lot worse
1491 * than the recommended method (both have problems).
1494 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1495 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1499 refresh_ring(struct intelfb_info *dinfo)
1502 DBG_MSG("refresh_ring\n");
1505 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1506 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1507 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1508 dinfo->ring_space = dinfo->ring_head
1509 - (dinfo->ring_tail + RING_MIN_FREE);
1511 dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
1512 - (dinfo->ring_tail + RING_MIN_FREE);
1516 reset_state(struct intelfb_info *dinfo)
1522 DBG_MSG("reset_state\n");
1525 for (i = 0; i < FENCE_NUM; i++)
1526 OUTREG(FENCE + (i << 2), 0);
1528 /* Flush the ring buffer if it's enabled. */
1529 tmp = INREG(PRI_RING_LENGTH);
1530 if (tmp & RING_ENABLE) {
1532 DBG_MSG("reset_state: ring was enabled\n");
1534 refresh_ring(dinfo);
1535 intelfbhw_do_sync(dinfo);
1539 OUTREG(PRI_RING_LENGTH, 0);
1540 OUTREG(PRI_RING_HEAD, 0);
1541 OUTREG(PRI_RING_TAIL, 0);
1542 OUTREG(PRI_RING_START, 0);
1545 /* Stop the 2D engine, and turn off the ring buffer. */
1547 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1550 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1551 dinfo->ring_active);
1557 dinfo->ring_active = 0;
1562 * Enable the ring buffer, and initialise the 2D engine.
1563 * It is assumed that the graphics engine has been stopped by previously
1564 * calling intelfb_2d_stop().
1567 intelfbhw_2d_start(struct intelfb_info *dinfo)
1570 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1571 dinfo->accel, dinfo->ring_active);
1577 /* Initialise the primary ring buffer. */
1578 OUTREG(PRI_RING_LENGTH, 0);
1579 OUTREG(PRI_RING_TAIL, 0);
1580 OUTREG(PRI_RING_HEAD, 0);
1582 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1583 OUTREG(PRI_RING_LENGTH,
1584 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1585 RING_NO_REPORT | RING_ENABLE);
1586 refresh_ring(dinfo);
1587 dinfo->ring_active = 1;
1590 /* 2D fillrect (solid fill or invert) */
1592 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1593 u32 color, u32 pitch, u32 bpp, u32 rop)
1595 u32 br00, br09, br13, br14, br16;
1598 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1599 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1602 br00 = COLOR_BLT_CMD;
1603 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1604 br13 = (rop << ROP_SHIFT) | pitch;
1605 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1610 br13 |= COLOR_DEPTH_8;
1613 br13 |= COLOR_DEPTH_16;
1616 br13 |= COLOR_DEPTH_32;
1617 br00 |= WRITE_ALPHA | WRITE_RGB;
1631 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1632 dinfo->ring_tail, dinfo->ring_space);
1637 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1638 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1640 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1643 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1644 curx, cury, dstx, dsty, w, h, pitch, bpp);
1647 br00 = XY_SRC_COPY_BLT_CMD;
1648 br09 = dinfo->fb_start;
1649 br11 = (pitch << PITCH_SHIFT);
1650 br12 = dinfo->fb_start;
1651 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1652 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1653 br23 = ((dstx + w) << WIDTH_SHIFT) |
1654 ((dsty + h) << HEIGHT_SHIFT);
1655 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1659 br13 |= COLOR_DEPTH_8;
1662 br13 |= COLOR_DEPTH_16;
1665 br13 |= COLOR_DEPTH_32;
1666 br00 |= WRITE_ALPHA | WRITE_RGB;
1683 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1684 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1686 int nbytes, ndwords, pad, tmp;
1687 u32 br00, br09, br13, br18, br19, br22, br23;
1688 int dat, ix, iy, iw;
1692 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1695 /* size in bytes of a padded scanline */
1696 nbytes = ROUND_UP_TO(w, 16) / 8;
1698 /* Total bytes of padded scanline data to write out. */
1699 nbytes = nbytes * h;
1702 * Check if the glyph data exceeds the immediate mode limit.
1703 * It would take a large font (1K pixels) to hit this limit.
1705 if (nbytes > MAX_MONO_IMM_SIZE)
1708 /* Src data is packaged a dword (32-bit) at a time. */
1709 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1712 * Ring has to be padded to a quad word. But because the command starts
1713 with 7 bytes, pad only if there is an even number of ndwords
1715 pad = !(ndwords % 2);
1717 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1718 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1719 br09 = dinfo->fb_start;
1720 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1723 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1724 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1728 br13 |= COLOR_DEPTH_8;
1731 br13 |= COLOR_DEPTH_16;
1734 br13 |= COLOR_DEPTH_32;
1735 br00 |= WRITE_ALPHA | WRITE_RGB;
1739 START_RING(8 + ndwords);
1748 iw = ROUND_UP_TO(w, 8) / 8;
1751 for (j = 0; j < 2; ++j) {
1752 for (i = 0; i < 2; ++i) {
1753 if (ix != iw || i == 0)
1754 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1756 if (ix == iw && iy != (h-1)) {
1770 /* HW cursor functions. */
1772 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1777 DBG_MSG("intelfbhw_cursor_init\n");
1780 if (dinfo->mobile || IS_I9XX(dinfo)) {
1781 if (!dinfo->cursor.physical)
1783 tmp = INREG(CURSOR_A_CONTROL);
1784 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1785 CURSOR_MEM_TYPE_LOCAL |
1786 (1 << CURSOR_PIPE_SELECT_SHIFT));
1787 tmp |= CURSOR_MODE_DISABLE;
1788 OUTREG(CURSOR_A_CONTROL, tmp);
1789 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1791 tmp = INREG(CURSOR_CONTROL);
1792 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1793 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1794 tmp = CURSOR_FORMAT_3C;
1795 OUTREG(CURSOR_CONTROL, tmp);
1796 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1797 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1798 (64 << CURSOR_SIZE_V_SHIFT);
1799 OUTREG(CURSOR_SIZE, tmp);
1804 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1809 DBG_MSG("intelfbhw_cursor_hide\n");
1812 dinfo->cursor_on = 0;
1813 if (dinfo->mobile || IS_I9XX(dinfo)) {
1814 if (!dinfo->cursor.physical)
1816 tmp = INREG(CURSOR_A_CONTROL);
1817 tmp &= ~CURSOR_MODE_MASK;
1818 tmp |= CURSOR_MODE_DISABLE;
1819 OUTREG(CURSOR_A_CONTROL, tmp);
1821 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1823 tmp = INREG(CURSOR_CONTROL);
1824 tmp &= ~CURSOR_ENABLE;
1825 OUTREG(CURSOR_CONTROL, tmp);
1830 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1835 DBG_MSG("intelfbhw_cursor_show\n");
1838 dinfo->cursor_on = 1;
1840 if (dinfo->cursor_blanked)
1843 if (dinfo->mobile || IS_I9XX(dinfo)) {
1844 if (!dinfo->cursor.physical)
1846 tmp = INREG(CURSOR_A_CONTROL);
1847 tmp &= ~CURSOR_MODE_MASK;
1848 tmp |= CURSOR_MODE_64_4C_AX;
1849 OUTREG(CURSOR_A_CONTROL, tmp);
1851 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1853 tmp = INREG(CURSOR_CONTROL);
1854 tmp |= CURSOR_ENABLE;
1855 OUTREG(CURSOR_CONTROL, tmp);
1860 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1865 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1869 * Sets the position. The coordinates are assumed to already
1870 * have any offset adjusted. Assume that the cursor is never
1871 * completely off-screen, and that x, y are always >= 0.
1874 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1875 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1876 OUTREG(CURSOR_A_POSITION, tmp);
1878 if (IS_I9XX(dinfo)) {
1879 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1884 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1887 DBG_MSG("intelfbhw_cursor_setcolor\n");
1890 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1891 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1892 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1893 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1897 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1900 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1901 int i, j, w = width / 8;
1902 int mod = width % 8, t_mask, d_mask;
1905 DBG_MSG("intelfbhw_cursor_load\n");
1908 if (!dinfo->cursor.virtual)
1911 t_mask = 0xff >> mod;
1912 d_mask = ~(0xff >> mod);
1913 for (i = height; i--; ) {
1914 for (j = 0; j < w; j++) {
1915 writeb(0x00, addr + j);
1916 writeb(*(data++), addr + j+8);
1919 writeb(t_mask, addr + j);
1920 writeb(*(data++) & d_mask, addr + j+8);
1927 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1928 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1932 DBG_MSG("intelfbhw_cursor_reset\n");
1935 if (!dinfo->cursor.virtual)
1938 for (i = 64; i--; ) {
1939 for (j = 0; j < 8; j++) {
1940 writeb(0xff, addr + j+0);
1941 writeb(0x00, addr + j+8);