2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/errno.h>
15 #include <linux/string.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/console.h>
23 #include <linux/backlight.h>
29 #include <asm/pci-bridge.h>
37 #undef CONFIG_FB_NVIDIA_DEBUG
38 #ifdef CONFIG_FB_NVIDIA_DEBUG
39 #define NVTRACE printk
41 #define NVTRACE if (0) printk
44 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
45 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
47 #ifdef CONFIG_FB_NVIDIA_DEBUG
48 #define assert(expr) \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
51 #expr,__FILE__,__FUNCTION__,__LINE__); \
58 #define PFX "nvidiafb: "
60 /* HW cursor parameters */
63 static struct pci_device_id nvidiafb_pci_tbl[] = {
64 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
65 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0},
68 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
70 /* command line data, set in nvidiafb_setup() */
71 static int flatpanel __devinitdata = -1; /* Autodetect later */
72 static int fpdither __devinitdata = -1;
73 static int forceCRTC __devinitdata = -1;
74 static int hwcur __devinitdata = 0;
75 static int noaccel __devinitdata = 0;
76 static int noscale __devinitdata = 0;
77 static int paneltweak __devinitdata = 0;
78 static int vram __devinitdata = 0;
79 static int bpp __devinitdata = 8;
81 static int nomtrr __devinitdata = 0;
84 static char *mode_option __devinitdata = NULL;
86 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
87 .type = FB_TYPE_PACKED_PIXELS,
92 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
102 .activate = FB_ACTIVATE_NOW,
112 .vmode = FB_VMODE_NONINTERLACED
115 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
116 u16 bg, u16 fg, u32 w, u32 h)
118 u32 *data = (u32 *) data8;
124 for (i = 0; i < h; i++) {
128 for (j = 0; j < w / 2; j++) {
130 #if defined (__BIG_ENDIAN)
131 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
133 tmp |= (b & (1 << 31)) ? fg : bg;
136 tmp = (b & 1) ? fg : bg;
138 tmp |= (b & 1) ? fg << 16 : bg << 16;
141 NV_WR32(&par->CURSOR[k++], 0, tmp);
143 k += (MAX_CURS - w) / 2;
147 static void nvidia_write_clut(struct nvidia_par *par,
148 u8 regnum, u8 red, u8 green, u8 blue)
150 NVWriteDacMask(par, 0xff);
151 NVWriteDacWriteAddr(par, regnum);
152 NVWriteDacData(par, red);
153 NVWriteDacData(par, green);
154 NVWriteDacData(par, blue);
157 static void nvidia_read_clut(struct nvidia_par *par,
158 u8 regnum, u8 * red, u8 * green, u8 * blue)
160 NVWriteDacMask(par, 0xff);
161 NVWriteDacReadAddr(par, regnum);
162 *red = NVReadDacData(par);
163 *green = NVReadDacData(par);
164 *blue = NVReadDacData(par);
167 static int nvidia_panel_tweak(struct nvidia_par *par,
168 struct _riva_hw_state *state)
172 if (par->paneltweak) {
173 tweak = par->paneltweak;
175 /* begin flat panel hacks */
176 /* This is unfortunate, but some chips need this register
177 tweaked or else you get artifacts where adjacent pixels are
178 swapped. There are no hard rules for what to set here so all
179 we can do is experiment and apply hacks. */
181 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
182 /* At least one NV34 laptop needs this workaround. */
186 if((par->Chipset & 0xfff0) == 0x0310) {
189 /* end flat panel hacks */
195 static void nvidia_vga_protect(struct nvidia_par *par, int on)
201 * Turn off screen and disable sequencer.
203 tmp = NVReadSeq(par, 0x01);
205 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
206 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
209 * Reenable sequencer, then turn on screen.
212 tmp = NVReadSeq(par, 0x01);
214 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
215 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
219 static void nvidia_save_vga(struct nvidia_par *par,
220 struct _riva_hw_state *state)
225 NVLockUnlock(par, 0);
227 NVUnloadStateExt(par, state);
229 state->misc_output = NVReadMiscOut(par);
231 for (i = 0; i < NUM_CRT_REGS; i++)
232 state->crtc[i] = NVReadCrtc(par, i);
234 for (i = 0; i < NUM_ATC_REGS; i++)
235 state->attr[i] = NVReadAttr(par, i);
237 for (i = 0; i < NUM_GRC_REGS; i++)
238 state->gra[i] = NVReadGr(par, i);
240 for (i = 0; i < NUM_SEQ_REGS; i++)
241 state->seq[i] = NVReadSeq(par, i);
247 static void nvidia_write_regs(struct nvidia_par *par,
248 struct _riva_hw_state *state)
254 NVLoadStateExt(par, state);
256 NVWriteMiscOut(par, state->misc_output);
258 for (i = 1; i < NUM_SEQ_REGS; i++) {
260 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
262 NVWriteSeq(par, i, state->seq[i]);
265 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
266 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
268 for (i = 0; i < NUM_CRT_REGS; i++) {
275 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
277 NVWriteCrtc(par, i, state->crtc[i]);
281 for (i = 0; i < NUM_GRC_REGS; i++) {
283 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
285 NVWriteGr(par, i, state->gra[i]);
288 for (i = 0; i < NUM_ATC_REGS; i++) {
290 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
292 NVWriteAttr(par, i, state->attr[i]);
298 static int nvidia_calc_regs(struct fb_info *info)
300 struct nvidia_par *par = info->par;
301 struct _riva_hw_state *state = &par->ModeReg;
302 int i, depth = fb_get_color_depth(&info->var, &info->fix);
303 int h_display = info->var.xres / 8 - 1;
304 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
305 int h_end = (info->var.xres + info->var.right_margin +
306 info->var.hsync_len) / 8 - 1;
307 int h_total = (info->var.xres + info->var.right_margin +
308 info->var.hsync_len + info->var.left_margin) / 8 - 5;
309 int h_blank_s = h_display;
310 int h_blank_e = h_total + 4;
311 int v_display = info->var.yres - 1;
312 int v_start = info->var.yres + info->var.lower_margin - 1;
313 int v_end = (info->var.yres + info->var.lower_margin +
314 info->var.vsync_len) - 1;
315 int v_total = (info->var.yres + info->var.lower_margin +
316 info->var.vsync_len + info->var.upper_margin) - 2;
317 int v_blank_s = v_display;
318 int v_blank_e = v_total + 1;
321 * Set all CRTC values.
324 if (info->var.vmode & FB_VMODE_INTERLACED)
327 if (par->FlatPanel == 1) {
328 v_start = v_total - 3;
331 h_start = h_total - 5;
333 h_blank_e = h_total + 4;
336 state->crtc[0x0] = Set8Bits(h_total);
337 state->crtc[0x1] = Set8Bits(h_display);
338 state->crtc[0x2] = Set8Bits(h_blank_s);
339 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
341 state->crtc[0x4] = Set8Bits(h_start);
342 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
343 | SetBitField(h_end, 4: 0, 4:0);
344 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
345 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
346 | SetBitField(v_display, 8: 8, 1:1)
347 | SetBitField(v_start, 8: 8, 2:2)
348 | SetBitField(v_blank_s, 8: 8, 3:3)
350 | SetBitField(v_total, 9: 9, 5:5)
351 | SetBitField(v_display, 9: 9, 6:6)
352 | SetBitField(v_start, 9: 9, 7:7);
353 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
355 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
356 state->crtc[0x10] = Set8Bits(v_start);
357 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
358 state->crtc[0x12] = Set8Bits(v_display);
359 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
360 (info->var.bits_per_pixel / 8));
361 state->crtc[0x15] = Set8Bits(v_blank_s);
362 state->crtc[0x16] = Set8Bits(v_blank_e);
364 state->attr[0x10] = 0x01;
367 state->attr[0x11] = 0x00;
369 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
370 | SetBitField(v_blank_s, 10: 10, 3:3)
371 | SetBitField(v_start, 10: 10, 2:2)
372 | SetBitField(v_display, 10: 10, 1:1)
373 | SetBitField(v_total, 10: 10, 0:0);
375 state->horiz = SetBitField(h_total, 8: 8, 0:0)
376 | SetBitField(h_display, 8: 8, 1:1)
377 | SetBitField(h_blank_s, 8: 8, 2:2)
378 | SetBitField(h_start, 8: 8, 3:3);
380 state->extra = SetBitField(v_total, 11: 11, 0:0)
381 | SetBitField(v_display, 11: 11, 2:2)
382 | SetBitField(v_start, 11: 11, 4:4)
383 | SetBitField(v_blank_s, 11: 11, 6:6);
385 if (info->var.vmode & FB_VMODE_INTERLACED) {
386 h_total = (h_total >> 1) & ~1;
387 state->interlace = Set8Bits(h_total);
388 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
390 state->interlace = 0xff; /* interlace off */
394 * Calculate the extended registers.
402 if (par->Architecture >= NV_ARCH_10)
403 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
406 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
407 state->misc_output &= ~0x40;
409 state->misc_output |= 0x40;
410 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
411 state->misc_output &= ~0x80;
413 state->misc_output |= 0x80;
415 NVCalcStateExt(par, state, i, info->var.xres_virtual,
416 info->var.xres, info->var.yres_virtual,
417 1000000000 / info->var.pixclock, info->var.vmode);
419 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
420 if (par->FlatPanel == 1) {
421 state->pixel |= (1 << 7);
423 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
424 || (par->fpHeight <= info->var.yres)) {
425 state->scale |= (1 << 8);
428 if (!par->crtcSync_read) {
429 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
430 par->crtcSync_read = 1;
433 par->PanelTweak = nvidia_panel_tweak(par, state);
436 state->vpll = state->pll;
437 state->vpll2 = state->pll;
438 state->vpllB = state->pllB;
439 state->vpll2B = state->pllB;
441 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
442 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
444 if (par->CRTCnumber) {
445 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
446 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
447 state->crtcOwner = 3;
448 state->pllsel |= 0x20000800;
449 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
450 if (par->twoStagePLL)
451 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
452 } else if (par->twoHeads) {
453 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
454 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
455 state->crtcOwner = 0;
456 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
457 if (par->twoStagePLL)
458 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
461 state->cursorConfig = 0x00000100;
463 if (info->var.vmode & FB_VMODE_DOUBLE)
464 state->cursorConfig |= (1 << 4);
466 if (par->alphaCursor) {
467 if ((par->Chipset & 0x0ff0) != 0x0110)
468 state->cursorConfig |= 0x04011000;
470 state->cursorConfig |= 0x14011000;
471 state->general |= (1 << 29);
473 state->cursorConfig |= 0x02000000;
476 if ((par->Chipset & 0x0ff0) == 0x0110) {
477 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
480 state->dither |= 0x00010000;
482 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
490 state->displayV = info->var.xres;
495 static void nvidia_init_vga(struct fb_info *info)
497 struct nvidia_par *par = info->par;
498 struct _riva_hw_state *state = &par->ModeReg;
501 for (i = 0; i < 0x10; i++)
503 state->attr[0x10] = 0x41;
504 state->attr[0x11] = 0xff;
505 state->attr[0x12] = 0x0f;
506 state->attr[0x13] = 0x00;
507 state->attr[0x14] = 0x00;
509 memset(state->crtc, 0x00, NUM_CRT_REGS);
510 state->crtc[0x0a] = 0x20;
511 state->crtc[0x17] = 0xe3;
512 state->crtc[0x18] = 0xff;
513 state->crtc[0x28] = 0x40;
515 memset(state->gra, 0x00, NUM_GRC_REGS);
516 state->gra[0x05] = 0x40;
517 state->gra[0x06] = 0x05;
518 state->gra[0x07] = 0x0f;
519 state->gra[0x08] = 0xff;
521 state->seq[0x00] = 0x03;
522 state->seq[0x01] = 0x01;
523 state->seq[0x02] = 0x0f;
524 state->seq[0x03] = 0x00;
525 state->seq[0x04] = 0x0e;
527 state->misc_output = 0xeb;
530 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
532 struct nvidia_par *par = info->par;
533 u8 data[MAX_CURS * MAX_CURS / 8];
534 int i, set = cursor->set;
537 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
540 NVShowHideCursor(par, 0);
542 if (par->cursor_reset) {
544 par->cursor_reset = 0;
547 if (set & FB_CUR_SETSIZE)
548 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
550 if (set & FB_CUR_SETPOS) {
553 yy = cursor->image.dy - info->var.yoffset;
554 xx = cursor->image.dx - info->var.xoffset;
558 NV_WR32(par->PRAMDAC, 0x0000300, temp);
561 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
562 u32 bg_idx = cursor->image.bg_color;
563 u32 fg_idx = cursor->image.fg_color;
564 u32 s_pitch = (cursor->image.width + 7) >> 3;
565 u32 d_pitch = MAX_CURS / 8;
566 u8 *dat = (u8 *) cursor->image.data;
567 u8 *msk = (u8 *) cursor->mask;
570 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
573 switch (cursor->rop) {
575 for (i = 0; i < s_pitch * cursor->image.height; i++)
576 src[i] = dat[i] ^ msk[i];
580 for (i = 0; i < s_pitch * cursor->image.height; i++)
581 src[i] = dat[i] & msk[i];
585 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
586 cursor->image.height);
588 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
589 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
590 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
592 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
593 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
594 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
596 NVLockUnlock(par, 0);
598 nvidiafb_load_cursor_image(par, data, bg, fg,
600 cursor->image.height);
606 NVShowHideCursor(par, 1);
611 static int nvidiafb_set_par(struct fb_info *info)
613 struct nvidia_par *par = info->par;
617 NVLockUnlock(par, 1);
618 if (!par->FlatPanel || !par->twoHeads)
621 if (par->FPDither < 0) {
622 if ((par->Chipset & 0x0ff0) == 0x0110)
623 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528)
626 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1);
627 printk(KERN_INFO PFX "Flat panel dithering %s\n",
628 par->FPDither ? "enabled" : "disabled");
631 info->fix.visual = (info->var.bits_per_pixel == 8) ?
632 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
634 nvidia_init_vga(info);
635 nvidia_calc_regs(info);
637 NVLockUnlock(par, 0);
639 VGA_WR08(par->PCIO, 0x03D4, 0x44);
640 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
641 NVLockUnlock(par, 0);
644 nvidia_vga_protect(par, 1);
646 nvidia_write_regs(par, &par->ModeReg);
647 NVSetStartAddress(par, 0);
649 #if defined (__BIG_ENDIAN)
650 /* turn on LFB swapping */
654 VGA_WR08(par->PCIO, 0x3d4, 0x46);
655 tmp = VGA_RD08(par->PCIO, 0x3d5);
657 VGA_WR08(par->PCIO, 0x3d5, tmp);
661 info->fix.line_length = (info->var.xres_virtual *
662 info->var.bits_per_pixel) >> 3;
663 if (info->var.accel_flags) {
664 info->fbops->fb_imageblit = nvidiafb_imageblit;
665 info->fbops->fb_fillrect = nvidiafb_fillrect;
666 info->fbops->fb_copyarea = nvidiafb_copyarea;
667 info->fbops->fb_sync = nvidiafb_sync;
668 info->pixmap.scan_align = 4;
669 info->flags &= ~FBINFO_HWACCEL_DISABLED;
670 NVResetGraphics(info);
672 info->fbops->fb_imageblit = cfb_imageblit;
673 info->fbops->fb_fillrect = cfb_fillrect;
674 info->fbops->fb_copyarea = cfb_copyarea;
675 info->fbops->fb_sync = NULL;
676 info->pixmap.scan_align = 1;
677 info->flags |= FBINFO_HWACCEL_DISABLED;
680 par->cursor_reset = 1;
682 nvidia_vga_protect(par, 0);
688 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
689 unsigned blue, unsigned transp,
690 struct fb_info *info)
692 struct nvidia_par *par = info->par;
696 if (regno >= (1 << info->var.green.length))
699 if (info->var.grayscale) {
700 /* gray = 0.30*R + 0.59*G + 0.11*B */
701 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
704 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
705 ((u32 *) info->pseudo_palette)[regno] =
706 (regno << info->var.red.offset) |
707 (regno << info->var.green.offset) |
708 (regno << info->var.blue.offset);
711 switch (info->var.bits_per_pixel) {
713 /* "transparent" stuff is completely ignored. */
714 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
717 if (info->var.green.length == 5) {
718 for (i = 0; i < 8; i++) {
719 nvidia_write_clut(par, regno * 8 + i, red >> 8,
720 green >> 8, blue >> 8);
726 for (i = 0; i < 8; i++) {
727 nvidia_write_clut(par, regno * 8 + i,
728 red >> 8, green >> 8,
733 nvidia_read_clut(par, regno * 4, &r, &g, &b);
735 for (i = 0; i < 4; i++)
736 nvidia_write_clut(par, regno * 4 + i, r,
741 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
752 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
753 struct fb_info *info)
755 struct nvidia_par *par = info->par;
756 int memlen, vramlen, mode_valid = 0;
761 var->transp.offset = 0;
762 var->transp.length = 0;
766 if (var->bits_per_pixel <= 8)
767 var->bits_per_pixel = 8;
768 else if (var->bits_per_pixel <= 16)
769 var->bits_per_pixel = 16;
771 var->bits_per_pixel = 32;
773 switch (var->bits_per_pixel) {
777 var->green.offset = 0;
778 var->green.length = 8;
779 var->blue.offset = 0;
780 var->blue.length = 8;
781 var->transp.offset = 0;
782 var->transp.length = 0;
785 var->green.length = (var->green.length < 6) ? 5 : 6;
787 var->blue.length = 5;
788 var->transp.length = 6 - var->green.length;
789 var->blue.offset = 0;
790 var->green.offset = 5;
791 var->red.offset = 5 + var->green.length;
792 var->transp.offset = (5 + var->red.offset) & 15;
794 case 32: /* RGBA 8888 */
795 var->red.offset = 16;
797 var->green.offset = 8;
798 var->green.length = 8;
799 var->blue.offset = 0;
800 var->blue.length = 8;
801 var->transp.length = 8;
802 var->transp.offset = 24;
806 var->red.msb_right = 0;
807 var->green.msb_right = 0;
808 var->blue.msb_right = 0;
809 var->transp.msb_right = 0;
811 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
812 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
815 /* calculate modeline if supported by monitor */
816 if (!mode_valid && info->monspecs.gtf) {
817 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
822 struct fb_videomode *mode;
824 mode = fb_find_best_mode(var, &info->modelist);
826 fb_videomode_to_var(var, mode);
831 if (!mode_valid && info->monspecs.modedb_len)
834 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
835 par->fpHeight < var->yres))
838 if (var->yres_virtual < var->yres)
839 var->yres_virtual = var->yres;
841 if (var->xres_virtual < var->xres)
842 var->xres_virtual = var->xres;
844 var->xres_virtual = (var->xres_virtual + 63) & ~63;
846 vramlen = info->screen_size;
847 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
848 memlen = pitch * var->yres_virtual;
850 if (memlen > vramlen) {
851 var->yres_virtual = vramlen / pitch;
853 if (var->yres_virtual < var->yres) {
854 var->yres_virtual = var->yres;
855 var->xres_virtual = vramlen / var->yres_virtual;
856 var->xres_virtual /= var->bits_per_pixel / 8;
857 var->xres_virtual &= ~63;
858 pitch = (var->xres_virtual *
859 var->bits_per_pixel + 7) / 8;
860 memlen = pitch * var->yres;
862 if (var->xres_virtual < var->xres) {
863 printk("nvidiafb: required video memory, "
864 "%d bytes, for %dx%d-%d (virtual) "
866 memlen, var->xres_virtual,
867 var->yres_virtual, var->bits_per_pixel);
873 if (var->accel_flags) {
874 if (var->yres_virtual > 0x7fff)
875 var->yres_virtual = 0x7fff;
876 if (var->xres_virtual > 0x7fff)
877 var->xres_virtual = 0x7fff;
880 var->xres_virtual &= ~63;
887 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
888 struct fb_info *info)
890 struct nvidia_par *par = info->par;
893 total = var->yoffset * info->fix.line_length + var->xoffset;
895 NVSetStartAddress(par, total);
900 static int nvidiafb_blank(int blank, struct fb_info *info)
902 struct nvidia_par *par = info->par;
903 unsigned char tmp, vesa;
905 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
906 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
914 case FB_BLANK_UNBLANK:
915 case FB_BLANK_NORMAL:
917 case FB_BLANK_VSYNC_SUSPEND:
920 case FB_BLANK_HSYNC_SUSPEND:
923 case FB_BLANK_POWERDOWN:
928 NVWriteSeq(par, 0x01, tmp);
929 NVWriteCrtc(par, 0x1a, vesa);
931 nvidia_bl_set_power(info, blank);
938 static struct fb_ops nvidia_fb_ops = {
939 .owner = THIS_MODULE,
940 .fb_check_var = nvidiafb_check_var,
941 .fb_set_par = nvidiafb_set_par,
942 .fb_setcolreg = nvidiafb_setcolreg,
943 .fb_pan_display = nvidiafb_pan_display,
944 .fb_blank = nvidiafb_blank,
945 .fb_fillrect = nvidiafb_fillrect,
946 .fb_copyarea = nvidiafb_copyarea,
947 .fb_imageblit = nvidiafb_imageblit,
948 .fb_cursor = nvidiafb_cursor,
949 .fb_sync = nvidiafb_sync,
953 static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t mesg)
955 struct fb_info *info = pci_get_drvdata(dev);
956 struct nvidia_par *par = info->par;
958 if (mesg.event == PM_EVENT_PRETHAW)
959 mesg.event = PM_EVENT_FREEZE;
960 acquire_console_sem();
961 par->pm_state = mesg.event;
963 if (mesg.event == PM_EVENT_SUSPEND) {
964 fb_set_suspend(info, 1);
965 nvidiafb_blank(FB_BLANK_POWERDOWN, info);
966 nvidia_write_regs(par, &par->SavedReg);
968 pci_disable_device(dev);
969 pci_set_power_state(dev, pci_choose_state(dev, mesg));
971 dev->dev.power.power_state = mesg;
973 release_console_sem();
977 static int nvidiafb_resume(struct pci_dev *dev)
979 struct fb_info *info = pci_get_drvdata(dev);
980 struct nvidia_par *par = info->par;
982 acquire_console_sem();
983 pci_set_power_state(dev, PCI_D0);
985 if (par->pm_state != PM_EVENT_FREEZE) {
986 pci_restore_state(dev);
988 if (pci_enable_device(dev))
994 par->pm_state = PM_EVENT_ON;
995 nvidiafb_set_par(info);
996 fb_set_suspend (info, 0);
997 nvidiafb_blank(FB_BLANK_UNBLANK, info);
1000 release_console_sem();
1004 #define nvidiafb_suspend NULL
1005 #define nvidiafb_resume NULL
1008 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1010 struct fb_monspecs *specs = &info->monspecs;
1011 struct fb_videomode modedb;
1012 struct nvidia_par *par = info->par;
1016 info->flags = FBINFO_DEFAULT
1017 | FBINFO_HWACCEL_IMAGEBLIT
1018 | FBINFO_HWACCEL_FILLRECT
1019 | FBINFO_HWACCEL_COPYAREA
1020 | FBINFO_HWACCEL_YPAN;
1022 fb_videomode_to_modelist(info->monspecs.modedb,
1023 info->monspecs.modedb_len, &info->modelist);
1024 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1038 if (specs->modedb != NULL) {
1039 struct fb_videomode *modedb;
1041 modedb = fb_find_best_display(specs, &info->modelist);
1042 fb_videomode_to_var(&nvidiafb_default_var, modedb);
1043 nvidiafb_default_var.bits_per_pixel = bpp;
1044 } else if (par->fpWidth && par->fpHeight) {
1048 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1049 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1050 specs->modedb_len, &modedb, bpp);
1054 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1055 specs->modedb, specs->modedb_len, &modedb, bpp);
1057 info->var = nvidiafb_default_var;
1058 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1059 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1060 info->pseudo_palette = par->pseudo_palette;
1061 fb_alloc_cmap(&info->cmap, 256, 0);
1062 fb_destroy_modedb(info->monspecs.modedb);
1063 info->monspecs.modedb = NULL;
1065 /* maximize virtual vertical length */
1066 lpitch = info->var.xres_virtual *
1067 ((info->var.bits_per_pixel + 7) >> 3);
1068 info->var.yres_virtual = info->screen_size / lpitch;
1070 info->pixmap.scan_align = 4;
1071 info->pixmap.buf_align = 4;
1072 info->pixmap.access_align = 32;
1073 info->pixmap.size = 8 * 1024;
1074 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1077 info->fbops->fb_cursor = NULL;
1079 info->var.accel_flags = (!noaccel);
1081 switch (par->Architecture) {
1083 info->fix.accel = FB_ACCEL_NV4;
1086 info->fix.accel = FB_ACCEL_NV_10;
1089 info->fix.accel = FB_ACCEL_NV_20;
1092 info->fix.accel = FB_ACCEL_NV_30;
1095 info->fix.accel = FB_ACCEL_NV_40;
1101 return nvidiafb_check_var(&info->var, info);
1104 static u32 __devinit nvidia_get_chipset(struct fb_info *info)
1106 struct nvidia_par *par = info->par;
1107 u32 id = (par->pci_dev->vendor << 16) | par->pci_dev->device;
1109 printk(KERN_INFO PFX "Device ID: %x \n", id);
1111 if ((id & 0xfff0) == 0x00f0) {
1113 id = NV_RD32(par->REGS, 0x1800);
1115 if ((id & 0x0000ffff) == 0x000010DE)
1116 id = 0x10DE0000 | (id >> 16);
1117 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */
1118 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) |
1119 ((id >> 8) & 0x000000ff);
1120 printk(KERN_INFO PFX "Subsystem ID: %x \n", id);
1126 static u32 __devinit nvidia_get_arch(struct fb_info *info)
1128 struct nvidia_par *par = info->par;
1131 switch (par->Chipset & 0x0ff0) {
1132 case 0x0100: /* GeForce 256 */
1133 case 0x0110: /* GeForce2 MX */
1134 case 0x0150: /* GeForce2 */
1135 case 0x0170: /* GeForce4 MX */
1136 case 0x0180: /* GeForce4 MX (8x AGP) */
1137 case 0x01A0: /* nForce */
1138 case 0x01F0: /* nForce2 */
1141 case 0x0200: /* GeForce3 */
1142 case 0x0250: /* GeForce4 Ti */
1143 case 0x0280: /* GeForce4 Ti (8x AGP) */
1146 case 0x0300: /* GeForceFX 5800 */
1147 case 0x0310: /* GeForceFX 5600 */
1148 case 0x0320: /* GeForceFX 5200 */
1149 case 0x0330: /* GeForceFX 5900 */
1150 case 0x0340: /* GeForceFX 5700 */
1169 case 0x0020: /* TNT, TNT2 */
1172 default: /* unknown architecture */
1179 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1180 const struct pci_device_id *ent)
1182 struct nvidia_par *par;
1183 struct fb_info *info;
1190 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1198 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1200 if (info->pixmap.addr == NULL)
1203 memset(info->pixmap.addr, 0, 8 * 1024);
1205 if (pci_enable_device(pd)) {
1206 printk(KERN_ERR PFX "cannot enable PCI device\n");
1207 goto err_out_enable;
1210 if (pci_request_regions(pd, "nvidiafb")) {
1211 printk(KERN_ERR PFX "cannot request PCI regions\n");
1212 goto err_out_enable;
1215 par->FlatPanel = flatpanel;
1217 printk(KERN_INFO PFX "flatpanel support enabled\n");
1218 par->FPDither = fpdither;
1220 par->CRTCnumber = forceCRTC;
1221 par->FpScale = (!noscale);
1222 par->paneltweak = paneltweak;
1224 /* enable IO and mem if not already done */
1225 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1226 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1227 pci_write_config_word(pd, PCI_COMMAND, cmd);
1229 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1230 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1231 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1233 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1236 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1237 goto err_out_free_base0;
1240 par->Chipset = nvidia_get_chipset(info);
1241 par->Architecture = nvidia_get_arch(info);
1243 if (par->Architecture == 0) {
1244 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1248 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1250 if (NVCommonSetup(info))
1253 par->FbAddress = nvidiafb_fix.smem_start;
1254 par->FbMapSize = par->RamAmountKBytes * 1024;
1255 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1256 par->FbMapSize = vram * 1024 * 1024;
1258 /* Limit amount of vram to 64 MB */
1259 if (par->FbMapSize > 64 * 1024 * 1024)
1260 par->FbMapSize = 64 * 1024 * 1024;
1262 if(par->Architecture >= NV_ARCH_40)
1263 par->FbUsableSize = par->FbMapSize - (560 * 1024);
1265 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1266 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1268 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1269 par->CursorStart = par->FbUsableSize + (32 * 1024);
1271 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1272 info->screen_size = par->FbUsableSize;
1273 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1275 if (!info->screen_base) {
1276 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1277 goto err_out_free_base1;
1280 par->FbStart = info->screen_base;
1284 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1285 par->RamAmountKBytes * 1024,
1286 MTRR_TYPE_WRCOMB, 1);
1287 if (par->mtrr.vram < 0) {
1288 printk(KERN_ERR PFX "unable to setup MTRR\n");
1290 par->mtrr.vram_valid = 1;
1291 /* let there be speed */
1292 printk(KERN_INFO PFX "MTRR set to ON\n");
1295 #endif /* CONFIG_MTRR */
1297 info->fbops = &nvidia_fb_ops;
1298 info->fix = nvidiafb_fix;
1300 if (nvidia_set_fbinfo(info) < 0) {
1301 printk(KERN_ERR PFX "error setting initial video mode\n");
1302 goto err_out_iounmap_fb;
1305 nvidia_save_vga(par, &par->SavedReg);
1307 pci_set_drvdata(pd, info);
1308 nvidia_bl_init(par);
1309 if (register_framebuffer(info) < 0) {
1310 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1311 goto err_out_iounmap_fb;
1315 printk(KERN_INFO PFX
1316 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1318 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1324 iounmap(info->screen_base);
1326 fb_destroy_modedb(info->monspecs.modedb);
1327 nvidia_delete_i2c_busses(par);
1331 pci_release_regions(pd);
1333 kfree(info->pixmap.addr);
1335 framebuffer_release(info);
1340 static void __exit nvidiafb_remove(struct pci_dev *pd)
1342 struct fb_info *info = pci_get_drvdata(pd);
1343 struct nvidia_par *par = info->par;
1347 nvidia_bl_exit(par);
1349 unregister_framebuffer(info);
1351 if (par->mtrr.vram_valid)
1352 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1353 info->fix.smem_len);
1354 #endif /* CONFIG_MTRR */
1356 iounmap(info->screen_base);
1357 fb_destroy_modedb(info->monspecs.modedb);
1358 nvidia_delete_i2c_busses(par);
1360 pci_release_regions(pd);
1361 kfree(info->pixmap.addr);
1362 framebuffer_release(info);
1363 pci_set_drvdata(pd, NULL);
1367 /* ------------------------------------------------------------------------- *
1371 * ------------------------------------------------------------------------- */
1374 static int __devinit nvidiafb_setup(char *options)
1379 if (!options || !*options)
1382 while ((this_opt = strsep(&options, ",")) != NULL) {
1383 if (!strncmp(this_opt, "forceCRTC", 9)) {
1389 forceCRTC = *p - '0';
1390 if (forceCRTC < 0 || forceCRTC > 1)
1392 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1394 } else if (!strncmp(this_opt, "hwcur", 5)) {
1396 } else if (!strncmp(this_opt, "noaccel", 6)) {
1398 } else if (!strncmp(this_opt, "noscale", 7)) {
1400 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1401 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1402 } else if (!strncmp(this_opt, "vram:", 5)) {
1403 vram = simple_strtoul(this_opt+5, NULL, 0);
1405 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1408 } else if (!strncmp(this_opt, "fpdither:", 9)) {
1409 fpdither = simple_strtol(this_opt+9, NULL, 0);
1410 } else if (!strncmp(this_opt, "bpp:", 4)) {
1411 bpp = simple_strtoul(this_opt+4, NULL, 0);
1413 mode_option = this_opt;
1418 #endif /* !MODULE */
1420 static struct pci_driver nvidiafb_driver = {
1422 .id_table = nvidiafb_pci_tbl,
1423 .probe = nvidiafb_probe,
1424 .suspend = nvidiafb_suspend,
1425 .resume = nvidiafb_resume,
1426 .remove = __exit_p(nvidiafb_remove),
1429 /* ------------------------------------------------------------------------- *
1433 * ------------------------------------------------------------------------- */
1435 static int __devinit nvidiafb_init(void)
1438 char *option = NULL;
1440 if (fb_get_options("nvidiafb", &option))
1442 nvidiafb_setup(option);
1444 return pci_register_driver(&nvidiafb_driver);
1447 module_init(nvidiafb_init);
1450 static void __exit nvidiafb_exit(void)
1452 pci_unregister_driver(&nvidiafb_driver);
1455 module_exit(nvidiafb_exit);
1457 module_param(flatpanel, int, 0);
1458 MODULE_PARM_DESC(flatpanel,
1459 "Enables experimental flat panel support for some chipsets. "
1460 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1461 module_param(fpdither, int, 0);
1462 MODULE_PARM_DESC(fpdither,
1463 "Enables dithering of flat panel for 6 bits panels. "
1464 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)");
1465 module_param(hwcur, int, 0);
1466 MODULE_PARM_DESC(hwcur,
1467 "Enables hardware cursor implementation. (0 or 1=enabled) "
1469 module_param(noaccel, int, 0);
1470 MODULE_PARM_DESC(noaccel,
1471 "Disables hardware acceleration. (0 or 1=disable) "
1473 module_param(noscale, int, 0);
1474 MODULE_PARM_DESC(noscale,
1475 "Disables screen scaleing. (0 or 1=disable) "
1476 "(default=0, do scaling)");
1477 module_param(paneltweak, int, 0);
1478 MODULE_PARM_DESC(paneltweak,
1479 "Tweak display settings for flatpanels. "
1480 "(default=0, no tweaks)");
1481 module_param(forceCRTC, int, 0);
1482 MODULE_PARM_DESC(forceCRTC,
1483 "Forces usage of a particular CRTC in case autodetection "
1484 "fails. (0 or 1) (default=autodetect)");
1485 module_param(vram, int, 0);
1486 MODULE_PARM_DESC(vram,
1487 "amount of framebuffer memory to remap in MiB"
1488 "(default=0 - remap entire memory)");
1489 module_param(mode_option, charp, 0);
1490 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
1491 module_param(bpp, int, 0);
1492 MODULE_PARM_DESC(bpp, "pixel width in bits"
1495 module_param(nomtrr, bool, 0);
1496 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1500 MODULE_AUTHOR("Antonino Daplas");
1501 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1502 MODULE_LICENSE("GPL");