2 * Permedia2 framebuffer driver.
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
45 #include <video/permedia2.h>
46 #include <video/cvisionppc.h>
48 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
49 #error "The endianness of the target host has not been defined."
52 #if !defined(CONFIG_PCI)
53 #error "Only generic PCI cards supported."
56 #undef PM2FB_MASTER_DEBUG
57 #ifdef PM2FB_MASTER_DEBUG
58 #define DPRINTK(a, b...) \
59 printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
61 #define DPRINTK(a, b...)
64 #define PM2_PIXMAP_SIZE (1600 * 4)
69 static char *mode __devinitdata;
72 * The XFree GLINT driver will (I think to implement hardware cursor
73 * support on TVP4010 and similar where there is no RAMDAC - see
74 * comment in set_video) always request +ve sync regardless of what
75 * the mode requires. This screws me because I have a Sun
76 * fixed-frequency monitor which absolutely has to have -ve sync. So
77 * these flags allow the user to specify that requests for +ve sync
78 * should be silently turned in -ve sync.
82 static int noaccel __devinitdata;
85 static int nomtrr __devinitdata;
89 * The hardware state of the graphics card that isn't part of the
94 pm2type_t type; /* Board type */
95 unsigned char __iomem *v_regs;/* virtual address of p_regs */
96 u32 memclock; /* memclock */
97 u32 video; /* video flags before blanking */
98 u32 mem_config; /* MemConfig reg at probe */
99 u32 mem_control; /* MemControl reg at probe */
100 u32 boot_address; /* BootAddress reg at probe */
106 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
107 * if we don't use modedb.
109 static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
111 .type = FB_TYPE_PACKED_PIXELS,
112 .visual = FB_VISUAL_PSEUDOCOLOR,
116 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
120 * Default video mode. In case the modedb doesn't work.
122 static struct fb_var_screeninfo pm2fb_var __devinitdata = {
123 /* "640x480, 8 bpp @ 60 Hz */
132 .activate = FB_ACTIVATE_NOW,
143 .vmode = FB_VMODE_NONINTERLACED
150 static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)
152 return fb_readl(p->v_regs + off);
155 static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
157 fb_writel(v, p->v_regs + off);
160 static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)
162 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
164 return pm2_RD(p, PM2R_RD_INDEXED_DATA);
167 static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)
169 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
171 return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
174 static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
176 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
178 pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
182 static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
184 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
186 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
190 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
191 #define WAIT_FIFO(p, a)
193 static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)
195 while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a);
201 * partial products for the supported horizontal resolutions.
203 #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
204 static const struct {
208 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
209 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
210 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
211 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
212 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
213 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
214 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
215 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
216 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
217 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
218 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
219 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
220 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
221 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
222 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
223 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
226 static u32 partprod(u32 xres)
230 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
232 if (pp_table[i].width == 0)
233 DPRINTK("invalid width %u\n", xres);
234 return pp_table[i].pp;
237 static u32 to3264(u32 timing, int bpp, int is64)
254 static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
265 for (n = 2; n < 15; n++) {
266 for (m = 2; m; m++) {
267 f = PM2_REFERENCE_CLOCK * m / n;
268 if (f >= 150000 && f <= 300000) {
269 for (p = 0; p < 5; p++, f >>= 1) {
270 curr = (clk > f) ? clk - f : f - clk;
283 static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
293 for (m = 1; m < 128; m++) {
294 for (n = 2 * m + 1; n; n++) {
295 for (p = 0; p < 2; p++) {
296 f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
297 if (clk > f - delta && clk < f + delta) {
298 delta = (clk > f) ? clk - f : f - clk;
308 static void clear_palette(struct pm2fb_par *p)
313 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
317 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
318 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
319 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
323 static void reset_card(struct pm2fb_par *p)
325 if (p->type == PM2_TYPE_PERMEDIA2V)
326 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
327 pm2_WR(p, PM2R_RESET_STATUS, 0);
329 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
332 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
333 DPRINTK("FIFO disconnect enabled\n");
334 pm2_WR(p, PM2R_FIFO_DISCON, 1);
338 /* Restore stashed memory config information from probe */
340 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
341 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
343 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
346 static void reset_config(struct pm2fb_par *p)
349 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
350 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
351 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
352 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
353 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
354 pm2_WR(p, PM2R_APERTURE_ONE, 0);
355 pm2_WR(p, PM2R_APERTURE_TWO, 0);
356 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
357 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
358 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
359 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
360 pm2_WR(p, PM2R_LB_READ_MODE, 0);
361 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
362 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
363 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
364 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
365 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
366 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
367 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
368 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
369 pm2_WR(p, PM2R_DITHER_MODE, 0);
370 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
371 pm2_WR(p, PM2R_DEPTH_MODE, 0);
372 pm2_WR(p, PM2R_STENCIL_MODE, 0);
373 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
374 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
375 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
376 pm2_WR(p, PM2R_YUV_MODE, 0);
377 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
378 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
379 pm2_WR(p, PM2R_FOG_MODE, 0);
380 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
381 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
382 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
383 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
384 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
385 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
387 case PM2_TYPE_PERMEDIA2:
388 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
389 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
390 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
391 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
392 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
393 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
394 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
395 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
397 case PM2_TYPE_PERMEDIA2V:
398 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
403 static void set_aperture(struct pm2fb_par *p, u32 depth)
406 * The hardware is little-endian. When used in big-endian
407 * hosts, the on-chip aperture settings are used where
408 * possible to translate from host to card byte order.
411 #ifdef __LITTLE_ENDIAN
412 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
415 case 24: /* RGB->BGR */
417 * We can't use the aperture to translate host to
418 * card byte order here, so we switch to BGR mode
419 * in pm2fb_set_par().
422 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
424 case 16: /* HL->LH */
425 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
427 case 32: /* RGBA->ABGR */
428 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
433 /* We don't use aperture two, so this may be superflous */
434 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
437 static void set_color(struct pm2fb_par *p, unsigned char regno,
438 unsigned char r, unsigned char g, unsigned char b)
441 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
443 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
445 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
447 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
450 static void set_memclock(struct pm2fb_par *par, u32 clk)
453 unsigned char m, n, p;
456 case PM2_TYPE_PERMEDIA2V:
457 pm2v_mnp(clk/2, &m, &n, &p);
459 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
460 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
461 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
462 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
463 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
464 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
466 for (i = 256; i; i--)
467 if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
469 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
471 case PM2_TYPE_PERMEDIA2:
472 pm2_mnp(clk, &m, &n, &p);
474 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
475 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
476 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
477 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
478 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
480 for (i = 256; i; i--)
481 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
487 static void set_pixclock(struct pm2fb_par *par, u32 clk)
490 unsigned char m, n, p;
493 case PM2_TYPE_PERMEDIA2:
494 pm2_mnp(clk, &m, &n, &p);
496 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
497 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
498 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
499 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
500 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
502 for (i = 256; i; i--)
503 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
506 case PM2_TYPE_PERMEDIA2V:
507 pm2v_mnp(clk/2, &m, &n, &p);
509 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
510 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
511 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
512 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
513 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
518 static void set_video(struct pm2fb_par *p, u32 video)
523 DPRINTK("video = 0x%x\n", video);
526 * The hardware cursor needs +vsync to recognise vert retrace.
527 * We may not be using the hardware cursor, but the X Glint
528 * driver may well. So always set +hsync/+vsync and then set
529 * the RAMDAC to invert the sync if necessary.
531 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
532 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
535 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
538 case PM2_TYPE_PERMEDIA2:
539 tmp = PM2F_RD_PALETTE_WIDTH_8;
540 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
541 tmp |= 4; /* invert hsync */
542 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
543 tmp |= 8; /* invert vsync */
544 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
546 case PM2_TYPE_PERMEDIA2V:
548 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
549 tmp |= 1; /* invert hsync */
550 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
551 tmp |= 4; /* invert vsync */
552 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
558 * pm2fb_check_var - Optional function. Validates a var passed in.
559 * @var: frame buffer variable screen structure
560 * @info: frame buffer structure that represents a single frame buffer
562 * Checks to see if the hardware supports the state requested by
565 * Returns negative errno on error, or zero on success.
567 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
571 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
572 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
573 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
577 if (var->xres != var->xres_virtual) {
578 DPRINTK("virtual x resolution != "
579 "physical x resolution not supported\n");
583 if (var->yres > var->yres_virtual) {
584 DPRINTK("virtual y resolution < "
585 "physical y resolution not possible\n");
590 DPRINTK("xoffset not supported\n");
594 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
595 DPRINTK("interlace not supported\n");
599 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
600 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
602 if (var->xres < 320 || var->xres > 1600) {
603 DPRINTK("width not supported: %u\n", var->xres);
607 if (var->yres < 200 || var->yres > 1200) {
608 DPRINTK("height not supported: %u\n", var->yres);
612 if (lpitch * var->yres_virtual > info->fix.smem_len) {
613 DPRINTK("no memory for screen (%ux%ux%u)\n",
614 var->xres, var->yres_virtual, var->bits_per_pixel);
618 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
619 DPRINTK("pixclock too high (%ldKHz)\n",
620 PICOS2KHZ(var->pixclock));
624 var->transp.offset = 0;
625 var->transp.length = 0;
626 switch (var->bits_per_pixel) {
629 var->green.length = 8;
630 var->blue.length = 8;
633 var->red.offset = 11;
635 var->green.offset = 5;
636 var->green.length = 6;
637 var->blue.offset = 0;
638 var->blue.length = 5;
641 var->transp.offset = 24;
642 var->transp.length = 8;
643 var->red.offset = 16;
644 var->green.offset = 8;
645 var->blue.offset = 0;
647 var->green.length = 8;
648 var->blue.length = 8;
653 var->blue.offset = 16;
655 var->red.offset = 16;
656 var->blue.offset = 0;
658 var->green.offset = 8;
660 var->green.length = 8;
661 var->blue.length = 8;
667 var->accel_flags = 0; /* Can't mmap if this is on */
669 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
670 var->xres, var->yres, var->bits_per_pixel);
675 * pm2fb_set_par - Alters the hardware state.
676 * @info: frame buffer structure that represents a single frame buffer
678 * Using the fb_var_screeninfo in fb_info we set the resolution of the
679 * this particular framebuffer.
681 static int pm2fb_set_par(struct fb_info *info)
683 struct pm2fb_par *par = info->par;
685 u32 width = (info->var.xres_virtual + 7) & ~7;
686 u32 height = info->var.yres_virtual;
687 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
688 u32 hsstart, hsend, hbend, htotal;
689 u32 vsstart, vsend, vbend, vtotal;
693 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
697 u32 misc = 1; /* 8-bit DAC */
698 u32 xres = (info->var.xres + 31) & ~31;
705 set_memclock(par, par->memclock);
707 depth = (depth > 32) ? 32 : depth;
708 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
710 pixclock = PICOS2KHZ(info->var.pixclock);
711 if (pixclock > PM2_MAX_PIXCLOCK) {
712 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
716 hsstart = to3264(info->var.right_margin, depth, data64);
717 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
718 hbend = hsend + to3264(info->var.left_margin, depth, data64);
719 htotal = to3264(xres, depth, data64) + hbend - 1;
720 vsstart = (info->var.lower_margin)
721 ? info->var.lower_margin - 1
723 vsend = info->var.lower_margin + info->var.vsync_len - 1;
724 vbend = info->var.lower_margin + info->var.vsync_len +
725 info->var.upper_margin;
726 vtotal = info->var.yres + vbend - 1;
727 stride = to3264(width, depth, 1);
728 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
730 video |= PM2F_DATA_64_ENABLE;
732 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
734 DPRINTK("ignoring +hsync, using -hsync.\n");
735 video |= PM2F_HSYNC_ACT_LOW;
737 video |= PM2F_HSYNC_ACT_HIGH;
739 video |= PM2F_HSYNC_ACT_LOW;
741 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
743 DPRINTK("ignoring +vsync, using -vsync.\n");
744 video |= PM2F_VSYNC_ACT_LOW;
746 video |= PM2F_VSYNC_ACT_HIGH;
748 video |= PM2F_VSYNC_ACT_LOW;
750 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
751 DPRINTK("interlaced not supported\n");
754 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
755 video |= PM2F_LINE_DOUBLE;
756 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
757 video |= PM2F_VIDEO_ENABLE;
761 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
762 info->fix.line_length = info->var.xres * depth / 8;
763 info->cmap.len = 256;
766 * Settings calculated. Now write them out.
768 if (par->type == PM2_TYPE_PERMEDIA2V) {
770 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
773 set_aperture(par, depth);
779 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
783 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
784 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
785 txtmap = PM2F_TEXTEL_SIZE_16;
791 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
792 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
793 txtmap = PM2F_TEXTEL_SIZE_32;
799 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
800 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
801 txtmap = PM2F_TEXTEL_SIZE_24;
807 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
808 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
809 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
810 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
811 pm2_WR(par, PM2R_H_TOTAL, htotal);
812 pm2_WR(par, PM2R_HS_START, hsstart);
813 pm2_WR(par, PM2R_HS_END, hsend);
814 pm2_WR(par, PM2R_HG_END, hbend);
815 pm2_WR(par, PM2R_HB_END, hbend);
816 pm2_WR(par, PM2R_V_TOTAL, vtotal);
817 pm2_WR(par, PM2R_VS_START, vsstart);
818 pm2_WR(par, PM2R_VS_END, vsend);
819 pm2_WR(par, PM2R_VB_END, vbend);
820 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
822 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
823 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
824 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
826 pm2_WR(par, PM2R_SCREEN_BASE, base);
828 set_video(par, video);
831 case PM2_TYPE_PERMEDIA2:
832 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
833 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
834 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
836 case PM2_TYPE_PERMEDIA2V:
837 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
838 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
839 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
840 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
841 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
844 set_pixclock(par, pixclock);
845 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
846 info->var.xres, info->var.yres, info->var.bits_per_pixel);
851 * pm2fb_setcolreg - Sets a color register.
852 * @regno: boolean, 0 copy local, 1 get_user() function
853 * @red: frame buffer colormap structure
854 * @green: The green value which can be up to 16 bits wide
855 * @blue: The blue value which can be up to 16 bits wide.
856 * @transp: If supported the alpha value which can be up to 16 bits wide.
857 * @info: frame buffer info structure
859 * Set a single color register. The values supplied have a 16 bit
860 * magnitude which needs to be scaled in this function for the hardware.
861 * Pretty much a direct lift from tdfxfb.c.
863 * Returns negative errno on error, or zero on success.
865 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
866 unsigned blue, unsigned transp,
867 struct fb_info *info)
869 struct pm2fb_par *par = info->par;
871 if (regno >= info->cmap.len) /* no. of hw registers */
874 * Program hardware... do anything you want with transp
877 /* grayscale works only partially under directcolor */
878 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
879 if (info->var.grayscale)
880 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
883 * var->{color}.offset contains start of bitfield
884 * var->{color}.length contains length of bitfield
885 * {hardwarespecific} contains width of DAC
886 * cmap[X] is programmed to
887 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
888 * RAMDAC[X] is programmed to (red, green, blue)
891 * uses offset = 0 && length = DAC register width.
892 * var->{color}.offset is 0
893 * var->{color}.length contains widht of DAC
895 * DAC[X] is programmed to (red, green, blue)
897 * does not use RAMDAC (usually has 3 of them).
898 * var->{color}.offset contains start of bitfield
899 * var->{color}.length contains length of bitfield
900 * cmap is programmed to
901 * (red << red.offset) | (green << green.offset) |
902 * (blue << blue.offset) | (transp << transp.offset)
903 * RAMDAC does not exist
905 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
906 switch (info->fix.visual) {
907 case FB_VISUAL_TRUECOLOR:
908 case FB_VISUAL_PSEUDOCOLOR:
909 red = CNVT_TOHW(red, info->var.red.length);
910 green = CNVT_TOHW(green, info->var.green.length);
911 blue = CNVT_TOHW(blue, info->var.blue.length);
912 transp = CNVT_TOHW(transp, info->var.transp.length);
914 case FB_VISUAL_DIRECTCOLOR:
915 /* example here assumes 8 bit DAC. Might be different
916 * for your hardware */
917 red = CNVT_TOHW(red, 8);
918 green = CNVT_TOHW(green, 8);
919 blue = CNVT_TOHW(blue, 8);
920 /* hey, there is bug in transp handling... */
921 transp = CNVT_TOHW(transp, 8);
925 /* Truecolor has hardware independent palette */
926 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
932 v = (red << info->var.red.offset) |
933 (green << info->var.green.offset) |
934 (blue << info->var.blue.offset) |
935 (transp << info->var.transp.offset);
937 switch (info->var.bits_per_pixel) {
943 par->palette[regno] = v;
947 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
948 set_color(par, regno, red, green, blue);
954 * pm2fb_pan_display - Pans the display.
955 * @var: frame buffer variable screen structure
956 * @info: frame buffer structure that represents a single frame buffer
958 * Pan (or wrap, depending on the `vmode' field) the display using the
959 * `xoffset' and `yoffset' fields of the `var' structure.
960 * If the values don't fit, return -EINVAL.
962 * Returns negative errno on error, or zero on success.
965 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
966 struct fb_info *info)
968 struct pm2fb_par *p = info->par;
970 u32 depth = (var->bits_per_pixel + 7) & ~7;
971 u32 xres = (var->xres + 31) & ~31;
973 depth = (depth > 32) ? 32 : depth;
974 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
976 pm2_WR(p, PM2R_SCREEN_BASE, base);
981 * pm2fb_blank - Blanks the display.
982 * @blank_mode: the blank mode we want.
983 * @info: frame buffer structure that represents a single frame buffer
985 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
986 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
987 * video mode which doesn't support it. Implements VESA suspend
988 * and powerdown modes on hardware that supports disabling hsync/vsync:
989 * blank_mode == 2: suspend vsync
990 * blank_mode == 3: suspend hsync
991 * blank_mode == 4: powerdown
993 * Returns negative errno on error, or zero on success.
996 static int pm2fb_blank(int blank_mode, struct fb_info *info)
998 struct pm2fb_par *par = info->par;
999 u32 video = par->video;
1001 DPRINTK("blank_mode %d\n", blank_mode);
1003 switch (blank_mode) {
1004 case FB_BLANK_UNBLANK:
1006 video |= PM2F_VIDEO_ENABLE;
1008 case FB_BLANK_NORMAL:
1010 video &= ~PM2F_VIDEO_ENABLE;
1012 case FB_BLANK_VSYNC_SUSPEND:
1014 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
1016 case FB_BLANK_HSYNC_SUSPEND:
1018 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1020 case FB_BLANK_POWERDOWN:
1021 /* HSync: Off, VSync: Off */
1022 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1025 set_video(par, video);
1029 static int pm2fb_sync(struct fb_info *info)
1031 struct pm2fb_par *par = info->par;
1034 pm2_WR(par, PM2R_SYNC, 0);
1037 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1040 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1045 static void pm2fb_fillrect(struct fb_info *info,
1046 const struct fb_fillrect *region)
1048 struct pm2fb_par *par = info->par;
1049 struct fb_fillrect modded;
1051 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1052 ((u32 *)info->pseudo_palette)[region->color] : region->color;
1054 if (info->state != FBINFO_STATE_RUNNING)
1056 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1057 region->rop != ROP_COPY ) {
1058 cfb_fillrect(info, region);
1062 vxres = info->var.xres_virtual;
1063 vyres = info->var.yres_virtual;
1065 memcpy(&modded, region, sizeof(struct fb_fillrect));
1067 if (!modded.width || !modded.height ||
1068 modded.dx >= vxres || modded.dy >= vyres)
1071 if (modded.dx + modded.width > vxres)
1072 modded.width = vxres - modded.dx;
1073 if (modded.dy + modded.height > vyres)
1074 modded.height = vyres - modded.dy;
1076 if (info->var.bits_per_pixel == 8)
1077 color |= color << 8;
1078 if (info->var.bits_per_pixel <= 16)
1079 color |= color << 16;
1082 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
1083 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1084 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1085 if (info->var.bits_per_pixel != 24) {
1087 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1089 pm2_WR(par, PM2R_RENDER,
1090 PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
1093 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1094 pm2_WR(par, PM2R_CONSTANT_COLOR, color);
1096 pm2_WR(par, PM2R_RENDER,
1097 PM2F_RENDER_RECTANGLE |
1098 PM2F_INCREASE_X | PM2F_INCREASE_Y );
1099 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1103 static void pm2fb_copyarea(struct fb_info *info,
1104 const struct fb_copyarea *area)
1106 struct pm2fb_par *par = info->par;
1107 struct fb_copyarea modded;
1110 if (info->state != FBINFO_STATE_RUNNING)
1112 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1113 cfb_copyarea(info, area);
1117 memcpy(&modded, area, sizeof(struct fb_copyarea));
1119 vxres = info->var.xres_virtual;
1120 vyres = info->var.yres_virtual;
1122 if (!modded.width || !modded.height ||
1123 modded.sx >= vxres || modded.sy >= vyres ||
1124 modded.dx >= vxres || modded.dy >= vyres)
1127 if (modded.sx + modded.width > vxres)
1128 modded.width = vxres - modded.sx;
1129 if (modded.dx + modded.width > vxres)
1130 modded.width = vxres - modded.dx;
1131 if (modded.sy + modded.height > vyres)
1132 modded.height = vyres - modded.sy;
1133 if (modded.dy + modded.height > vyres)
1134 modded.height = vyres - modded.dy;
1137 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1138 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1139 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1140 ((modded.sy - modded.dy) & 0xfff) << 16 |
1141 ((modded.sx - modded.dx) & 0xfff));
1142 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1143 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1145 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
1146 (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) |
1147 (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0));
1150 static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
1152 struct pm2fb_par *par = info->par;
1153 u32 height = image->height;
1155 const u32 *src = (const u32 *)image->data;
1156 u32 xres = (info->var.xres + 31) & ~31;
1158 if (info->state != FBINFO_STATE_RUNNING)
1160 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
1161 cfb_imageblit(info, image);
1164 switch (info->fix.visual) {
1165 case FB_VISUAL_PSEUDOCOLOR:
1166 fgx = image->fg_color;
1167 bgx = image->bg_color;
1169 case FB_VISUAL_TRUECOLOR:
1171 fgx = par->palette[image->fg_color];
1172 bgx = par->palette[image->bg_color];
1175 if (info->var.bits_per_pixel == 8) {
1179 if (info->var.bits_per_pixel <= 16) {
1185 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
1186 pm2_WR(par, PM2R_SCISSOR_MIN_XY,
1187 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1188 pm2_WR(par, PM2R_SCISSOR_MAX_XY,
1189 (((image->dy + image->height) & 0x0fff) << 16) |
1190 ((image->dx + image->width) & 0x0fff));
1191 pm2_WR(par, PM2R_SCISSOR_MODE, 1);
1192 /* GXcopy & UNIT_ENABLE */
1193 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
1194 pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
1195 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1196 pm2_WR(par, PM2R_RECTANGLE_SIZE,
1197 ((image->height & 0x0fff) << 16) |
1198 ((image->width) & 0x0fff));
1199 if (info->var.bits_per_pixel == 24) {
1200 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1202 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
1203 pm2_WR(par, PM2R_RENDER,
1204 PM2F_RENDER_RECTANGLE |
1205 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1206 /* BitMapPackEachScanline & invert bits and byte order*/
1207 /* force background */
1208 pm2_WR(par, PM2R_RASTERIZER_MODE, (1 << 9) | 1 | (3 << 7));
1209 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
1210 pm2_WR(par, PM2R_RENDER,
1211 PM2F_RENDER_RECTANGLE |
1212 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1213 PM2F_RENDER_SYNC_ON_BIT_MASK);
1215 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1217 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
1218 pm2_WR(par, PM2R_RENDER,
1219 PM2F_RENDER_RECTANGLE |
1220 PM2F_RENDER_FASTFILL |
1221 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1222 /* invert bits and byte order*/
1223 pm2_WR(par, PM2R_RASTERIZER_MODE, 1 | (3 << 7));
1224 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
1225 pm2_WR(par, PM2R_RENDER,
1226 PM2F_RENDER_RECTANGLE |
1227 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1228 PM2F_RENDER_FASTFILL |
1229 PM2F_RENDER_SYNC_ON_BIT_MASK);
1233 int width = ((image->width + 7) >> 3)
1234 + info->pixmap.scan_align - 1;
1236 WAIT_FIFO(par, width);
1238 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
1243 pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
1244 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1245 pm2_WR(par, PM2R_SCISSOR_MODE, 0);
1248 /* ------------ Hardware Independent Functions ------------ */
1251 * Frame buffer operations
1254 static struct fb_ops pm2fb_ops = {
1255 .owner = THIS_MODULE,
1256 .fb_check_var = pm2fb_check_var,
1257 .fb_set_par = pm2fb_set_par,
1258 .fb_setcolreg = pm2fb_setcolreg,
1259 .fb_blank = pm2fb_blank,
1260 .fb_pan_display = pm2fb_pan_display,
1261 .fb_fillrect = pm2fb_fillrect,
1262 .fb_copyarea = pm2fb_copyarea,
1263 .fb_imageblit = pm2fb_imageblit,
1264 .fb_sync = pm2fb_sync,
1273 * Device initialisation
1275 * Initialise and allocate resource for PCI device.
1277 * @param pdev PCI device.
1278 * @param id PCI device ID.
1280 static int __devinit pm2fb_probe(struct pci_dev *pdev,
1281 const struct pci_device_id *id)
1283 struct pm2fb_par *default_par;
1284 struct fb_info *info;
1286 int retval = -ENXIO;
1288 err = pci_enable_device(pdev);
1290 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1294 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1297 default_par = info->par;
1299 switch (pdev->device) {
1300 case PCI_DEVICE_ID_TI_TVP4020:
1301 strcpy(pm2fb_fix.id, "TVP4020");
1302 default_par->type = PM2_TYPE_PERMEDIA2;
1304 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1305 strcpy(pm2fb_fix.id, "Permedia2");
1306 default_par->type = PM2_TYPE_PERMEDIA2;
1308 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1309 strcpy(pm2fb_fix.id, "Permedia2v");
1310 default_par->type = PM2_TYPE_PERMEDIA2V;
1314 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1315 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1317 #if defined(__BIG_ENDIAN)
1319 * PM2 has a 64k register file, mapped twice in 128k. Lower
1320 * map is little-endian, upper map is big-endian.
1322 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1323 DPRINTK("Adjusting register base for big-endian.\n");
1325 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1327 /* Registers - request region and map it. */
1328 if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1330 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1331 goto err_exit_neither;
1333 default_par->v_regs =
1334 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1335 if (!default_par->v_regs) {
1336 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1338 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1339 goto err_exit_neither;
1342 /* Stash away memory register info for use when we reset the board */
1343 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1344 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1345 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1346 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1347 default_par->mem_control, default_par->boot_address,
1348 default_par->mem_config);
1350 if (default_par->mem_control == 0 &&
1351 default_par->boot_address == 0x31 &&
1352 default_par->mem_config == 0x259fffff) {
1353 default_par->memclock = CVPPC_MEMCLOCK;
1354 default_par->mem_control = 0;
1355 default_par->boot_address = 0x20;
1356 default_par->mem_config = 0xe6002021;
1357 if (pdev->subsystem_vendor == 0x1048 &&
1358 pdev->subsystem_device == 0x0a31) {
1359 DPRINTK("subsystem_vendor: %04x, "
1360 "subsystem_device: %04x\n",
1361 pdev->subsystem_vendor, pdev->subsystem_device);
1362 DPRINTK("We have not been initialized by VGA BIOS and "
1363 "are running on an Elsa Winner 2000 Office\n");
1364 DPRINTK("Initializing card timings manually...\n");
1365 default_par->memclock = 100000;
1367 if (pdev->subsystem_vendor == 0x3d3d &&
1368 pdev->subsystem_device == 0x0100) {
1369 DPRINTK("subsystem_vendor: %04x, "
1370 "subsystem_device: %04x\n",
1371 pdev->subsystem_vendor, pdev->subsystem_device);
1372 DPRINTK("We have not been initialized by VGA BIOS and "
1373 "are running on an 3dlabs reference board\n");
1374 DPRINTK("Initializing card timings manually...\n");
1375 default_par->memclock = 74894;
1379 /* Now work out how big lfb is going to be. */
1380 switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1381 case PM2F_MEM_BANKS_1:
1382 pm2fb_fix.smem_len = 0x200000;
1384 case PM2F_MEM_BANKS_2:
1385 pm2fb_fix.smem_len = 0x400000;
1387 case PM2F_MEM_BANKS_3:
1388 pm2fb_fix.smem_len = 0x600000;
1390 case PM2F_MEM_BANKS_4:
1391 pm2fb_fix.smem_len = 0x800000;
1394 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1396 /* Linear frame buffer - request region and map it. */
1397 if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1399 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1403 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1404 if (!info->screen_base) {
1405 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1406 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1411 default_par->mtrr_handle = -1;
1413 default_par->mtrr_handle =
1414 mtrr_add(pm2fb_fix.smem_start,
1416 MTRR_TYPE_WRCOMB, 1);
1419 info->fbops = &pm2fb_ops;
1420 info->fix = pm2fb_fix;
1421 info->pseudo_palette = default_par->palette;
1422 info->flags = FBINFO_DEFAULT |
1423 FBINFO_HWACCEL_YPAN |
1424 FBINFO_HWACCEL_COPYAREA |
1425 FBINFO_HWACCEL_IMAGEBLIT |
1426 FBINFO_HWACCEL_FILLRECT;
1428 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
1429 if (!info->pixmap.addr) {
1431 goto err_exit_pixmap;
1433 info->pixmap.size = PM2_PIXMAP_SIZE;
1434 info->pixmap.buf_align = 4;
1435 info->pixmap.scan_align = 4;
1436 info->pixmap.access_align = 32;
1437 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1440 printk(KERN_DEBUG "disabling acceleration\n");
1441 info->flags |= FBINFO_HWACCEL_DISABLED;
1442 info->pixmap.scan_align = 1;
1446 mode = "640x480@60";
1448 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1449 if (!err || err == 4)
1450 info->var = pm2fb_var;
1452 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1455 if (register_framebuffer(info) < 0)
1458 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1459 info->node, info->fix.id, pm2fb_fix.smem_len / 1024);
1464 pci_set_drvdata(pdev, info);
1469 fb_dealloc_cmap(&info->cmap);
1471 kfree(info->pixmap.addr);
1473 iounmap(info->screen_base);
1474 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1476 iounmap(default_par->v_regs);
1477 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1479 framebuffer_release(info);
1486 * Release all device resources.
1488 * @param pdev PCI device to clean up.
1490 static void __devexit pm2fb_remove(struct pci_dev *pdev)
1492 struct fb_info *info = pci_get_drvdata(pdev);
1493 struct fb_fix_screeninfo *fix = &info->fix;
1494 struct pm2fb_par *par = info->par;
1496 unregister_framebuffer(info);
1499 if (par->mtrr_handle >= 0)
1500 mtrr_del(par->mtrr_handle, info->fix.smem_start,
1501 info->fix.smem_len);
1502 #endif /* CONFIG_MTRR */
1503 iounmap(info->screen_base);
1504 release_mem_region(fix->smem_start, fix->smem_len);
1505 iounmap(par->v_regs);
1506 release_mem_region(fix->mmio_start, fix->mmio_len);
1508 pci_set_drvdata(pdev, NULL);
1509 kfree(info->pixmap.addr);
1513 static struct pci_device_id pm2fb_id_table[] = {
1514 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1516 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1518 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1523 static struct pci_driver pm2fb_driver = {
1525 .id_table = pm2fb_id_table,
1526 .probe = pm2fb_probe,
1527 .remove = __devexit_p(pm2fb_remove),
1530 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1535 * Parse user speficied options.
1537 * This is, comma-separated options following `video=pm2fb:'.
1539 static int __init pm2fb_setup(char *options)
1543 if (!options || !*options)
1546 while ((this_opt = strsep(&options, ",")) != NULL) {
1549 if (!strcmp(this_opt, "lowhsync"))
1551 else if (!strcmp(this_opt, "lowvsync"))
1554 else if (!strncmp(this_opt, "nomtrr", 6))
1557 else if (!strncmp(this_opt, "noaccel", 7))
1567 static int __init pm2fb_init(void)
1570 char *option = NULL;
1572 if (fb_get_options("pm2fb", &option))
1574 pm2fb_setup(option);
1577 return pci_register_driver(&pm2fb_driver);
1580 module_init(pm2fb_init);
1587 static void __exit pm2fb_exit(void)
1589 pci_unregister_driver(&pm2fb_driver);
1594 module_exit(pm2fb_exit);
1596 module_param(mode, charp, 0);
1597 MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1598 module_param(lowhsync, bool, 0);
1599 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1600 module_param(lowvsync, bool, 0);
1601 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1602 module_param(noaccel, bool, 0);
1603 MODULE_PARM_DESC(noaccel, "Disable acceleration");
1605 module_param(nomtrr, bool, 0);
1606 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1609 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1610 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1611 MODULE_LICENSE("GPL");