drivers/video/pm3fb.c

   1 /*
   2  *  linux/drivers/video/pm3fb.c -- 3DLabs Permedia3 frame buffer device
   3  *
   4  *  Copyright (C) 2001 Romain Dolbeau <romain@dolbeau.org>.
   5  *
   6  *  Ported to 2.6 kernel on 1 May 2007 by Krzysztof Helt <krzysztof.h1@wp.pl>
   7  *      based on pm2fb.c
   8  *
   9  *  Based on code written by:
  10  *         Sven Luther, <luther@dpt-info.u-strasbg.fr>
  11  *         Alan Hourihane, <alanh@fairlite.demon.co.uk>
  12  *         Russell King, <rmk@arm.linux.org.uk>
  13  *  Based on linux/drivers/video/skeletonfb.c:
  14  *      Copyright (C) 1997 Geert Uytterhoeven
  15  *  Based on linux/driver/video/pm2fb.c:
  16  *      Copyright (C) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  17  *      Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
  18  *
  19  *  This file is subject to the terms and conditions of the GNU General Public
  20  *  License. See the file COPYING in the main directory of this archive for
  21  *  more details.
  22  *
  23  */
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/errno.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/fb.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35
  36 #include <video/pm3fb.h>
  37
  38 #if !defined(CONFIG_PCI)
  39 #error "Only generic PCI cards supported."
  40 #endif
  41
  42 #undef PM3FB_MASTER_DEBUG
  43 #ifdef PM3FB_MASTER_DEBUG
  44 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm3fb: %s: " a, __FUNCTION__ , ## b)
  45 #else
  46 #define DPRINTK(a,b...)
  47 #endif
  48
  49 /*
  50  * Driver data
  51  */
  52 static char *mode_option __devinitdata;
  53
  54 /*
  55  * This structure defines the hardware state of the graphics card. Normally
  56  * you place this in a header file in linux/include/video. This file usually
  57  * also includes register information. That allows other driver subsystems
  58  * and userland applications the ability to use the same header file to
  59  * avoid duplicate work and easy porting of software.
  60  */
  61 struct pm3_par {
  62         unsigned char   __iomem *v_regs;/* virtual address of p_regs */
  63         u32             video;          /* video flags before blanking */
  64         u32             base;           /* screen base (xoffset+yoffset) in 128 bits unit */
  65         u32             palette[16];
  66 };
  67
  68 /*
  69  * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  70  * if we don't use modedb. If we do use modedb see pm3fb_init how to use it
  71  * to get a fb_var_screeninfo. Otherwise define a default var as well.
  72  */
  73 static struct fb_fix_screeninfo pm3fb_fix __devinitdata = {
  74         .id =           "Permedia3",
  75         .type =         FB_TYPE_PACKED_PIXELS,
  76         .visual =       FB_VISUAL_PSEUDOCOLOR,
  77         .xpanstep =     1,
  78         .ypanstep =     1,
  79         .ywrapstep =    0,
  80         .accel =        FB_ACCEL_3DLABS_PERMEDIA3,
  81 };
  82
  83 /*
  84  * Utility functions
  85  */
  86
  87 static inline u32 PM3_READ_REG(struct pm3_par *par, s32 off)
  88 {
  89         return fb_readl(par->v_regs + off);
  90 }
  91
  92 static inline void PM3_WRITE_REG(struct pm3_par *par, s32 off, u32 v)
  93 {
  94         fb_writel(v, par->v_regs + off);
  95 }
  96
  97 static inline void PM3_WAIT(struct pm3_par *par, u32 n)
  98 {
  99         while (PM3_READ_REG(par, PM3InFIFOSpace) < n);
 100 }
 101
 102 static inline void PM3_WRITE_DAC_REG(struct pm3_par *par, unsigned r, u8 v)
 103 {
 104         PM3_WAIT(par, 3);
 105         PM3_WRITE_REG(par, PM3RD_IndexHigh, (r >> 8) & 0xff);
 106         PM3_WRITE_REG(par, PM3RD_IndexLow, r & 0xff);
 107         wmb();
 108         PM3_WRITE_REG(par, PM3RD_IndexedData, v);
 109         wmb();
 110 }
 111
 112 static inline void pm3fb_set_color(struct pm3_par *par, unsigned char regno,
 113                         unsigned char r, unsigned char g, unsigned char b)
 114 {
 115         PM3_WAIT(par, 4);
 116         PM3_WRITE_REG(par, PM3RD_PaletteWriteAddress, regno);
 117         wmb();
 118         PM3_WRITE_REG(par, PM3RD_PaletteData, r);
 119         wmb();
 120         PM3_WRITE_REG(par, PM3RD_PaletteData, g);
 121         wmb();
 122         PM3_WRITE_REG(par, PM3RD_PaletteData, b);
 123         wmb();
 124 }
 125
 126 static void pm3fb_clear_colormap(struct pm3_par *par,
 127                         unsigned char r, unsigned char g, unsigned char b)
 128 {
 129         int i;
 130
 131         for (i = 0; i < 256 ; i++)
 132                 pm3fb_set_color(par, i, r, g, b);
 133
 134 }
 135
 136 /* Calculating various clock parameter */
 137 static void pm3fb_calculate_clock(unsigned long reqclock,
 138                                 unsigned char *prescale,
 139                                 unsigned char *feedback,
 140                                 unsigned char *postscale)
 141 {
 142         int f, pre, post;
 143         unsigned long freq;
 144         long freqerr = 1000;
 145         long currerr;
 146
 147         for (f = 1; f < 256; f++) {
 148                 for (pre = 1; pre < 256; pre++) {
 149                         for (post = 0; post < 5; post++) {
 150                                 freq = ((2*PM3_REF_CLOCK * f) >> post) / pre;
 151                                 currerr = (reqclock > freq)
 152                                         ? reqclock - freq
 153                                         : freq - reqclock;
 154                                 if (currerr < freqerr) {
 155                                         freqerr = currerr;
 156                                         *feedback = f;
 157                                         *prescale = pre;
 158                                         *postscale = post;
 159                                 }
 160                         }
 161                 }
 162         }
 163 }
 164
 165 static inline int pm3fb_depth(const struct fb_var_screeninfo *var)
 166 {
 167         if ( var->bits_per_pixel == 16 )
 168                 return var->red.length + var->green.length
 169                         + var->blue.length;
 170
 171         return var->bits_per_pixel;
 172 }
 173
 174 static inline int pm3fb_shift_bpp(unsigned bpp, int v)
 175 {
 176         switch (bpp) {
 177         case 8:
 178                 return (v >> 4);
 179         case 16:
 180                 return (v >> 3);
 181         case 32:
 182                 return (v >> 2);
 183         }
 184         DPRINTK("Unsupported depth %u\n", bpp);
 185         return 0;
 186 }
 187
 188 /* acceleration */
 189 static int pm3fb_sync(struct fb_info *info)
 190 {
 191         struct pm3_par *par = info->par;
 192
 193         PM3_WAIT(par, 2);
 194         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 195         PM3_WRITE_REG(par, PM3Sync, 0);
 196         mb();
 197         do {
 198                 while ((PM3_READ_REG(par, PM3OutFIFOWords)) == 0);
 199                 rmb();
 200         } while ((PM3_READ_REG(par, PM3OutputFifo)) != PM3Sync_Tag);
 201
 202         return 0;
 203 }
 204
 205 static void pm3fb_init_engine(struct fb_info *info)
 206 {
 207         struct pm3_par *par = info->par;
 208         const u32 width = (info->var.xres_virtual + 7) & ~7;
 209
 210         PM3_WAIT(par, 50);
 211         PM3_WRITE_REG(par, PM3FilterMode, PM3FilterModeSync);
 212         PM3_WRITE_REG(par, PM3StatisticMode, 0x0);
 213         PM3_WRITE_REG(par, PM3DeltaMode, 0x0);
 214         PM3_WRITE_REG(par, PM3RasterizerMode, 0x0);
 215         PM3_WRITE_REG(par, PM3ScissorMode, 0x0);
 216         PM3_WRITE_REG(par, PM3LineStippleMode, 0x0);
 217         PM3_WRITE_REG(par, PM3AreaStippleMode, 0x0);
 218         PM3_WRITE_REG(par, PM3GIDMode, 0x0);
 219         PM3_WRITE_REG(par, PM3DepthMode, 0x0);
 220         PM3_WRITE_REG(par, PM3StencilMode, 0x0);
 221         PM3_WRITE_REG(par, PM3StencilData, 0x0);
 222         PM3_WRITE_REG(par, PM3ColorDDAMode, 0x0);
 223         PM3_WRITE_REG(par, PM3TextureCoordMode, 0x0);
 224         PM3_WRITE_REG(par, PM3TextureIndexMode0, 0x0);
 225         PM3_WRITE_REG(par, PM3TextureIndexMode1, 0x0);
 226         PM3_WRITE_REG(par, PM3TextureReadMode, 0x0);
 227         PM3_WRITE_REG(par, PM3LUTMode, 0x0);
 228         PM3_WRITE_REG(par, PM3TextureFilterMode, 0x0);
 229         PM3_WRITE_REG(par, PM3TextureCompositeMode, 0x0);
 230         PM3_WRITE_REG(par, PM3TextureApplicationMode, 0x0);
 231         PM3_WRITE_REG(par, PM3TextureCompositeColorMode1, 0x0);
 232         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode1, 0x0);
 233         PM3_WRITE_REG(par, PM3TextureCompositeColorMode0, 0x0);
 234         PM3_WRITE_REG(par, PM3TextureCompositeAlphaMode0, 0x0);
 235         PM3_WRITE_REG(par, PM3FogMode, 0x0);
 236         PM3_WRITE_REG(par, PM3ChromaTestMode, 0x0);
 237         PM3_WRITE_REG(par, PM3AlphaTestMode, 0x0);
 238         PM3_WRITE_REG(par, PM3AntialiasMode, 0x0);
 239         PM3_WRITE_REG(par, PM3YUVMode, 0x0);
 240         PM3_WRITE_REG(par, PM3AlphaBlendColorMode, 0x0);
 241         PM3_WRITE_REG(par, PM3AlphaBlendAlphaMode, 0x0);
 242         PM3_WRITE_REG(par, PM3DitherMode, 0x0);
 243         PM3_WRITE_REG(par, PM3LogicalOpMode, 0x0);
 244         PM3_WRITE_REG(par, PM3RouterMode, 0x0);
 245         PM3_WRITE_REG(par, PM3Window, 0x0);
 246
 247         PM3_WRITE_REG(par, PM3Config2D, 0x0);
 248
 249         PM3_WRITE_REG(par, PM3SpanColorMask, 0xffffffff);
 250
 251         PM3_WRITE_REG(par, PM3XBias, 0x0);
 252         PM3_WRITE_REG(par, PM3YBias, 0x0);
 253         PM3_WRITE_REG(par, PM3DeltaControl, 0x0);
 254
 255         PM3_WRITE_REG(par, PM3BitMaskPattern, 0xffffffff);
 256
 257         PM3_WRITE_REG(par, PM3FBDestReadEnables,
 258                            PM3FBDestReadEnables_E(0xff) |
 259                            PM3FBDestReadEnables_R(0xff) |
 260                            PM3FBDestReadEnables_ReferenceAlpha(0xff));
 261         PM3_WRITE_REG(par, PM3FBDestReadBufferAddr0, 0x0);
 262         PM3_WRITE_REG(par, PM3FBDestReadBufferOffset0, 0x0);
 263         PM3_WRITE_REG(par, PM3FBDestReadBufferWidth0,
 264                            PM3FBDestReadBufferWidth_Width(width));
 265
 266         PM3_WRITE_REG(par, PM3FBDestReadMode,
 267                            PM3FBDestReadMode_ReadEnable |
 268                            PM3FBDestReadMode_Enable0);
 269         PM3_WRITE_REG(par, PM3FBSourceReadBufferAddr, 0x0);
 270         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset, 0x0);
 271         PM3_WRITE_REG(par, PM3FBSourceReadBufferWidth,
 272                            PM3FBSourceReadBufferWidth_Width(width));
 273         PM3_WRITE_REG(par, PM3FBSourceReadMode,
 274                            PM3FBSourceReadMode_Blocking |
 275                            PM3FBSourceReadMode_ReadEnable);
 276
 277         PM3_WAIT(par, 2);
 278         {
 279                 /* invert bits in bitmask */
 280                 unsigned long rm = 1 | (3 << 7);
 281                 switch (info->var.bits_per_pixel) {
 282                 case 8:
 283                         PM3_WRITE_REG(par, PM3PixelSize,
 284                                            PM3PixelSize_GLOBAL_8BIT);
 285 #ifdef __BIG_ENDIAN
 286                         rm |= 3 << 15;
 287 #endif
 288                         break;
 289                 case 16:
 290                         PM3_WRITE_REG(par, PM3PixelSize,
 291                                            PM3PixelSize_GLOBAL_16BIT);
 292 #ifdef __BIG_ENDIAN
 293                         rm |= 2 << 15;
 294 #endif
 295                         break;
 296                 case 32:
 297                         PM3_WRITE_REG(par, PM3PixelSize,
 298                                            PM3PixelSize_GLOBAL_32BIT);
 299                         break;
 300                 default:
 301                         DPRINTK(1, "Unsupported depth %d\n",
 302                                 info->var.bits_per_pixel);
 303                         break;
 304                 }
 305                 PM3_WRITE_REG(par, PM3RasterizerMode, rm);
 306         }
 307
 308         PM3_WAIT(par, 20);
 309         PM3_WRITE_REG(par, PM3FBSoftwareWriteMask, 0xffffffff);
 310         PM3_WRITE_REG(par, PM3FBHardwareWriteMask, 0xffffffff);
 311         PM3_WRITE_REG(par, PM3FBWriteMode,
 312                            PM3FBWriteMode_WriteEnable |
 313                            PM3FBWriteMode_OpaqueSpan |
 314                            PM3FBWriteMode_Enable0);
 315         PM3_WRITE_REG(par, PM3FBWriteBufferAddr0, 0x0);
 316         PM3_WRITE_REG(par, PM3FBWriteBufferOffset0, 0x0);
 317         PM3_WRITE_REG(par, PM3FBWriteBufferWidth0,
 318                            PM3FBWriteBufferWidth_Width(width));
 319
 320         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 0x0);
 321         {
 322                 /* size in lines of FB */
 323                 unsigned long sofb = info->screen_size /
 324                         info->fix.line_length;
 325                 if (sofb > 4095)
 326                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, 4095);
 327                 else
 328                         PM3_WRITE_REG(par, PM3SizeOfFramebuffer, sofb);
 329
 330                 switch (info->var.bits_per_pixel) {
 331                 case 8:
 332                         PM3_WRITE_REG(par, PM3DitherMode,
 333                                            (1 << 10) | (2 << 3));
 334                         break;
 335                 case 16:
 336                         PM3_WRITE_REG(par, PM3DitherMode,
 337                                            (1 << 10) | (1 << 3));
 338                         break;
 339                 case 32:
 340                         PM3_WRITE_REG(par, PM3DitherMode,
 341                                            (1 << 10) | (0 << 3));
 342                         break;
 343                 default:
 344                         DPRINTK(1, "Unsupported depth %d\n",
 345                                 info->current_par->depth);
 346                         break;
 347                 }
 348         }
 349
 350         PM3_WRITE_REG(par, PM3dXDom, 0x0);
 351         PM3_WRITE_REG(par, PM3dXSub, 0x0);
 352         PM3_WRITE_REG(par, PM3dY, (1 << 16));
 353         PM3_WRITE_REG(par, PM3StartXDom, 0x0);
 354         PM3_WRITE_REG(par, PM3StartXSub, 0x0);
 355         PM3_WRITE_REG(par, PM3StartY, 0x0);
 356         PM3_WRITE_REG(par, PM3Count, 0x0);
 357
 358 /* Disable LocalBuffer. better safe than sorry */
 359         PM3_WRITE_REG(par, PM3LBDestReadMode, 0x0);
 360         PM3_WRITE_REG(par, PM3LBDestReadEnables, 0x0);
 361         PM3_WRITE_REG(par, PM3LBSourceReadMode, 0x0);
 362         PM3_WRITE_REG(par, PM3LBWriteMode, 0x0);
 363
 364         pm3fb_sync(info);
 365 }
 366
 367 static void pm3fb_fillrect (struct fb_info *info,
 368                                 const struct fb_fillrect *region)
 369 {
 370         struct pm3_par *par = info->par;
 371         struct fb_fillrect modded;
 372         int vxres, vyres;
 373         u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
 374                 ((u32*)info->pseudo_palette)[region->color] : region->color;
 375
 376         if (info->state != FBINFO_STATE_RUNNING)
 377                 return;
 378         if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
 379                 region->rop != ROP_COPY ) {
 380                 cfb_fillrect(info, region);
 381                 return;
 382         }
 383
 384         vxres = info->var.xres_virtual;
 385         vyres = info->var.yres_virtual;
 386
 387         memcpy(&modded, region, sizeof(struct fb_fillrect));
 388
 389         if(!modded.width || !modded.height ||
 390            modded.dx >= vxres || modded.dy >= vyres)
 391                 return;
 392
 393         if(modded.dx + modded.width  > vxres)
 394                 modded.width  = vxres - modded.dx;
 395         if(modded.dy + modded.height > vyres)
 396                 modded.height = vyres - modded.dy;
 397
 398         if(info->var.bits_per_pixel == 8)
 399                 color |= color << 8;
 400         if(info->var.bits_per_pixel <= 16)
 401                 color |= color << 16;
 402
 403         PM3_WAIT(par, 4);
 404         /* ROP Ox3 is GXcopy */
 405         PM3_WRITE_REG(par, PM3Config2D,
 406                         PM3Config2D_UseConstantSource |
 407                         PM3Config2D_ForegroundROPEnable |
 408                         (PM3Config2D_ForegroundROP(0x3)) |
 409                         PM3Config2D_FBWriteEnable);
 410
 411         PM3_WRITE_REG(par, PM3ForegroundColor, color);
 412
 413         PM3_WRITE_REG(par, PM3RectanglePosition,
 414                         (PM3RectanglePosition_XOffset(modded.dx)) |
 415                         (PM3RectanglePosition_YOffset(modded.dy)));
 416
 417         PM3_WRITE_REG(par, PM3Render2D,
 418                       PM3Render2D_XPositive |
 419                       PM3Render2D_YPositive |
 420                       PM3Render2D_Operation_Normal |
 421                       PM3Render2D_SpanOperation |
 422                       (PM3Render2D_Width(modded.width)) |
 423                       (PM3Render2D_Height(modded.height)));
 424 }
 425
 426 static void pm3fb_copyarea(struct fb_info *info,
 427                                 const struct fb_copyarea *area)
 428 {
 429         struct pm3_par *par = info->par;
 430         struct fb_copyarea modded;
 431         u32 vxres, vyres;
 432         int x_align, o_x, o_y;
 433
 434         if (info->state != FBINFO_STATE_RUNNING)
 435                 return;
 436         if (info->flags & FBINFO_HWACCEL_DISABLED) {
 437                 cfb_copyarea(info, area);
 438                 return;
 439         }
 440
 441         memcpy(&modded, area, sizeof(struct fb_copyarea));
 442
 443         vxres = info->var.xres_virtual;
 444         vyres = info->var.yres_virtual;
 445
 446         if(!modded.width || !modded.height ||
 447            modded.sx >= vxres || modded.sy >= vyres ||
 448            modded.dx >= vxres || modded.dy >= vyres)
 449                 return;
 450
 451         if(modded.sx + modded.width > vxres)
 452                 modded.width = vxres - modded.sx;
 453         if(modded.dx + modded.width > vxres)
 454                 modded.width = vxres - modded.dx;
 455         if(modded.sy + modded.height > vyres)
 456                 modded.height = vyres - modded.sy;
 457         if(modded.dy + modded.height > vyres)
 458                 modded.height = vyres - modded.dy;
 459
 460         o_x = modded.sx - modded.dx;    /*(sx > dx ) ? (sx - dx) : (dx - sx); */
 461         o_y = modded.sy - modded.dy;    /*(sy > dy ) ? (sy - dy) : (dy - sy); */
 462
 463         x_align = (modded.sx & 0x1f);
 464
 465         PM3_WAIT(par, 6);
 466
 467         PM3_WRITE_REG(par, PM3Config2D,
 468                         PM3Config2D_UserScissorEnable |
 469                         PM3Config2D_ForegroundROPEnable |
 470                         PM3Config2D_Blocking |
 471                         (PM3Config2D_ForegroundROP(0x3)) | /* Ox3 is GXcopy */
 472                         PM3Config2D_FBWriteEnable);
 473
 474         PM3_WRITE_REG(par, PM3ScissorMinXY,
 475                         ((modded.dy & 0x0fff) << 16) | (modded.dx & 0x0fff));
 476         PM3_WRITE_REG(par, PM3ScissorMaxXY,
 477                         (((modded.dy + modded.height) & 0x0fff) << 16) |
 478                         ((modded.dx + modded.width) & 0x0fff));
 479
 480         PM3_WRITE_REG(par, PM3FBSourceReadBufferOffset,
 481                         PM3FBSourceReadBufferOffset_XOffset(o_x) |
 482                         PM3FBSourceReadBufferOffset_YOffset(o_y));
 483
 484         PM3_WRITE_REG(par, PM3RectanglePosition,
 485                         (PM3RectanglePosition_XOffset(modded.dx - x_align)) |
 486                         (PM3RectanglePosition_YOffset(modded.dy)));
 487
 488         PM3_WRITE_REG(par, PM3Render2D,
 489                         ((modded.sx > modded.dx) ? PM3Render2D_XPositive : 0) |
 490                         ((modded.sy > modded.dy) ? PM3Render2D_YPositive : 0) |
 491                         PM3Render2D_Operation_Normal |
 492                         PM3Render2D_SpanOperation |
 493                         PM3Render2D_FBSourceReadEnable |
 494                         (PM3Render2D_Width(modded.width + x_align)) |
 495                         (PM3Render2D_Height(modded.height)));
 496 }
 497
 498 static void pm3fb_imageblit(struct fb_info *info, const struct fb_image *image)
 499 {
 500         struct pm3_par *par = info->par;
 501         u32 height = image->height;
 502         u32 fgx, bgx;
 503         const u32 *src = (const u32*)image->data;
 504
 505         switch (info->fix.visual) {
 506                 case FB_VISUAL_PSEUDOCOLOR:
 507                         fgx = image->fg_color;
 508                         bgx = image->bg_color;
 509                         break;
 510                 case FB_VISUAL_TRUECOLOR:
 511                 default:
 512                         fgx = par->palette[image->fg_color];
 513                         bgx = par->palette[image->bg_color];
 514                         break;
 515         }
 516         if (image->depth != 1 || (image->width & 0x1f)) {
 517                 return cfb_imageblit(info, image);
 518         }
 519         if (info->var.bits_per_pixel == 8) {
 520                 fgx |= fgx << 8;
 521                 bgx |= bgx << 8;
 522         }
 523         if (info->var.bits_per_pixel <= 16) {
 524                 fgx |= fgx << 16;
 525                 bgx |= bgx << 16;
 526         }
 527
 528         PM3_WAIT(par, 5);
 529
 530         PM3_WRITE_REG(par, PM3ForegroundColor, fgx);
 531         PM3_WRITE_REG(par, PM3BackgroundColor, bgx);
 532
 533         /* ROP Ox3 is GXcopy */
 534         PM3_WRITE_REG(par, PM3Config2D,
 535                         PM3Config2D_UseConstantSource |
 536                         PM3Config2D_ForegroundROPEnable |
 537                         (PM3Config2D_ForegroundROP(0x3)) |
 538                         PM3Config2D_OpaqueSpan |
 539                         PM3Config2D_FBWriteEnable);
 540         PM3_WRITE_REG(par, PM3RectanglePosition,
 541                         (PM3RectanglePosition_XOffset(image->dx)) |
 542                         (PM3RectanglePosition_YOffset(image->dy)));
 543         PM3_WRITE_REG(par, PM3Render2D,
 544                         PM3Render2D_XPositive |
 545                         PM3Render2D_YPositive |
 546                         PM3Render2D_Operation_SyncOnBitMask |
 547                         PM3Render2D_SpanOperation |
 548                         (PM3Render2D_Width(image->width)) |
 549                         (PM3Render2D_Height(image->height)));
 550
 551
 552         while (height--) {
 553                 u32 width = (image->width + 31) >> 5;
 554
 555                 while (width >= PM3_FIFO_SIZE) {
 556                         int i = PM3_FIFO_SIZE - 1;
 557
 558                         PM3_WAIT(par, PM3_FIFO_SIZE);
 559                         while (i--) {
 560                                 PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
 561                                 src++;
 562                         }
 563                         width -= PM3_FIFO_SIZE - 1;
 564                 }
 565
 566                 PM3_WAIT(par, width + 1);
 567                 while (width--) {
 568                         PM3_WRITE_REG(par, PM3BitMaskPattern, *src);
 569                         src++;
 570                 }
 571         }
 572 }
 573 /* end of acceleration functions */
 574
 575 /* write the mode to registers */
 576 static void pm3fb_write_mode(struct fb_info *info)
 577 {
 578         struct pm3_par *par = info->par;
 579         char tempsync = 0x00, tempmisc = 0x00;
 580         const u32 hsstart = info->var.right_margin;
 581         const u32 hsend = hsstart + info->var.hsync_len;
 582         const u32 hbend = hsend + info->var.left_margin;
 583         const u32 xres = (info->var.xres + 31) & ~31;
 584         const u32 htotal = xres + hbend;
 585         const u32 vsstart = info->var.lower_margin;
 586         const u32 vsend = vsstart + info->var.vsync_len;
 587         const u32 vbend = vsend + info->var.upper_margin;
 588         const u32 vtotal = info->var.yres + vbend;
 589         const u32 width = (info->var.xres_virtual + 7) & ~7;
 590         const unsigned bpp = info->var.bits_per_pixel;
 591
 592         PM3_WAIT(par, 20);
 593         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xffffffff);
 594         PM3_WRITE_REG(par, PM3Aperture0, 0x00000000);
 595         PM3_WRITE_REG(par, PM3Aperture1, 0x00000000);
 596         PM3_WRITE_REG(par, PM3FIFODis, 0x00000007);
 597
 598         PM3_WRITE_REG(par, PM3HTotal,
 599                            pm3fb_shift_bpp(bpp, htotal - 1));
 600         PM3_WRITE_REG(par, PM3HsEnd,
 601                            pm3fb_shift_bpp(bpp, hsend));
 602         PM3_WRITE_REG(par, PM3HsStart,
 603                            pm3fb_shift_bpp(bpp, hsstart));
 604         PM3_WRITE_REG(par, PM3HbEnd,
 605                            pm3fb_shift_bpp(bpp, hbend));
 606         PM3_WRITE_REG(par, PM3HgEnd,
 607                            pm3fb_shift_bpp(bpp, hbend));
 608         PM3_WRITE_REG(par, PM3ScreenStride,
 609                            pm3fb_shift_bpp(bpp, width));
 610         PM3_WRITE_REG(par, PM3VTotal, vtotal - 1);
 611         PM3_WRITE_REG(par, PM3VsEnd, vsend - 1);
 612         PM3_WRITE_REG(par, PM3VsStart, vsstart - 1);
 613         PM3_WRITE_REG(par, PM3VbEnd, vbend);
 614
 615         switch (bpp) {
 616         case 8:
 617                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 618                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 619                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 620                                    PM3ByApertureMode_PIXELSIZE_8BIT);
 621                 break;
 622
 623         case 16:
 624 #ifndef __BIG_ENDIAN
 625                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 626                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 627                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 628                                    PM3ByApertureMode_PIXELSIZE_16BIT);
 629 #else
 630                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 631                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 632                                    PM3ByApertureMode_BYTESWAP_BADC);
 633                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 634                                    PM3ByApertureMode_PIXELSIZE_16BIT |
 635                                    PM3ByApertureMode_BYTESWAP_BADC);
 636 #endif /* ! __BIG_ENDIAN */
 637                 break;
 638
 639         case 32:
 640 #ifndef __BIG_ENDIAN
 641                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 642                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 643                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 644                                    PM3ByApertureMode_PIXELSIZE_32BIT);
 645 #else
 646                 PM3_WRITE_REG(par, PM3ByAperture1Mode,
 647                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 648                                    PM3ByApertureMode_BYTESWAP_DCBA);
 649                 PM3_WRITE_REG(par, PM3ByAperture2Mode,
 650                                    PM3ByApertureMode_PIXELSIZE_32BIT |
 651                                    PM3ByApertureMode_BYTESWAP_DCBA);
 652 #endif /* ! __BIG_ENDIAN */
 653                 break;
 654
 655         default:
 656                 DPRINTK("Unsupported depth %d\n", bpp);
 657                 break;
 658         }
 659
 660         /*
 661          * Oxygen VX1 - it appears that setting PM3VideoControl and
 662          * then PM3RD_SyncControl to the same SYNC settings undoes
 663          * any net change - they seem to xor together.  Only set the
 664          * sync options in PM3RD_SyncControl.  --rmk
 665          */
 666         {
 667                 unsigned int video = par->video;
 668
 669                 video &= ~(PM3VideoControl_HSYNC_MASK |
 670                            PM3VideoControl_VSYNC_MASK);
 671                 video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
 672                          PM3VideoControl_VSYNC_ACTIVE_HIGH;
 673                 PM3_WRITE_REG(par, PM3VideoControl, video);
 674         }
 675         PM3_WRITE_REG(par, PM3VClkCtl,
 676                            (PM3_READ_REG(par, PM3VClkCtl) & 0xFFFFFFFC));
 677         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
 678         PM3_WRITE_REG(par, PM3ChipConfig,
 679                            (PM3_READ_REG(par, PM3ChipConfig) & 0xFFFFFFFD));
 680
 681         wmb();
 682         {
 683                 unsigned char uninitialized_var(m);     /* ClkPreScale */
 684                 unsigned char uninitialized_var(n);     /* ClkFeedBackScale */
 685                 unsigned char uninitialized_var(p);     /* ClkPostScale */
 686                 unsigned long pixclock = PICOS2KHZ(info->var.pixclock);
 687
 688                 (void)pm3fb_calculate_clock(pixclock, &m, &n, &p);
 689
 690                 DPRINTK("Pixclock: %ld, Pre: %d, Feedback: %d, Post: %d\n",
 691                         pixclock, (int) m, (int) n, (int) p);
 692
 693                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PreScale, m);
 694                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0FeedbackScale, n);
 695                 PM3_WRITE_DAC_REG(par, PM3RD_DClk0PostScale, p);
 696         }
 697         /*
 698            PM3_WRITE_DAC_REG(par, PM3RD_IndexControl, 0x00);
 699          */
 700         /*
 701            PM3_SLOW_WRITE_REG(par, PM3RD_IndexControl, 0x00);
 702          */
 703         if ((par->video & PM3VideoControl_HSYNC_MASK) ==
 704             PM3VideoControl_HSYNC_ACTIVE_HIGH)
 705                 tempsync |= PM3RD_SyncControl_HSYNC_ACTIVE_HIGH;
 706         if ((par->video & PM3VideoControl_VSYNC_MASK) ==
 707             PM3VideoControl_VSYNC_ACTIVE_HIGH)
 708                 tempsync |= PM3RD_SyncControl_VSYNC_ACTIVE_HIGH;
 709
 710         PM3_WRITE_DAC_REG(par, PM3RD_SyncControl, tempsync);
 711         DPRINTK("PM3RD_SyncControl: %d\n", tempsync);
 712
 713         PM3_WRITE_DAC_REG(par, PM3RD_DACControl, 0x00);
 714
 715         switch (pm3fb_depth(&info->var)) {
 716         case 8:
 717                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 718                                   PM3RD_PixelSize_8_BIT_PIXELS);
 719                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 720                                   PM3RD_ColorFormat_CI8_COLOR |
 721                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 722                 tempmisc |= PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 723                 break;
 724         case 12:
 725                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 726                                   PM3RD_PixelSize_16_BIT_PIXELS);
 727                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 728                                   PM3RD_ColorFormat_4444_COLOR |
 729                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 730                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 731                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 732                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 733                 break;
 734         case 15:
 735                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 736                                   PM3RD_PixelSize_16_BIT_PIXELS);
 737                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 738                                   PM3RD_ColorFormat_5551_FRONT_COLOR |
 739                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 740                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 741                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 742                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 743                 break;
 744         case 16:
 745                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 746                                   PM3RD_PixelSize_16_BIT_PIXELS);
 747                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 748                                   PM3RD_ColorFormat_565_FRONT_COLOR |
 749                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW |
 750                                   PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE);
 751                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 752                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 753                 break;
 754         case 32:
 755                 PM3_WRITE_DAC_REG(par, PM3RD_PixelSize,
 756                                   PM3RD_PixelSize_32_BIT_PIXELS);
 757                 PM3_WRITE_DAC_REG(par, PM3RD_ColorFormat,
 758                                   PM3RD_ColorFormat_8888_COLOR |
 759                                   PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW);
 760                 tempmisc |= PM3RD_MiscControl_DIRECTCOLOR_ENABLE |
 761                         PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE;
 762                 break;
 763         }
 764         PM3_WRITE_DAC_REG(par, PM3RD_MiscControl, tempmisc);
 765 }
 766
 767 /*
 768  * hardware independent functions
 769  */
 770 static int pm3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 771 {
 772         u32 lpitch;
 773         unsigned bpp = var->red.length + var->green.length
 774                         + var->blue.length + var->transp.length;
 775
 776         if ( bpp != var->bits_per_pixel ) {
 777                 /* set predefined mode for bits_per_pixel settings */
 778
 779                 switch(var->bits_per_pixel) {
 780                 case 8:
 781                         var->red.length = var->green.length = var->blue.length = 8;
 782                         var->red.offset = var->green.offset = var->blue.offset = 0;
 783                         var->transp.offset = 0;
 784                         var->transp.length = 0;
 785                         break;
 786                 case 16:
 787                         var->red.length = var->blue.length = 5;
 788                         var->green.length = 6;
 789                         var->transp.length = 0;
 790                         break;
 791                 case 32:
 792                         var->red.length = var->green.length = var->blue.length = 8;
 793                         var->transp.length = 8;
 794                         break;
 795                 default:
 796                         DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 797                         return -EINVAL;
 798                 }
 799         }
 800         /* it is assumed BGRA order */
 801         if (var->bits_per_pixel > 8 )
 802         {
 803                 var->blue.offset = 0;
 804                 var->green.offset = var->blue.length;
 805                 var->red.offset = var->green.offset + var->green.length;
 806                 var->transp.offset = var->red.offset + var->red.length;
 807         }
 808         var->height = var->width = -1;
 809
 810         if (var->xres != var->xres_virtual) {
 811                 DPRINTK("virtual x resolution != physical x resolution not supported\n");
 812                 return -EINVAL;
 813         }
 814
 815         if (var->yres > var->yres_virtual) {
 816                 DPRINTK("virtual y resolution < physical y resolution not possible\n");
 817                 return -EINVAL;
 818         }
 819
 820         if (var->xoffset) {
 821                 DPRINTK("xoffset not supported\n");
 822                 return -EINVAL;
 823         }
 824
 825         if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
 826                 DPRINTK("interlace not supported\n");
 827                 return -EINVAL;
 828         }
 829
 830         var->xres = (var->xres + 31) & ~31; /* could sometimes be 8 */
 831         lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
 832
 833         if (var->xres < 200 || var->xres > 2048) {
 834                 DPRINTK("width not supported: %u\n", var->xres);
 835                 return -EINVAL;
 836         }
 837
 838         if (var->yres < 200 || var->yres > 4095) {
 839                 DPRINTK("height not supported: %u\n", var->yres);
 840                 return -EINVAL;
 841         }
 842
 843         if (lpitch * var->yres_virtual > info->fix.smem_len) {
 844                 DPRINTK("no memory for screen (%ux%ux%u)\n",
 845                         var->xres, var->yres_virtual, var->bits_per_pixel);
 846                 return -EINVAL;
 847         }
 848
 849         if (PICOS2KHZ(var->pixclock) > PM3_MAX_PIXCLOCK) {
 850                 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
 851                 return -EINVAL;
 852         }
 853
 854         var->accel_flags = 0;   /* Can't mmap if this is on */
 855
 856         DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 857                 var->xres, var->yres, var->bits_per_pixel);
 858         return 0;
 859 }
 860
 861 static int pm3fb_set_par(struct fb_info *info)
 862 {
 863         struct pm3_par *par = info->par;
 864         const u32 xres = (info->var.xres + 31) & ~31;
 865         const unsigned bpp = info->var.bits_per_pixel;
 866
 867         par->base = pm3fb_shift_bpp(bpp,(info->var.yoffset * xres)
 868                                         + info->var.xoffset);
 869         par->video = 0;
 870
 871         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 872                 par->video |= PM3VideoControl_HSYNC_ACTIVE_HIGH;
 873         else
 874                 par->video |= PM3VideoControl_HSYNC_ACTIVE_LOW;
 875
 876         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 877                 par->video |= PM3VideoControl_VSYNC_ACTIVE_HIGH;
 878         else
 879                 par->video |= PM3VideoControl_VSYNC_ACTIVE_LOW;
 880
 881         if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
 882                 par->video |= PM3VideoControl_LINE_DOUBLE_ON;
 883         else
 884                 par->video |= PM3VideoControl_LINE_DOUBLE_OFF;
 885
 886         if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
 887                 par->video |= PM3VideoControl_ENABLE;
 888         else {
 889                 par->video |= PM3VideoControl_DISABLE;
 890                 DPRINTK("PM3Video disabled\n");
 891         }
 892         switch (bpp) {
 893         case 8:
 894                 par->video |= PM3VideoControl_PIXELSIZE_8BIT;
 895                 break;
 896         case 16:
 897                 par->video |= PM3VideoControl_PIXELSIZE_16BIT;
 898                 break;
 899         case 32:
 900                 par->video |= PM3VideoControl_PIXELSIZE_32BIT;
 901                 break;
 902         default:
 903                 DPRINTK("Unsupported depth\n");
 904                 break;
 905         }
 906
 907         info->fix.visual =
 908                 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
 909         info->fix.line_length = ((info->var.xres_virtual + 7)  & ~7)
 910                                         * bpp / 8;
 911
 912 /*      pm3fb_clear_memory(info, 0);*/
 913         pm3fb_clear_colormap(par, 0, 0, 0);
 914         PM3_WRITE_DAC_REG(par, PM3RD_CursorMode,
 915                           PM3RD_CursorMode_CURSOR_DISABLE);
 916         pm3fb_init_engine(info);
 917         pm3fb_write_mode(info);
 918         return 0;
 919 }
 920
 921 static int pm3fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 922                            unsigned blue, unsigned transp,
 923                            struct fb_info *info)
 924 {
 925         struct pm3_par *par = info->par;
 926
 927         if (regno >= 256)  /* no. of hw registers */
 928            return -EINVAL;
 929
 930         /* grayscale works only partially under directcolor */
 931         if (info->var.grayscale) {
 932            /* grayscale = 0.30*R + 0.59*G + 0.11*B */
 933            red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
 934         }
 935
 936         /* Directcolor:
 937          *   var->{color}.offset contains start of bitfield
 938          *   var->{color}.length contains length of bitfield
 939          *   {hardwarespecific} contains width of DAC
 940          *   pseudo_palette[X] is programmed to (X << red.offset) |
 941          *                                      (X << green.offset) |
 942          *                                      (X << blue.offset)
 943          *   RAMDAC[X] is programmed to (red, green, blue)
 944          *   color depth = SUM(var->{color}.length)
 945          *
 946          * Pseudocolor:
 947          *      var->{color}.offset is 0
 948          *      var->{color}.length contains width of DAC or the number of unique
 949          *                      colors available (color depth)
 950          *      pseudo_palette is not used
 951          *      RAMDAC[X] is programmed to (red, green, blue)
 952          *      color depth = var->{color}.length
 953          */
 954
 955         /*
 956          * This is the point where the color is converted to something that
 957          * is acceptable by the hardware.
 958          */
 959 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
 960         red = CNVT_TOHW(red, info->var.red.length);
 961         green = CNVT_TOHW(green, info->var.green.length);
 962         blue = CNVT_TOHW(blue, info->var.blue.length);
 963         transp = CNVT_TOHW(transp, info->var.transp.length);
 964 #undef CNVT_TOHW
 965
 966         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
 967         info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 968                 u32 v;
 969
 970                 if (regno >= 16)
 971                         return -EINVAL;
 972
 973                 v = (red << info->var.red.offset) |
 974                         (green << info->var.green.offset) |
 975                         (blue << info->var.blue.offset) |
 976                         (transp << info->var.transp.offset);
 977
 978                 switch (info->var.bits_per_pixel) {
 979                 case 8:
 980                         break;
 981                 case 16:
 982                 case 32:
 983                         ((u32*)(info->pseudo_palette))[regno] = v;
 984                         break;
 985                 }
 986                 return 0;
 987         }
 988         else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
 989                 pm3fb_set_color(par, regno, red, green, blue);
 990
 991         return 0;
 992 }
 993
 994 static int pm3fb_pan_display(struct fb_var_screeninfo *var,
 995                                  struct fb_info *info)
 996 {
 997         struct pm3_par *par = info->par;
 998         const u32 xres = (var->xres + 31) & ~31;
 999
1000         par->base = pm3fb_shift_bpp(var->bits_per_pixel,
1001                                         (var->yoffset * xres)
1002                                         + var->xoffset);
1003         PM3_WAIT(par, 1);
1004         PM3_WRITE_REG(par, PM3ScreenBase, par->base);
1005         return 0;
1006 }
1007
1008 static int pm3fb_blank(int blank_mode, struct fb_info *info)
1009 {
1010         struct pm3_par *par = info->par;
1011         u32 video = par->video;
1012
1013         /*
1014          * Oxygen VX1 - it appears that setting PM3VideoControl and
1015          * then PM3RD_SyncControl to the same SYNC settings undoes
1016          * any net change - they seem to xor together.  Only set the
1017          * sync options in PM3RD_SyncControl.  --rmk
1018          */
1019         video &= ~(PM3VideoControl_HSYNC_MASK |
1020                    PM3VideoControl_VSYNC_MASK);
1021         video |= PM3VideoControl_HSYNC_ACTIVE_HIGH |
1022                  PM3VideoControl_VSYNC_ACTIVE_HIGH;
1023
1024         switch (blank_mode) {
1025         case FB_BLANK_UNBLANK:
1026                 video |= PM3VideoControl_ENABLE;
1027                 break;
1028         case FB_BLANK_NORMAL:
1029                 video &= ~(PM3VideoControl_ENABLE);
1030                 break;
1031         case FB_BLANK_HSYNC_SUSPEND:
1032                 video &= ~(PM3VideoControl_HSYNC_MASK |
1033                           PM3VideoControl_BLANK_ACTIVE_LOW);
1034                 break;
1035         case FB_BLANK_VSYNC_SUSPEND:
1036                 video &= ~(PM3VideoControl_VSYNC_MASK |
1037                           PM3VideoControl_BLANK_ACTIVE_LOW);
1038                 break;
1039         case FB_BLANK_POWERDOWN:
1040                 video &= ~(PM3VideoControl_HSYNC_MASK |
1041                           PM3VideoControl_VSYNC_MASK |
1042                           PM3VideoControl_BLANK_ACTIVE_LOW);
1043                 break;
1044         default:
1045                 DPRINTK("Unsupported blanking %d\n", blank_mode);
1046                 return 1;
1047         }
1048
1049         PM3_WAIT(par, 1);
1050         PM3_WRITE_REG(par,PM3VideoControl, video);
1051         return 0;
1052 }
1053
1054         /*
1055          *  Frame buffer operations
1056          */
1057
1058 static struct fb_ops pm3fb_ops = {
1059         .owner          = THIS_MODULE,
1060         .fb_check_var   = pm3fb_check_var,
1061         .fb_set_par     = pm3fb_set_par,
1062         .fb_setcolreg   = pm3fb_setcolreg,
1063         .fb_pan_display = pm3fb_pan_display,
1064         .fb_fillrect    = pm3fb_fillrect,
1065         .fb_copyarea    = pm3fb_copyarea,
1066         .fb_imageblit   = pm3fb_imageblit,
1067         .fb_blank       = pm3fb_blank,
1068         .fb_sync        = pm3fb_sync,
1069 };
1070
1071 /* ------------------------------------------------------------------------- */
1072
1073         /*
1074          *  Initialization
1075          */
1076
1077 /* mmio register are already mapped when this function is called */
1078 /* the pm3fb_fix.smem_start is also set */
1079 static unsigned long pm3fb_size_memory(struct pm3_par *par)
1080 {
1081         unsigned long   memsize = 0, tempBypass, i, temp1, temp2;
1082         unsigned char   __iomem *screen_mem;
1083
1084         pm3fb_fix.smem_len = 64 * 1024l * 1024; /* request full aperture size */
1085         /* Linear frame buffer - request region and map it. */
1086         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1087                                  "pm3fb smem")) {
1088                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1089                 return 0;
1090         }
1091         screen_mem =
1092                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1093         if (!screen_mem) {
1094                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1095                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1096                 return 0;
1097         }
1098
1099         /* TODO: card-specific stuff, *before* accessing *any* FB memory */
1100         /* For Appian Jeronimo 2000 board second head */
1101
1102         tempBypass = PM3_READ_REG(par, PM3MemBypassWriteMask);
1103
1104         DPRINTK("PM3MemBypassWriteMask was: 0x%08lx\n", tempBypass);
1105
1106         PM3_WAIT(par, 1);
1107         PM3_WRITE_REG(par, PM3MemBypassWriteMask, 0xFFFFFFFF);
1108
1109         /* pm3 split up memory, replicates, and do a lot of nasty stuff IMHO ;-) */
1110         for (i = 0; i < 32; i++) {
1111                 fb_writel(i * 0x00345678,
1112                           (screen_mem + (i * 1048576)));
1113                 mb();
1114                 temp1 = fb_readl((screen_mem + (i * 1048576)));
1115
1116                 /* Let's check for wrapover, write will fail at 16MB boundary */
1117                 if (temp1 == (i * 0x00345678))
1118                         memsize = i;
1119                 else
1120                         break;
1121         }
1122
1123         DPRINTK("First detect pass already got %ld MB\n", memsize + 1);
1124
1125         if (memsize + 1 == i) {
1126                 for (i = 0; i < 32; i++) {
1127                         /* Clear first 32MB ; 0 is 0, no need to byteswap */
1128                         writel(0x0000000, (screen_mem + (i * 1048576)));
1129                 }
1130                 wmb();
1131
1132                 for (i = 32; i < 64; i++) {
1133                         fb_writel(i * 0x00345678,
1134                                   (screen_mem + (i * 1048576)));
1135                         mb();
1136                         temp1 =
1137                             fb_readl((screen_mem + (i * 1048576)));
1138                         temp2 =
1139                             fb_readl((screen_mem + ((i - 32) * 1048576)));
1140                         /* different value, different RAM... */
1141                         if ((temp1 == (i * 0x00345678)) && (temp2 == 0))
1142                                 memsize = i;
1143                         else
1144                                 break;
1145                 }
1146         }
1147         DPRINTK("Second detect pass got %ld MB\n", memsize + 1);
1148
1149         PM3_WAIT(par, 1);
1150         PM3_WRITE_REG(par, PM3MemBypassWriteMask, tempBypass);
1151
1152         iounmap(screen_mem);
1153         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1154         memsize = 1048576 * (memsize + 1);
1155
1156         DPRINTK("Returning 0x%08lx bytes\n", memsize);
1157
1158         return memsize;
1159 }
1160
1161 static int __devinit pm3fb_probe(struct pci_dev *dev,
1162                                   const struct pci_device_id *ent)
1163 {
1164         struct fb_info *info;
1165         struct pm3_par *par;
1166         struct device* device = &dev->dev; /* for pci drivers */
1167         int err, retval = -ENXIO;
1168
1169         err = pci_enable_device(dev);
1170         if (err) {
1171                 printk(KERN_WARNING "pm3fb: Can't enable PCI dev: %d\n", err);
1172                 return err;
1173         }
1174         /*
1175          * Dynamically allocate info and par
1176          */
1177         info = framebuffer_alloc(sizeof(struct pm3_par), device);
1178
1179         if (!info)
1180                 return -ENOMEM;
1181         par = info->par;
1182
1183         /*
1184          * Here we set the screen_base to the virtual memory address
1185          * for the framebuffer.
1186          */
1187         pm3fb_fix.mmio_start = pci_resource_start(dev, 0);
1188         pm3fb_fix.mmio_len = PM3_REGS_SIZE;
1189
1190         /* Registers - request region and map it. */
1191         if (!request_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len,
1192                                  "pm3fb regbase")) {
1193                 printk(KERN_WARNING "pm3fb: Can't reserve regbase.\n");
1194                 goto err_exit_neither;
1195         }
1196         par->v_regs =
1197                 ioremap_nocache(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1198         if (!par->v_regs) {
1199                 printk(KERN_WARNING "pm3fb: Can't remap %s register area.\n",
1200                         pm3fb_fix.id);
1201                 release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1202                 goto err_exit_neither;
1203         }
1204
1205 #if defined(__BIG_ENDIAN)
1206         pm3fb_fix.mmio_start += PM3_REGS_SIZE;
1207         DPRINTK("Adjusting register base for big-endian.\n");
1208 #endif
1209         /* Linear frame buffer - request region and map it. */
1210         pm3fb_fix.smem_start = pci_resource_start(dev, 1);
1211         pm3fb_fix.smem_len = pm3fb_size_memory(par);
1212         if (!pm3fb_fix.smem_len)
1213         {
1214                 printk(KERN_WARNING "pm3fb: Can't find memory on board.\n");
1215                 goto err_exit_mmio;
1216         }
1217         if (!request_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len,
1218                                  "pm3fb smem")) {
1219                 printk(KERN_WARNING "pm3fb: Can't reserve smem.\n");
1220                 goto err_exit_mmio;
1221         }
1222         info->screen_base =
1223                 ioremap_nocache(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1224         if (!info->screen_base) {
1225                 printk(KERN_WARNING "pm3fb: Can't ioremap smem area.\n");
1226                 release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1227                 goto err_exit_mmio;
1228         }
1229         info->screen_size = pm3fb_fix.smem_len;
1230
1231         info->fbops = &pm3fb_ops;
1232
1233         par->video = PM3_READ_REG(par, PM3VideoControl);
1234
1235         info->fix = pm3fb_fix;
1236         info->pseudo_palette = par->palette;
1237         info->flags = FBINFO_DEFAULT |
1238 /*                      FBINFO_HWACCEL_YPAN |*/
1239                         FBINFO_HWACCEL_COPYAREA |
1240                         FBINFO_HWACCEL_IMAGEBLIT |
1241                         FBINFO_HWACCEL_FILLRECT;
1242
1243         /*
1244          * This should give a reasonable default video mode. The following is
1245          * done when we can set a video mode.
1246          */
1247         if (!mode_option)
1248                 mode_option = "640x480@60";
1249
1250         retval = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1251
1252         if (!retval || retval == 4) {
1253                 retval = -EINVAL;
1254                 goto err_exit_both;
1255         }
1256
1257         if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1258                 retval = -ENOMEM;
1259                 goto err_exit_both;
1260         }
1261
1262         /*
1263          * For drivers that can...
1264          */
1265         pm3fb_check_var(&info->var, info);
1266
1267         if (register_framebuffer(info) < 0) {
1268                 retval = -EINVAL;
1269                 goto err_exit_all;
1270         }
1271         printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
1272            info->fix.id);
1273         pci_set_drvdata(dev, info);
1274         return 0;
1275
1276  err_exit_all:
1277         fb_dealloc_cmap(&info->cmap);
1278  err_exit_both:
1279         iounmap(info->screen_base);
1280         release_mem_region(pm3fb_fix.smem_start, pm3fb_fix.smem_len);
1281  err_exit_mmio:
1282         iounmap(par->v_regs);
1283         release_mem_region(pm3fb_fix.mmio_start, pm3fb_fix.mmio_len);
1284  err_exit_neither:
1285         framebuffer_release(info);
1286         return retval;
1287 }
1288
1289         /*
1290          *  Cleanup
1291          */
1292 static void __devexit pm3fb_remove(struct pci_dev *dev)
1293 {
1294         struct fb_info *info = pci_get_drvdata(dev);
1295
1296         if (info) {
1297                 struct fb_fix_screeninfo *fix = &info->fix;
1298                 struct pm3_par *par = info->par;
1299
1300                 unregister_framebuffer(info);
1301                 fb_dealloc_cmap(&info->cmap);
1302
1303                 iounmap(info->screen_base);
1304                 release_mem_region(fix->smem_start, fix->smem_len);
1305                 iounmap(par->v_regs);
1306                 release_mem_region(fix->mmio_start, fix->mmio_len);
1307
1308                 pci_set_drvdata(dev, NULL);
1309                 framebuffer_release(info);
1310         }
1311 }
1312
1313 static struct pci_device_id pm3fb_id_table[] = {
1314         { PCI_VENDOR_ID_3DLABS, 0x0a,
1315           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1316         { 0, }
1317 };
1318
1319 /* For PCI drivers */
1320 static struct pci_driver pm3fb_driver = {
1321         .name =         "pm3fb",
1322         .id_table =     pm3fb_id_table,
1323         .probe =        pm3fb_probe,
1324         .remove =       __devexit_p(pm3fb_remove),
1325 };
1326
1327 MODULE_DEVICE_TABLE(pci, pm3fb_id_table);
1328
1329 static int __init pm3fb_init(void)
1330 {
1331 #ifndef MODULE
1332         if (fb_get_options("pm3fb", NULL))
1333                 return -ENODEV;
1334 #endif
1335         return pci_register_driver(&pm3fb_driver);
1336 }
1337
1338 static void __exit pm3fb_exit(void)
1339 {
1340         pci_unregister_driver(&pm3fb_driver);
1341 }
1342
1343 module_init(pm3fb_init);
1344 module_exit(pm3fb_exit);
1345
1346 MODULE_LICENSE("GPL");