2 * linux/drivers/video/s3c2410fb.c
3 * Copyright (c) Arnaud Patard, Ben Dooks
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
9 * S3C2410 LCD Controller Frame Buffer Driver
10 * based on skeletonfb.c, sa1100fb.c and others
13 * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
14 * - u32 state -> pm_message_t state
15 * - S3C2410_{VA,SZ}_LCD -> S3C24XX
17 * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
19 * - use readl/writel instead of __raw_writel/__raw_readl
21 * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
22 * - Added the possibility to set on or off the
24 * - Replaced 0 and 1 by on or off when reading the
27 * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
28 * - added non 16bpp modes
29 * - updated platform information for range of x/y/bpp
30 * - add code to ensure palette is written correctly
31 * - add pixel clock divisor control
33 * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
34 * - Removed the use of currcon as it no more exists
35 * - Added LCD power sysfs interface
37 * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
39 * - add suspend/resume support
40 * - s3c2410fb_setcolreg() not valid in >8bpp modes
41 * - removed last CONFIG_FB_S3C2410_FIXED
42 * - ensure lcd controller stopped before cleanup
43 * - added sysfs interface for backlight power
44 * - added mask for gpio configuration
45 * - ensured IRQs disabled during GPIO configuration
46 * - disable TPAL before enabling video
48 * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
49 * - Suppress command line options
51 * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
54 * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
55 * - Renamed from h1940fb.c to s3c2410fb.c
56 * - Add support for different devices
59 * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
60 * - added clock (de-)allocation code
61 * - added fixem fbmem option
63 * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
65 * - added a forgotten return in h1940fb_init
67 * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
68 * - code cleanup and extended debugging
70 * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
74 #include <linux/module.h>
75 #include <linux/kernel.h>
76 #include <linux/errno.h>
77 #include <linux/string.h>
79 #include <linux/slab.h>
80 #include <linux/delay.h>
82 #include <linux/init.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/interrupt.h>
85 #include <linux/platform_device.h>
86 #include <linux/clk.h>
89 #include <asm/div64.h>
91 #include <asm/mach/map.h>
92 #include <asm/arch/regs-lcd.h>
93 #include <asm/arch/regs-gpio.h>
94 #include <asm/arch/fb.h>
100 #include "s3c2410fb.h"
102 /* Debugging stuff */
103 #ifdef CONFIG_FB_S3C2410_DEBUG
104 static int debug = 1;
106 static int debug = 0;
109 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
111 /* useful functions */
113 /* s3c2410fb_set_lcdaddr
115 * initialise lcd controller address pointers
117 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
119 unsigned long saddr1, saddr2, saddr3;
120 struct s3c2410fb_info *fbi = info->par;
121 void __iomem *regs = fbi->io;
123 saddr1 = info->fix.smem_start >> 1;
124 saddr2 = info->fix.smem_start;
125 saddr2 += info->fix.line_length * info->var.yres;
128 saddr3 = S3C2410_OFFSIZE(0) |
129 S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
131 dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
132 dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
133 dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
135 writel(saddr1, regs + S3C2410_LCDSADDR1);
136 writel(saddr2, regs + S3C2410_LCDSADDR2);
137 writel(saddr3, regs + S3C2410_LCDSADDR3);
140 /* s3c2410fb_calc_pixclk()
142 * calculate divisor for clk->pixclk
144 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
145 unsigned long pixclk)
147 unsigned long clk = clk_get_rate(fbi->clk);
148 unsigned long long div;
150 /* pixclk is in picoseconds, our clock is in Hz
152 * Hz -> picoseconds is / 10^-12
155 div = (unsigned long long)clk * pixclk;
156 div >>= 12; /* div / 2^12 */
157 do_div(div, 625 * 625UL * 625); /* div / 5^12 */
159 dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
164 * s3c2410fb_check_var():
165 * Get the video params out of 'var'. If a value doesn't fit, round it up,
166 * if it's too big, return -EINVAL.
169 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
170 struct fb_info *info)
172 struct s3c2410fb_info *fbi = info->par;
173 struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
174 struct s3c2410fb_display *display = NULL;
177 dprintk("check_var(var=%p, info=%p)\n", var, info);
179 /* validate x/y resolution */
181 for (i = 0; i < mach_info->num_displays; i++)
182 if (var->yres == mach_info->displays[i].yres &&
183 var->xres == mach_info->displays[i].xres &&
184 var->bits_per_pixel == mach_info->displays[i].bpp) {
185 display = mach_info->displays + i;
190 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
191 var->xres, var->yres, var->bits_per_pixel);
195 /* it is always the size as the display */
196 var->xres_virtual = display->xres;
197 var->yres_virtual = display->yres;
198 var->height = display->height;
199 var->width = display->width;
201 /* copy lcd settings */
202 var->pixclock = display->pixclock;
203 var->left_margin = display->left_margin;
204 var->right_margin = display->right_margin;
205 var->upper_margin = display->upper_margin;
206 var->lower_margin = display->lower_margin;
207 var->vsync_len = display->vsync_len;
208 var->hsync_len = display->hsync_len;
210 fbi->regs.lcdcon5 = display->lcdcon5;
211 /* set display type */
212 fbi->regs.lcdcon1 = display->type;
214 var->transp.offset = 0;
215 var->transp.length = 0;
216 /* set r/g/b positions */
217 switch (var->bits_per_pixel) {
222 var->red.length = var->bits_per_pixel;
223 var->green = var->red;
224 var->blue = var->red;
227 if (display->type != S3C2410_LCDCON1_TFT) {
231 var->green.length = 3;
232 var->green.offset = 2;
233 var->blue.length = 2;
234 var->blue.offset = 0;
238 var->green = var->red;
239 var->blue = var->red;
246 var->green.length = 4;
247 var->green.offset = 4;
248 var->blue.length = 4;
249 var->blue.offset = 0;
254 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
255 /* 16 bpp, 565 format */
256 var->red.offset = 11;
257 var->green.offset = 5;
258 var->blue.offset = 0;
260 var->green.length = 6;
261 var->blue.length = 5;
263 /* 16 bpp, 5551 format */
264 var->red.offset = 11;
265 var->green.offset = 6;
266 var->blue.offset = 1;
268 var->green.length = 5;
269 var->blue.length = 5;
273 /* 24 bpp 888 and 8 dummy */
275 var->red.offset = 16;
276 var->green.length = 8;
277 var->green.offset = 8;
278 var->blue.length = 8;
279 var->blue.offset = 0;
285 /* s3c2410fb_calculate_stn_lcd_regs
287 * calculate register values from var settings
289 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
290 struct s3c2410fb_hw *regs)
292 const struct s3c2410fb_info *fbi = info->par;
293 const struct fb_var_screeninfo *var = &info->var;
294 int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
295 int hs = var->xres >> 2;
296 unsigned wdly = (var->left_margin >> 4) - 1;
297 unsigned wlh = (var->hsync_len >> 4) - 1;
299 if (type != S3C2410_LCDCON1_STN4)
302 switch (var->bits_per_pixel) {
304 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
307 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
310 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
313 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
317 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
322 /* invalid pixel depth */
323 dev_err(fbi->dev, "invalid bpp %d\n",
324 var->bits_per_pixel);
326 /* update X/Y info */
327 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
328 var->left_margin, var->right_margin, var->hsync_len);
330 regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
338 regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
339 S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
340 S3C2410_LCDCON3_HOZVAL(hs - 1);
342 regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
345 /* s3c2410fb_calculate_tft_lcd_regs
347 * calculate register values from var settings
349 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
350 struct s3c2410fb_hw *regs)
352 const struct s3c2410fb_info *fbi = info->par;
353 const struct fb_var_screeninfo *var = &info->var;
355 switch (var->bits_per_pixel) {
357 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
360 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
363 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
366 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
367 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
368 S3C2410_LCDCON5_FRM565;
369 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
372 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
373 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
374 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
377 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
378 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
379 S3C2410_LCDCON5_HWSWP |
380 S3C2410_LCDCON5_BPP24BL);
383 /* invalid pixel depth */
384 dev_err(fbi->dev, "invalid bpp %d\n",
385 var->bits_per_pixel);
387 /* update X/Y info */
388 dprintk("setting vert: up=%d, low=%d, sync=%d\n",
389 var->upper_margin, var->lower_margin, var->vsync_len);
391 dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
392 var->left_margin, var->right_margin, var->hsync_len);
394 regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
395 S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
396 S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
397 S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
399 regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
400 S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
401 S3C2410_LCDCON3_HOZVAL(var->xres - 1);
403 regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
406 /* s3c2410fb_activate_var
408 * activate (set) the controller from the given framebuffer
411 static void s3c2410fb_activate_var(struct fb_info *info)
413 struct s3c2410fb_info *fbi = info->par;
414 void __iomem *regs = fbi->io;
415 int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
416 struct fb_var_screeninfo *var = &info->var;
417 int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
419 dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
420 dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
421 dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
423 if (type == S3C2410_LCDCON1_TFT) {
424 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
429 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
434 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
436 /* write new registers */
438 dprintk("new register set:\n");
439 dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
440 dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
441 dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
442 dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
443 dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
445 writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
446 regs + S3C2410_LCDCON1);
447 writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
448 writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
449 writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
450 writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
452 /* set lcd address pointers */
453 s3c2410fb_set_lcdaddr(info);
455 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
456 writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
460 * s3c2410fb_set_par - Alters the hardware state.
461 * @info: frame buffer structure that represents a single frame buffer
464 static int s3c2410fb_set_par(struct fb_info *info)
466 struct fb_var_screeninfo *var = &info->var;
468 switch (var->bits_per_pixel) {
472 info->fix.visual = FB_VISUAL_TRUECOLOR;
475 info->fix.visual = FB_VISUAL_MONO01;
478 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
482 info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
484 /* activate this new configuration */
486 s3c2410fb_activate_var(info);
490 static void schedule_palette_update(struct s3c2410fb_info *fbi,
491 unsigned int regno, unsigned int val)
495 void __iomem *regs = fbi->io;
497 local_irq_save(flags);
499 fbi->palette_buffer[regno] = val;
501 if (!fbi->palette_ready) {
502 fbi->palette_ready = 1;
505 irqen = readl(regs + S3C2410_LCDINTMSK);
506 irqen &= ~S3C2410_LCDINT_FRSYNC;
507 writel(irqen, regs + S3C2410_LCDINTMSK);
510 local_irq_restore(flags);
514 static inline unsigned int chan_to_field(unsigned int chan,
515 struct fb_bitfield *bf)
518 chan >>= 16 - bf->length;
519 return chan << bf->offset;
522 static int s3c2410fb_setcolreg(unsigned regno,
523 unsigned red, unsigned green, unsigned blue,
524 unsigned transp, struct fb_info *info)
526 struct s3c2410fb_info *fbi = info->par;
527 void __iomem *regs = fbi->io;
530 /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
531 regno, red, green, blue); */
533 switch (info->fix.visual) {
534 case FB_VISUAL_TRUECOLOR:
535 /* true-colour, use pseudo-palette */
538 u32 *pal = info->pseudo_palette;
540 val = chan_to_field(red, &info->var.red);
541 val |= chan_to_field(green, &info->var.green);
542 val |= chan_to_field(blue, &info->var.blue);
548 case FB_VISUAL_PSEUDOCOLOR:
550 /* currently assume RGB 5-6-5 mode */
552 val = (red >> 0) & 0xf800;
553 val |= (green >> 5) & 0x07e0;
554 val |= (blue >> 11) & 0x001f;
556 writel(val, regs + S3C2410_TFTPAL(regno));
557 schedule_palette_update(fbi, regno, val);
563 return 1; /* unknown type */
571 * @blank_mode: the blank mode we want.
572 * @info: frame buffer structure that represents a single frame buffer
574 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
575 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
576 * video mode which doesn't support it. Implements VESA suspend
577 * and powerdown modes on hardware that supports disabling hsync/vsync:
578 * blank_mode == 2: suspend vsync
579 * blank_mode == 3: suspend hsync
580 * blank_mode == 4: powerdown
582 * Returns negative errno on error, or zero on success.
585 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
587 struct s3c2410fb_info *fbi = info->par;
588 void __iomem *regs = fbi->io;
590 dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
592 if (blank_mode == FB_BLANK_UNBLANK)
593 writel(0x0, regs + S3C2410_TPAL);
595 dprintk("setting TPAL to output 0x000000\n");
596 writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
602 static int s3c2410fb_debug_show(struct device *dev,
603 struct device_attribute *attr, char *buf)
605 return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
608 static int s3c2410fb_debug_store(struct device *dev,
609 struct device_attribute *attr,
610 const char *buf, size_t len)
615 if (strnicmp(buf, "on", 2) == 0 ||
616 strnicmp(buf, "1", 1) == 0) {
618 printk(KERN_DEBUG "s3c2410fb: Debug On");
619 } else if (strnicmp(buf, "off", 3) == 0 ||
620 strnicmp(buf, "0", 1) == 0) {
622 printk(KERN_DEBUG "s3c2410fb: Debug Off");
630 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
632 static struct fb_ops s3c2410fb_ops = {
633 .owner = THIS_MODULE,
634 .fb_check_var = s3c2410fb_check_var,
635 .fb_set_par = s3c2410fb_set_par,
636 .fb_blank = s3c2410fb_blank,
637 .fb_setcolreg = s3c2410fb_setcolreg,
638 .fb_fillrect = cfb_fillrect,
639 .fb_copyarea = cfb_copyarea,
640 .fb_imageblit = cfb_imageblit,
644 * s3c2410fb_map_video_memory():
645 * Allocates the DRAM memory for the frame buffer. This buffer is
646 * remapped into a non-cached, non-buffered, memory region to
647 * allow palette and pixel writes to occur without flushing the
648 * cache. Once this area is remapped, all virtual memory
649 * access to the video memory should occur at the new region.
651 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
653 struct s3c2410fb_info *fbi = info->par;
655 unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
657 dprintk("map_video_memory(fbi=%p)\n", fbi);
659 info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
660 &map_dma, GFP_KERNEL);
662 if (info->screen_base) {
663 /* prevent initial garbage on screen */
664 dprintk("map_video_memory: clear %p:%08x\n",
665 info->screen_base, map_size);
666 memset(info->screen_base, 0xf0, map_size);
668 info->fix.smem_start = map_dma;
670 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
671 info->fix.smem_start, info->screen_base, map_size);
674 return info->screen_base ? 0 : -ENOMEM;
677 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
679 struct s3c2410fb_info *fbi = info->par;
681 dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
682 info->screen_base, info->fix.smem_start);
685 static inline void modify_gpio(void __iomem *reg,
686 unsigned long set, unsigned long mask)
690 tmp = readl(reg) & ~mask;
691 writel(tmp | set, reg);
695 * s3c2410fb_init_registers - Initialise all LCD-related registers
697 static int s3c2410fb_init_registers(struct fb_info *info)
699 struct s3c2410fb_info *fbi = info->par;
700 struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
702 void __iomem *regs = fbi->io;
704 /* Initialise LCD with values from haret */
706 local_irq_save(flags);
708 /* modify the gpio(s) with interrupts set (bjd) */
710 modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
711 modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
712 modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
713 modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
715 local_irq_restore(flags);
717 dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
718 writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
720 dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
722 /* ensure temporary palette disabled */
723 writel(0x00, regs + S3C2410_TPAL);
728 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
731 void __iomem *regs = fbi->io;
733 fbi->palette_ready = 0;
735 for (i = 0; i < 256; i++) {
736 unsigned long ent = fbi->palette_buffer[i];
737 if (ent == PALETTE_BUFF_CLEAR)
740 writel(ent, regs + S3C2410_TFTPAL(i));
742 /* it seems the only way to know exactly
743 * if the palette wrote ok, is to check
744 * to see if the value verifies ok
747 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
748 fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
750 fbi->palette_ready = 1; /* retry */
754 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
756 struct s3c2410fb_info *fbi = dev_id;
757 void __iomem *regs = fbi->io;
758 unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
760 if (lcdirq & S3C2410_LCDINT_FRSYNC) {
761 if (fbi->palette_ready)
762 s3c2410fb_write_palette(fbi);
764 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
765 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
771 static char driver_name[] = "s3c2410fb";
773 static int __init s3c2410fb_probe(struct platform_device *pdev)
775 struct s3c2410fb_info *info;
776 struct s3c2410fb_display *display;
777 struct fb_info *fbinfo;
778 struct s3c2410fb_mach_info *mach_info;
779 struct resource *res;
786 mach_info = pdev->dev.platform_data;
787 if (mach_info == NULL) {
789 "no platform data for lcd, cannot attach\n");
793 display = mach_info->displays + mach_info->default_display;
795 irq = platform_get_irq(pdev, 0);
797 dev_err(&pdev->dev, "no irq for device\n");
801 fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
805 platform_set_drvdata(pdev, fbinfo);
808 info->dev = &pdev->dev;
810 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
812 dev_err(&pdev->dev, "failed to get memory registers\n");
817 size = (res->end - res->start) + 1;
818 info->mem = request_mem_region(res->start, size, pdev->name);
819 if (info->mem == NULL) {
820 dev_err(&pdev->dev, "failed to get memory region\n");
825 info->io = ioremap(res->start, size);
826 if (info->io == NULL) {
827 dev_err(&pdev->dev, "ioremap() of registers failed\n");
832 dprintk("devinit\n");
834 strcpy(fbinfo->fix.id, driver_name);
837 lcdcon1 = readl(info->io + S3C2410_LCDCON1);
838 writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
840 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
841 fbinfo->fix.type_aux = 0;
842 fbinfo->fix.xpanstep = 0;
843 fbinfo->fix.ypanstep = 0;
844 fbinfo->fix.ywrapstep = 0;
845 fbinfo->fix.accel = FB_ACCEL_NONE;
847 fbinfo->var.nonstd = 0;
848 fbinfo->var.activate = FB_ACTIVATE_NOW;
849 fbinfo->var.accel_flags = 0;
850 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
852 fbinfo->fbops = &s3c2410fb_ops;
853 fbinfo->flags = FBINFO_FLAG_DEFAULT;
854 fbinfo->pseudo_palette = &info->pseudo_pal;
856 for (i = 0; i < 256; i++)
857 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
859 ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
861 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
866 info->clk = clk_get(NULL, "lcd");
867 if (!info->clk || IS_ERR(info->clk)) {
868 printk(KERN_ERR "failed to get lcd clock source\n");
873 clk_enable(info->clk);
874 dprintk("got and enabled clock\n");
878 /* find maximum required memory size for display */
879 for (i = 0; i < mach_info->num_displays; i++) {
880 unsigned long smem_len = mach_info->displays[i].xres;
882 smem_len *= mach_info->displays[i].yres;
883 smem_len *= mach_info->displays[i].bpp;
885 if (fbinfo->fix.smem_len < smem_len)
886 fbinfo->fix.smem_len = smem_len;
889 /* Initialize video memory */
890 ret = s3c2410fb_map_video_memory(fbinfo);
892 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
897 dprintk("got video memory\n");
899 fbinfo->var.xres = display->xres;
900 fbinfo->var.yres = display->yres;
901 fbinfo->var.bits_per_pixel = display->bpp;
903 s3c2410fb_init_registers(fbinfo);
905 s3c2410fb_check_var(&fbinfo->var, fbinfo);
907 ret = register_framebuffer(fbinfo);
909 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
911 goto free_video_memory;
914 /* create device files */
915 device_create_file(&pdev->dev, &dev_attr_debug);
917 printk(KERN_INFO "fb%d: %s frame buffer device\n",
918 fbinfo->node, fbinfo->fix.id);
923 s3c2410fb_unmap_video_memory(fbinfo);
925 clk_disable(info->clk);
932 release_resource(info->mem);
935 platform_set_drvdata(pdev, NULL);
936 framebuffer_release(fbinfo);
940 /* s3c2410fb_stop_lcd
942 * shutdown the lcd controller
944 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
948 local_irq_save(flags);
950 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
951 writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
953 local_irq_restore(flags);
959 static int s3c2410fb_remove(struct platform_device *pdev)
961 struct fb_info *fbinfo = platform_get_drvdata(pdev);
962 struct s3c2410fb_info *info = fbinfo->par;
965 unregister_framebuffer(fbinfo);
967 s3c2410fb_stop_lcd(info);
970 s3c2410fb_unmap_video_memory(fbinfo);
973 clk_disable(info->clk);
978 irq = platform_get_irq(pdev, 0);
983 release_resource(info->mem);
986 platform_set_drvdata(pdev, NULL);
987 framebuffer_release(fbinfo);
994 /* suspend and resume support for the lcd controller */
995 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
997 struct fb_info *fbinfo = platform_get_drvdata(dev);
998 struct s3c2410fb_info *info = fbinfo->par;
1000 s3c2410fb_stop_lcd(info);
1002 /* sleep before disabling the clock, we need to ensure
1003 * the LCD DMA engine is not going to get back on the bus
1004 * before the clock goes off again (bjd) */
1007 clk_disable(info->clk);
1012 static int s3c2410fb_resume(struct platform_device *dev)
1014 struct fb_info *fbinfo = platform_get_drvdata(dev);
1015 struct s3c2410fb_info *info = fbinfo->par;
1017 clk_enable(info->clk);
1020 s3c2410fb_init_registers(info);
1026 #define s3c2410fb_suspend NULL
1027 #define s3c2410fb_resume NULL
1030 static struct platform_driver s3c2410fb_driver = {
1031 .probe = s3c2410fb_probe,
1032 .remove = s3c2410fb_remove,
1033 .suspend = s3c2410fb_suspend,
1034 .resume = s3c2410fb_resume,
1036 .name = "s3c2410-lcd",
1037 .owner = THIS_MODULE,
1041 int __init s3c2410fb_init(void)
1043 return platform_driver_register(&s3c2410fb_driver);
1046 static void __exit s3c2410fb_cleanup(void)
1048 platform_driver_unregister(&s3c2410fb_driver);
1051 module_init(s3c2410fb_init);
1052 module_exit(s3c2410fb_cleanup);
1054 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1055 "Ben Dooks <ben-linux@fluff.org>");
1056 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1057 MODULE_LICENSE("GPL");