2 * linux/drivers/video/sgivwfb.c -- SGI DBE frame buffer device
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Jeffrey Newquist, newquist@engr.sgi.som
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/ioport.h>
21 #include <linux/platform_device.h>
26 #include <setup_arch.h>
28 #define INCLUDE_TIMING_TABLE_DATA
29 #define DBE_REG_BASE par->regs
30 #include <video/sgivw.h>
38 #define FLATPANEL_SGI_1600SW 5
41 * RAM we reserve for the frame buffer. This defines the maximum screen
44 * The default can be overridden if the driver is compiled as a module
50 static int flatpanel_id = -1;
52 static struct fb_fix_screeninfo sgivwfb_fix __initdata = {
53 .id = "SGI Vis WS FB",
54 .type = FB_TYPE_PACKED_PIXELS,
55 .visual = FB_VISUAL_PSEUDOCOLOR,
56 .mmio_start = DBE_REG_PHYS,
57 .mmio_len = DBE_REG_SIZE,
58 .accel = FB_ACCEL_NONE,
62 static struct fb_var_screeninfo sgivwfb_var __initdata = {
81 .vmode = FB_VMODE_NONINTERLACED
84 static struct fb_var_screeninfo sgivwfb_var1600sw __initdata = {
85 /* 1600x1024, 8 bpp */
103 .vmode = FB_VMODE_NONINTERLACED
107 * Interface used by the world
109 int sgivwfb_init(void);
111 static int sgivwfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
112 static int sgivwfb_set_par(struct fb_info *info);
113 static int sgivwfb_setcolreg(u_int regno, u_int red, u_int green,
114 u_int blue, u_int transp,
115 struct fb_info *info);
116 static int sgivwfb_mmap(struct fb_info *info,
117 struct vm_area_struct *vma);
119 static struct fb_ops sgivwfb_ops = {
120 .owner = THIS_MODULE,
121 .fb_check_var = sgivwfb_check_var,
122 .fb_set_par = sgivwfb_set_par,
123 .fb_setcolreg = sgivwfb_setcolreg,
124 .fb_fillrect = cfb_fillrect,
125 .fb_copyarea = cfb_copyarea,
126 .fb_imageblit = cfb_imageblit,
127 .fb_mmap = sgivwfb_mmap,
133 static unsigned long bytes_per_pixel(int bpp)
143 printk(KERN_INFO "sgivwfb: unsupported bpp %d\n", bpp);
148 static unsigned long get_line_length(int xres_virtual, int bpp)
150 return (xres_virtual * bytes_per_pixel(bpp));
154 * Function: dbe_TurnOffDma
156 * Description: This should turn off the monitor and dbe. This is used
157 * when switching between the serial console and the graphics
161 static void dbe_TurnOffDma(struct sgivw_par *par)
163 unsigned int readVal;
166 // Check to see if things are already turned off:
167 // 1) Check to see if dbe is not using the internal dotclock.
168 // 2) Check to see if the xy counter in dbe is already off.
170 DBE_GETREG(ctrlstat, readVal);
171 if (GET_DBE_FIELD(CTRLSTAT, PCLKSEL, readVal) < 2)
174 DBE_GETREG(vt_xy, readVal);
175 if (GET_DBE_FIELD(VT_XY, VT_FREEZE, readVal) == 1)
178 // Otherwise, turn off dbe
180 DBE_GETREG(ovr_control, readVal);
181 SET_DBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, readVal, 0);
182 DBE_SETREG(ovr_control, readVal);
184 DBE_GETREG(frm_control, readVal);
185 SET_DBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, readVal, 0);
186 DBE_SETREG(frm_control, readVal);
188 DBE_GETREG(did_control, readVal);
189 SET_DBE_FIELD(DID_CONTROL, DID_DMA_ENABLE, readVal, 0);
190 DBE_SETREG(did_control, readVal);
195 // This was necessary for GBE--we had to wait through two
196 // vertical retrace periods before the pixel DMA was
197 // turned off for sure. I've left this in for now, in
198 // case dbe needs it.
200 for (i = 0; i < 10000; i++) {
201 DBE_GETREG(frm_inhwctrl, readVal);
202 if (GET_DBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, readVal) ==
206 DBE_GETREG(ovr_inhwctrl, readVal);
208 (OVR_INHWCTRL, OVR_DMA_ENABLE, readVal) == 0)
211 DBE_GETREG(did_inhwctrl, readVal);
213 (DID_INHWCTRL, DID_DMA_ENABLE,
224 * Set the User Defined Part of the Display. Again if par use it to get
227 static int sgivwfb_check_var(struct fb_var_screeninfo *var,
228 struct fb_info *info)
230 struct sgivw_par *par = (struct sgivw_par *)info->par;
231 struct dbe_timing_info *timing;
238 * FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
239 * as FB_VMODE_SMOOTH_XPAN is only used internally
242 if (var->vmode & FB_VMODE_CONUPDATE) {
243 var->vmode |= FB_VMODE_YWRAP;
244 var->xoffset = info->var.xoffset;
245 var->yoffset = info->var.yoffset;
248 /* XXX FIXME - forcing var's */
252 /* Limit bpp to 8, 16, and 32 */
253 if (var->bits_per_pixel <= 8)
254 var->bits_per_pixel = 8;
255 else if (var->bits_per_pixel <= 16)
256 var->bits_per_pixel = 16;
257 else if (var->bits_per_pixel <= 32)
258 var->bits_per_pixel = 32;
262 var->grayscale = 0; /* No grayscale for now */
264 /* determine valid resolution and timing */
265 for (min_mode = 0; min_mode < DBE_VT_SIZE; min_mode++) {
266 if (dbeVTimings[min_mode].width >= var->xres &&
267 dbeVTimings[min_mode].height >= var->yres)
271 if (min_mode == DBE_VT_SIZE)
272 return -EINVAL; /* Resolution to high */
274 /* XXX FIXME - should try to pick best refresh rate */
275 /* for now, pick closest dot-clock within 3MHz */
276 req_dot = PICOS2KHZ(var->pixclock);
277 printk(KERN_INFO "sgivwfb: requested pixclock=%d ps (%d KHz)\n",
278 var->pixclock, req_dot);
279 test_mode = min_mode;
280 while (dbeVTimings[min_mode].width == dbeVTimings[test_mode].width) {
281 if (dbeVTimings[test_mode].cfreq + 3000 > req_dot)
285 if (dbeVTimings[min_mode].width != dbeVTimings[test_mode].width)
287 min_mode = test_mode;
288 timing = &dbeVTimings[min_mode];
289 printk(KERN_INFO "sgivwfb: granted dot-clock=%d KHz\n", timing->cfreq);
291 /* Adjust virtual resolution, if necessary */
292 if (var->xres > var->xres_virtual || (!ywrap && !ypan))
293 var->xres_virtual = var->xres;
294 if (var->yres > var->yres_virtual || (!ywrap && !ypan))
295 var->yres_virtual = var->yres;
300 line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
301 if (line_length * var->yres_virtual > sgivwfb_mem_size)
302 return -ENOMEM; /* Virtual resolution to high */
304 info->fix.line_length = line_length;
306 switch (var->bits_per_pixel) {
310 var->green.offset = 0;
311 var->green.length = 8;
312 var->blue.offset = 0;
313 var->blue.length = 8;
314 var->transp.offset = 0;
315 var->transp.length = 0;
317 case 16: /* RGBA 5551 */
318 var->red.offset = 11;
320 var->green.offset = 6;
321 var->green.length = 5;
322 var->blue.offset = 1;
323 var->blue.length = 5;
324 var->transp.offset = 0;
325 var->transp.length = 0;
327 case 32: /* RGB 8888 */
330 var->green.offset = 8;
331 var->green.length = 8;
332 var->blue.offset = 16;
333 var->blue.length = 8;
334 var->transp.offset = 24;
335 var->transp.length = 8;
338 var->red.msb_right = 0;
339 var->green.msb_right = 0;
340 var->blue.msb_right = 0;
341 var->transp.msb_right = 0;
343 /* set video timing information */
344 var->pixclock = KHZ2PICOS(timing->cfreq);
345 var->left_margin = timing->htotal - timing->hsync_end;
346 var->right_margin = timing->hsync_start - timing->width;
347 var->upper_margin = timing->vtotal - timing->vsync_end;
348 var->lower_margin = timing->vsync_start - timing->height;
349 var->hsync_len = timing->hsync_end - timing->hsync_start;
350 var->vsync_len = timing->vsync_end - timing->vsync_start;
352 /* Ouch. This breaks the rules but timing_num is only important if you
353 * change a video mode */
354 par->timing_num = min_mode;
356 printk(KERN_INFO "sgivwfb: new video mode xres=%d yres=%d bpp=%d\n",
357 var->xres, var->yres, var->bits_per_pixel);
358 printk(KERN_INFO " vxres=%d vyres=%d\n", var->xres_virtual,
364 * Setup flatpanel related registers.
366 static void sgivwfb_setup_flatpanel(struct sgivw_par *par, struct dbe_timing_info *currentTiming)
368 int fp_wid, fp_hgt, fp_vbs, fp_vbe;
371 SET_DBE_FIELD(VT_FLAGS, HDRV_INVERT, outputVal,
372 (currentTiming->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
373 SET_DBE_FIELD(VT_FLAGS, VDRV_INVERT, outputVal,
374 (currentTiming->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
375 DBE_SETREG(vt_flags, outputVal);
377 /* Turn on the flat panel */
378 switch (flatpanel_id) {
379 case FLATPANEL_SGI_1600SW:
384 currentTiming->pll_m = 4;
385 currentTiming->pll_n = 1;
386 currentTiming->pll_p = 0;
389 fp_wid = fp_hgt = fp_vbs = fp_vbe = 0xfff;
393 SET_DBE_FIELD(FP_DE, FP_DE_ON, outputVal, fp_vbs);
394 SET_DBE_FIELD(FP_DE, FP_DE_OFF, outputVal, fp_vbe);
395 DBE_SETREG(fp_de, outputVal);
397 SET_DBE_FIELD(FP_HDRV, FP_HDRV_OFF, outputVal, fp_wid);
398 DBE_SETREG(fp_hdrv, outputVal);
400 SET_DBE_FIELD(FP_VDRV, FP_VDRV_ON, outputVal, 1);
401 SET_DBE_FIELD(FP_VDRV, FP_VDRV_OFF, outputVal, fp_hgt + 1);
402 DBE_SETREG(fp_vdrv, outputVal);
406 * Set the hardware according to 'par'.
408 static int sgivwfb_set_par(struct fb_info *info)
410 struct sgivw_par *par = info->par;
411 int i, j, htmp, temp;
412 u32 readVal, outputVal;
413 int wholeTilesX, maxPixelsPerTileX;
414 int frmWrite1, frmWrite2, frmWrite3b;
415 struct dbe_timing_info *currentTiming; /* Current Video Timing */
416 int xpmax, ypmax; // Monitor resolution
417 int bytesPerPixel; // Bytes per pixel
419 currentTiming = &dbeVTimings[par->timing_num];
420 bytesPerPixel = bytes_per_pixel(info->var.bits_per_pixel);
421 xpmax = currentTiming->width;
422 ypmax = currentTiming->height;
424 /* dbe_InitGraphicsBase(); */
425 /* Turn on dotclock PLL */
426 DBE_SETREG(ctrlstat, 0x20000000);
430 /* dbe_CalculateScreenParams(); */
431 maxPixelsPerTileX = 512 / bytesPerPixel;
432 wholeTilesX = xpmax / maxPixelsPerTileX;
433 if (wholeTilesX * maxPixelsPerTileX < xpmax)
436 printk(KERN_DEBUG "sgivwfb: pixPerTile=%d wholeTilesX=%d\n",
437 maxPixelsPerTileX, wholeTilesX);
439 /* dbe_InitGammaMap(); */
442 for (i = 0; i < 256; i++) {
443 DBE_ISETREG(gmap, i, (i << 24) | (i << 16) | (i << 8));
447 DBE_GETREG(vt_xy, readVal);
448 if (GET_DBE_FIELD(VT_XY, VT_FREEZE, readVal) == 1) {
449 DBE_SETREG(vt_xy, 0x00000000);
455 for (i = 0; i < 256; i++) {
456 for (j = 0; j < 100; j++) {
457 DBE_GETREG(cm_fifo, readVal);
458 if (readVal != 0x00000000)
464 // DBE_ISETREG(cmap, i, 0x00000000);
465 DBE_ISETREG(cmap, i, (i << 8) | (i << 16) | (i << 24));
468 /* dbe_InitFramebuffer(); */
470 SET_DBE_FIELD(FRM_SIZE_TILE, FRM_WIDTH_TILE, frmWrite1,
472 SET_DBE_FIELD(FRM_SIZE_TILE, FRM_RHS, frmWrite1, 0);
474 switch (bytesPerPixel) {
476 SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
480 SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
484 SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
490 SET_DBE_FIELD(FRM_SIZE_PIXEL, FB_HEIGHT_PIX, frmWrite2, ypmax);
492 // Tell dbe about the framebuffer location and type
493 // XXX What format is the FRM_TILE_PTR?? 64K aligned address?
495 SET_DBE_FIELD(FRM_CONTROL, FRM_TILE_PTR, frmWrite3b,
496 sgivwfb_mem_phys >> 9);
497 SET_DBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, frmWrite3b, 1);
498 SET_DBE_FIELD(FRM_CONTROL, FRM_LINEAR, frmWrite3b, 1);
500 /* Initialize DIDs */
503 switch (bytesPerPixel) {
505 SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_I8);
508 SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_RGBA5);
511 SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_RGB8);
514 SET_DBE_FIELD(WID, BUF, outputVal, DBE_BMODE_BOTH);
516 for (i = 0; i < 32; i++) {
517 DBE_ISETREG(mode_regs, i, outputVal);
520 /* dbe_InitTiming(); */
521 DBE_SETREG(vt_intr01, 0xffffffff);
522 DBE_SETREG(vt_intr23, 0xffffffff);
524 DBE_GETREG(dotclock, readVal);
525 DBE_SETREG(dotclock, readVal & 0xffff);
527 DBE_SETREG(vt_xymax, 0x00000000);
529 SET_DBE_FIELD(VT_VSYNC, VT_VSYNC_ON, outputVal,
530 currentTiming->vsync_start);
531 SET_DBE_FIELD(VT_VSYNC, VT_VSYNC_OFF, outputVal,
532 currentTiming->vsync_end);
533 DBE_SETREG(vt_vsync, outputVal);
535 SET_DBE_FIELD(VT_HSYNC, VT_HSYNC_ON, outputVal,
536 currentTiming->hsync_start);
537 SET_DBE_FIELD(VT_HSYNC, VT_HSYNC_OFF, outputVal,
538 currentTiming->hsync_end);
539 DBE_SETREG(vt_hsync, outputVal);
541 SET_DBE_FIELD(VT_VBLANK, VT_VBLANK_ON, outputVal,
542 currentTiming->vblank_start);
543 SET_DBE_FIELD(VT_VBLANK, VT_VBLANK_OFF, outputVal,
544 currentTiming->vblank_end);
545 DBE_SETREG(vt_vblank, outputVal);
547 SET_DBE_FIELD(VT_HBLANK, VT_HBLANK_ON, outputVal,
548 currentTiming->hblank_start);
549 SET_DBE_FIELD(VT_HBLANK, VT_HBLANK_OFF, outputVal,
550 currentTiming->hblank_end - 3);
551 DBE_SETREG(vt_hblank, outputVal);
553 SET_DBE_FIELD(VT_VCMAP, VT_VCMAP_ON, outputVal,
554 currentTiming->vblank_start);
555 SET_DBE_FIELD(VT_VCMAP, VT_VCMAP_OFF, outputVal,
556 currentTiming->vblank_end);
557 DBE_SETREG(vt_vcmap, outputVal);
559 SET_DBE_FIELD(VT_HCMAP, VT_HCMAP_ON, outputVal,
560 currentTiming->hblank_start);
561 SET_DBE_FIELD(VT_HCMAP, VT_HCMAP_OFF, outputVal,
562 currentTiming->hblank_end - 3);
563 DBE_SETREG(vt_hcmap, outputVal);
565 if (flatpanel_id != -1)
566 sgivwfb_setup_flatpanel(par, currentTiming);
569 temp = currentTiming->vblank_start - currentTiming->vblank_end - 1;
573 SET_DBE_FIELD(DID_START_XY, DID_STARTY, outputVal, (u32) temp);
574 if (currentTiming->hblank_end >= 20)
575 SET_DBE_FIELD(DID_START_XY, DID_STARTX, outputVal,
576 currentTiming->hblank_end - 20);
578 SET_DBE_FIELD(DID_START_XY, DID_STARTX, outputVal,
579 currentTiming->htotal - (20 -
582 DBE_SETREG(did_start_xy, outputVal);
585 SET_DBE_FIELD(CRS_START_XY, CRS_STARTY, outputVal,
587 if (currentTiming->hblank_end >= DBE_CRS_MAGIC)
588 SET_DBE_FIELD(CRS_START_XY, CRS_STARTX, outputVal,
589 currentTiming->hblank_end - DBE_CRS_MAGIC);
591 SET_DBE_FIELD(CRS_START_XY, CRS_STARTX, outputVal,
592 currentTiming->htotal - (DBE_CRS_MAGIC -
595 DBE_SETREG(crs_start_xy, outputVal);
598 SET_DBE_FIELD(VC_START_XY, VC_STARTY, outputVal, (u32) temp);
599 SET_DBE_FIELD(VC_START_XY, VC_STARTX, outputVal,
600 currentTiming->hblank_end - 4);
601 DBE_SETREG(vc_start_xy, outputVal);
603 DBE_SETREG(frm_size_tile, frmWrite1);
604 DBE_SETREG(frm_size_pixel, frmWrite2);
607 SET_DBE_FIELD(DOTCLK, M, outputVal, currentTiming->pll_m - 1);
608 SET_DBE_FIELD(DOTCLK, N, outputVal, currentTiming->pll_n - 1);
609 SET_DBE_FIELD(DOTCLK, P, outputVal, currentTiming->pll_p);
610 SET_DBE_FIELD(DOTCLK, RUN, outputVal, 1);
611 DBE_SETREG(dotclock, outputVal);
615 DBE_SETREG(vt_vpixen, 0xffffff);
616 DBE_SETREG(vt_hpixen, 0xffffff);
619 SET_DBE_FIELD(VT_XYMAX, VT_MAXX, outputVal, currentTiming->htotal);
620 SET_DBE_FIELD(VT_XYMAX, VT_MAXY, outputVal, currentTiming->vtotal);
621 DBE_SETREG(vt_xymax, outputVal);
623 outputVal = frmWrite1;
624 SET_DBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, outputVal, 1);
625 DBE_SETREG(frm_size_tile, outputVal);
626 DBE_SETREG(frm_size_tile, frmWrite1);
629 SET_DBE_FIELD(OVR_WIDTH_TILE, OVR_FIFO_RESET, outputVal, 1);
630 DBE_SETREG(ovr_width_tile, outputVal);
631 DBE_SETREG(ovr_width_tile, 0);
633 DBE_SETREG(frm_control, frmWrite3b);
634 DBE_SETREG(did_control, 0);
636 // Wait for dbe to take frame settings
637 for (i = 0; i < 100000; i++) {
638 DBE_GETREG(frm_inhwctrl, readVal);
639 if (GET_DBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, readVal) !=
648 "sgivwfb: timeout waiting for frame DMA enable.\n");
651 htmp = currentTiming->hblank_end - 19;
653 htmp += currentTiming->htotal; /* allow blank to wrap around */
654 SET_DBE_FIELD(VT_HPIXEN, VT_HPIXEN_ON, outputVal, htmp);
655 SET_DBE_FIELD(VT_HPIXEN, VT_HPIXEN_OFF, outputVal,
656 ((htmp + currentTiming->width -
657 2) % currentTiming->htotal));
658 DBE_SETREG(vt_hpixen, outputVal);
661 SET_DBE_FIELD(VT_VPIXEN, VT_VPIXEN_OFF, outputVal,
662 currentTiming->vblank_start);
663 SET_DBE_FIELD(VT_VPIXEN, VT_VPIXEN_ON, outputVal,
664 currentTiming->vblank_end);
665 DBE_SETREG(vt_vpixen, outputVal);
667 // Turn off mouse cursor
668 par->regs->crs_ctl = 0;
670 // XXX What's this section for??
671 DBE_GETREG(ctrlstat, readVal);
672 readVal &= 0x02000000;
675 DBE_SETREG(ctrlstat, 0x30000000);
681 * Set a single color register. The values supplied are already
682 * rounded down to the hardware's capabilities (according to the
683 * entries in the var structure). Return != 0 for invalid regno.
686 static int sgivwfb_setcolreg(u_int regno, u_int red, u_int green,
687 u_int blue, u_int transp,
688 struct fb_info *info)
690 struct sgivw_par *par = (struct sgivw_par *) info->par;
698 /* wait for the color map FIFO to have a free entry */
699 while (par->cmap_fifo == 0)
700 par->cmap_fifo = par->regs->cm_fifo;
702 par->regs->cmap[regno] = (red << 24) | (green << 16) | (blue << 8);
703 par->cmap_fifo--; /* assume FIFO is filling up */
707 static int sgivwfb_mmap(struct fb_info *info,
708 struct vm_area_struct *vma)
710 unsigned long size = vma->vm_end - vma->vm_start;
711 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
713 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
715 if (offset + size > sgivwfb_mem_size)
717 offset += sgivwfb_mem_phys;
718 pgprot_val(vma->vm_page_prot) =
719 pgprot_val(vma->vm_page_prot) | _PAGE_PCD;
720 vma->vm_flags |= VM_IO;
721 if (remap_pfn_range(vma, vma->vm_start, offset >> PAGE_SHIFT,
722 size, vma->vm_page_prot))
724 printk(KERN_DEBUG "sgivwfb: mmap framebuffer P(%lx)->V(%lx)\n",
725 offset, vma->vm_start);
729 int __init sgivwfb_setup(char *options)
733 if (!options || !*options)
736 while ((this_opt = strsep(&options, ",")) != NULL) {
737 if (!strncmp(this_opt, "monitor:", 8)) {
738 if (!strncmp(this_opt + 8, "crt", 3))
740 else if (!strncmp(this_opt + 8, "1600sw", 6))
741 flatpanel_id = FLATPANEL_SGI_1600SW;
750 static int __init sgivwfb_probe(struct platform_device *dev)
752 struct sgivw_par *par;
753 struct fb_info *info;
756 info = framebuffer_alloc(sizeof(struct sgivw_par) + sizeof(u32) * 256, &dev->dev);
761 if (!request_mem_region(DBE_REG_PHYS, DBE_REG_SIZE, "sgivwfb")) {
762 printk(KERN_ERR "sgivwfb: couldn't reserve mmio region\n");
763 framebuffer_release(info);
767 par->regs = (struct asregs *) ioremap_nocache(DBE_REG_PHYS, DBE_REG_SIZE);
769 printk(KERN_ERR "sgivwfb: couldn't ioremap registers\n");
770 goto fail_ioremap_regs;
773 mtrr_add(sgivwfb_mem_phys, sgivwfb_mem_size, MTRR_TYPE_WRCOMB, 1);
775 sgivwfb_fix.smem_start = sgivwfb_mem_phys;
776 sgivwfb_fix.smem_len = sgivwfb_mem_size;
777 sgivwfb_fix.ywrapstep = ywrap;
778 sgivwfb_fix.ypanstep = ypan;
780 info->fix = sgivwfb_fix;
782 switch (flatpanel_id) {
783 case FLATPANEL_SGI_1600SW:
784 info->var = sgivwfb_var1600sw;
785 monitor = "SGI 1600SW flatpanel";
788 info->var = sgivwfb_var;
792 printk(KERN_INFO "sgivwfb: %s monitor selected\n", monitor);
794 info->fbops = &sgivwfb_ops;
795 info->pseudo_palette = (void *) (par + 1);
796 info->flags = FBINFO_DEFAULT;
798 info->screen_base = ioremap_nocache((unsigned long) sgivwfb_mem_phys, sgivwfb_mem_size);
799 if (!info->screen_base) {
800 printk(KERN_ERR "sgivwfb: couldn't ioremap screen_base\n");
801 goto fail_ioremap_fbmem;
804 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
807 if (register_framebuffer(info) < 0) {
808 printk(KERN_ERR "sgivwfb: couldn't register framebuffer\n");
809 goto fail_register_framebuffer;
812 platform_set_drvdata(dev, info);
814 printk(KERN_INFO "fb%d: SGI DBE frame buffer device, using %ldK of video memory at %#lx\n",
815 info->node, sgivwfb_mem_size >> 10, sgivwfb_mem_phys);
818 fail_register_framebuffer:
819 fb_dealloc_cmap(&info->cmap);
821 iounmap((char *) info->screen_base);
825 release_mem_region(DBE_REG_PHYS, DBE_REG_SIZE);
826 framebuffer_release(info);
830 static int sgivwfb_remove(struct platform_device *dev)
832 struct fb_info *info = platform_get_drvdata(dev);
835 struct sgivw_par *par = info->par;
837 unregister_framebuffer(info);
840 iounmap(info->screen_base);
841 release_mem_region(DBE_REG_PHYS, DBE_REG_SIZE);
846 static struct platform_driver sgivwfb_driver = {
847 .probe = sgivwfb_probe,
848 .remove = sgivwfb_remove,
854 static struct platform_device *sgivwfb_device;
856 int __init sgivwfb_init(void)
863 if (fb_get_options("sgivwfb", &option))
865 sgivwfb_setup(option);
867 ret = platform_driver_register(&sgivwfb_driver);
869 sgivwfb_device = platform_device_alloc("sgivwfb", 0);
870 if (sgivwfb_device) {
871 ret = platform_device_add(sgivwfb_device);
875 platform_driver_unregister(&sgivwfb_driver);
876 platform_device_put(sgivwfb_device);
882 module_init(sgivwfb_init);
885 MODULE_LICENSE("GPL");
887 static void __exit sgivwfb_exit(void)
889 platform_device_unregister(sgivwfb_device);
890 platform_driver_unregister(&sgivwfb_driver);
893 module_exit(sgivwfb_exit);