5 /* The ATU offsets can change based on the strapping */
6 extern u32 iop13xx_atux_pmmr_offset;
7 extern u32 iop13xx_atue_pmmr_offset;
8 void iop13xx_init_irq(void);
9 void iop13xx_map_io(void);
10 void iop13xx_platform_init(void);
11 void iop13xx_init_irq(void);
13 /* CPUID CP6 R0 Page 0 */
14 static inline int iop13xx_cpu_id(void)
17 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
24 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
26 #define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
27 #define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
30 * bus range cpu phys cpu virt note
31 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
32 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
33 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
36 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
37 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
39 #define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
40 #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
41 #define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
42 #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
43 #define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
44 #define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
45 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
46 #define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
47 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
48 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
49 (IOP13XX_PCIX_LOWER_IO_PA\
50 - IOP13XX_PCIX_LOWER_IO_VA))
52 #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
53 #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
54 #define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
55 #define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
56 IOP13XX_PCIX_LOWER_MEM_BA)
57 #define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
58 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
59 #define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
60 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
62 #define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
63 #define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
64 #define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
65 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
66 #define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
67 IOP13XX_PCIX_LOWER_MEM_BA)
70 #define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
71 #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
72 #define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
73 #define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
74 #define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
75 #define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
76 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
77 #define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
78 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
79 #define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
80 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
81 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
82 (IOP13XX_PCIE_LOWER_IO_PA\
83 - IOP13XX_PCIE_LOWER_IO_VA))
85 #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
86 #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
87 #define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
88 #define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
89 IOP13XX_PCIE_LOWER_MEM_BA)
90 #define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
91 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
92 #define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
93 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
95 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
96 #define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
97 #define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
98 #define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
99 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
100 #define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
101 IOP13XX_PCIE_LOWER_MEM_BA)
104 #define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
105 #define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
106 #define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
107 #define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
108 #define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
109 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
112 * IOP13XX chipset registers
114 #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
115 #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
116 #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
117 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
118 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
119 #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
120 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
121 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
122 (IOP13XX_PMMR_PHYS_MEM_BASE\
123 - IOP13XX_PMMR_VIRT_MEM_BASE))
124 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
125 (IOP13XX_PMMR_PHYS_MEM_BASE\
126 - IOP13XX_PMMR_VIRT_MEM_BASE))
127 #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
128 #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
129 #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
130 #define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
131 #define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
132 #define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
133 #define IOP13XX_PMMR_SIZE 0x00080000
135 /*=================== Defines for Platform Devices =====================*/
136 #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
137 #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
138 #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
139 #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
141 #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
142 #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
143 #define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
144 #define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
145 #define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
146 #define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
148 /* ATU selection flags */
149 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
150 #define IOP13XX_INIT_ATU_DEFAULT (0)
151 #define IOP13XX_INIT_ATU_ATUX (1 << 0)
152 #define IOP13XX_INIT_ATU_ATUE (1 << 1)
153 #define IOP13XX_INIT_ATU_NONE (1 << 2)
155 /* UART selection flags */
156 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
157 #define IOP13XX_INIT_UART_DEFAULT (0)
158 #define IOP13XX_INIT_UART_0 (1 << 0)
159 #define IOP13XX_INIT_UART_1 (1 << 1)
161 /* I2C selection flags */
162 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
163 #define IOP13XX_INIT_I2C_DEFAULT (0)
164 #define IOP13XX_INIT_I2C_0 (1 << 0)
165 #define IOP13XX_INIT_I2C_1 (1 << 1)
166 #define IOP13XX_INIT_I2C_2 (1 << 2)
168 #define IQ81340_NUM_UART 2
169 #define IQ81340_NUM_I2C 3
170 #define IQ81340_NUM_PHYS_MAP_FLASH 1
171 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
173 IQ81340_NUM_PHYS_MAP_FLASH)
175 /*========================== PMMR offsets for key registers ============*/
176 #define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
177 #define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
178 #define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
179 #define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
180 #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
181 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
182 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580
183 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
184 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
186 #define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
187 #define IOP13XX_CONTROLLER_ONLY (1 << 14)
188 #define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
190 #define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
191 #define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
192 IOP13XX_PMON_PMMR_OFFSET)
193 #define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
194 IOP13XX_PMON_PMMR_OFFSET)
196 #define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
197 #define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
198 #define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
199 #define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
201 #define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
202 #define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
203 #define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
204 #define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
206 #define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
207 #define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
208 #define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
209 #define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
211 #define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
212 #define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
214 /*================================ATU===================================*/
215 #define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
216 iop13xx_atux_pmmr_offset + (ofs))
218 #define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
219 iop13xx_atux_pmmr_offset + 0x2)
221 #define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
222 iop13xx_atux_pmmr_offset + 0x4)
223 #define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
224 iop13xx_atux_pmmr_offset + 0x6)
226 #define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
227 #define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
228 #define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
229 #define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
230 #define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
231 #define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
232 #define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
233 #define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
234 #define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
235 #define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
236 #define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
237 #define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
238 #define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
239 #define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
240 #define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
241 #define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
242 #define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
243 #define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
244 #define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
245 #define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
246 #define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
247 #define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
248 #define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
249 #define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
251 #define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
252 #define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
253 #define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
254 #define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
255 #define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
256 #define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
257 #define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
258 #define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
259 #define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
260 #define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
261 #define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
262 #define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
263 #define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
264 #define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
266 #define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
267 #define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
268 #define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
269 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
270 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
271 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
273 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
274 #define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
275 #define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
276 #define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
277 #define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
278 #define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
279 #define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
280 #define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
281 #define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
282 #define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
283 #define IOP13XX_ATUX_STAT_BIST (1 << 8 )
284 #define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
285 #define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
286 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
287 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
288 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
289 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
291 #define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
292 #define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
293 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
295 #define IOP13XX_ATUX_IALR_DISABLE 0x00000001
296 #define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
298 #define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
299 iop13xx_atue_pmmr_offset + (ofs))
301 #define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
302 iop13xx_atue_pmmr_offset + 0x2)
303 #define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
304 iop13xx_atue_pmmr_offset + 0x4)
305 #define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
306 iop13xx_atue_pmmr_offset + 0x6)
308 #define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
309 #define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
310 #define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
311 #define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
312 #define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
313 #define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
314 #define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
315 #define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
316 #define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
317 #define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
318 #define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
319 #define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
320 #define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
321 #define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
322 #define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
323 #define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
324 iop13xx_atue_pmmr_offset + 0xe2)
325 #define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
326 #define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
327 #define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
328 #define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
329 #define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
330 #define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
331 #define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
332 #define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
333 #define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
335 #define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
336 #define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
337 #define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
338 #define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
339 #define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
340 #define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
342 #define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
343 #define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
345 #define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
346 #define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
347 #define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
348 #define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
349 #define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
350 #define IOP13XX_ATUE_OCCAR_EXT_REG (8)
351 #define IOP13XX_ATUE_OCCAR_REG (2)
353 #define IOP13XX_ATUE_PCSR_BUS_NUM (24)
354 #define IOP13XX_ATUE_PCSR_DEV_NUM (19)
355 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
356 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
357 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
358 #define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
359 #define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
361 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
362 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
363 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
365 #define IOP13XX_ATUE_PCSR_CORE_RESET (8)
366 #define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
368 #define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
369 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
370 #define IOP13XX_ATUE_STAT_PME (1 << 27)
371 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
372 #define IOP13XX_ATUE_STAT_IVM (1 << 25)
373 #define IOP13XX_ATUE_STAT_BIST (1 << 24)
374 #define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
375 #define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
376 #define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
377 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
378 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
379 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
380 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
381 #define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
382 #define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
383 #define IOP13XX_ATUE_STAT_CRS (1 << 7 )
384 #define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
385 #define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
386 #define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
387 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
388 #define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
389 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
390 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
392 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
393 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
394 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
395 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
396 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
397 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
398 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
399 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
400 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
401 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
402 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
403 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
404 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
405 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
406 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
408 #define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
409 #define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
410 #define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
411 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
412 /*=======================================================================*/
414 /*==============================ADMA UNITS===============================*/
415 #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
416 #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
417 #define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
419 #define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
420 #define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
421 #define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
422 #define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
423 #define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
424 #define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
425 #define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
426 #define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
427 #define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
428 #define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
429 #define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
430 #define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
431 #define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
432 #define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
434 /*==============================XSI BRIDGE===============================*/
435 #define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
436 #define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
437 #define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
438 #define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
439 IOP13XX_PMMR_VIRT_TO_PHYS(\
440 IOP13XX_ATUE_OCCDR))\
441 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
442 #define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
443 IOP13XX_PMMR_VIRT_TO_PHYS(\
444 IOP13XX_ATUX_OCCDR))\
445 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
446 /*=======================================================================*/
448 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
451 #define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
452 #define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
453 #define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
454 #define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
455 #define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
456 #define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
458 #endif /* _IOP13XX_HW_H_ */