2 * linux/include/asm-arm/cacheflush.h
4 * Copyright (C) 1999-2002 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef _ASMARM_CACHEFLUSH_H
11 #define _ASMARM_CACHEFLUSH_H
13 #include <linux/sched.h>
17 #include <asm/shmparam.h>
19 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
28 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) || \
29 defined(CONFIG_CPU_ARM740T)
31 # define MULTI_CACHE 1
37 #if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM7TDMI) || \
38 defined(CONFIG_CPU_ARM9TDMI)
40 # define MULTI_CACHE 1
46 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
47 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
48 # define MULTI_CACHE 1
51 #if defined(CONFIG_CPU_ARM926T)
53 # define MULTI_CACHE 1
55 # define _CACHE arm926
59 #if defined(CONFIG_CPU_ARM940T)
61 # define MULTI_CACHE 1
63 # define _CACHE arm940
67 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
69 # define MULTI_CACHE 1
75 #if defined(CONFIG_CPU_XSCALE)
77 # define MULTI_CACHE 1
79 # define _CACHE xscale
83 #if defined(CONFIG_CPU_XSC3)
85 # define MULTI_CACHE 1
91 #if defined(CONFIG_CPU_V6)
93 # define MULTI_CACHE 1
99 #if !defined(_CACHE) && !defined(MULTI_CACHE)
100 #error Unknown cache maintainence model
104 * This flag is used to indicate that the page pointed to by a pte
105 * is dirty and requires cleaning before returning it to the user.
107 #define PG_dcache_dirty PG_arch_1
110 * MM Cache Management
111 * ===================
113 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
114 * implement these methods.
116 * Start addresses are inclusive and end addresses are exclusive;
117 * start addresses should be rounded down, end addresses up.
119 * See Documentation/cachetlb.txt for more information.
120 * Please note that the implementation of these, and the required
121 * effects are cache-type (VIVT/VIPT/PIPT) specific.
123 * flush_cache_kern_all()
125 * Unconditionally clean and invalidate the entire cache.
127 * flush_cache_user_mm(mm)
129 * Clean and invalidate all user space cache entries
130 * before a change of page tables.
132 * flush_cache_user_range(start, end, flags)
134 * Clean and invalidate a range of cache entries in the
135 * specified address space before a change of page tables.
136 * - start - user start address (inclusive, page aligned)
137 * - end - user end address (exclusive, page aligned)
138 * - flags - vma->vm_flags field
140 * coherent_kern_range(start, end)
142 * Ensure coherency between the Icache and the Dcache in the
143 * region described by start, end. If you have non-snooping
144 * Harvard caches, you need to implement this function.
145 * - start - virtual start address
146 * - end - virtual end address
148 * DMA Cache Coherency
149 * ===================
151 * dma_inv_range(start, end)
153 * Invalidate (discard) the specified virtual address range.
154 * May not write back any entries. If 'start' or 'end'
155 * are not cache line aligned, those lines must be written
157 * - start - virtual start address
158 * - end - virtual end address
160 * dma_clean_range(start, end)
162 * Clean (write back) the specified virtual address range.
163 * - start - virtual start address
164 * - end - virtual end address
166 * dma_flush_range(start, end)
168 * Clean and invalidate the specified virtual address range.
169 * - start - virtual start address
170 * - end - virtual end address
173 struct cpu_cache_fns {
174 void (*flush_kern_all)(void);
175 void (*flush_user_all)(void);
176 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
178 void (*coherent_kern_range)(unsigned long, unsigned long);
179 void (*coherent_user_range)(unsigned long, unsigned long);
180 void (*flush_kern_dcache_page)(void *);
182 void (*dma_inv_range)(unsigned long, unsigned long);
183 void (*dma_clean_range)(unsigned long, unsigned long);
184 void (*dma_flush_range)(unsigned long, unsigned long);
188 * Select the calling method
192 extern struct cpu_cache_fns cpu_cache;
194 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all
195 #define __cpuc_flush_user_all cpu_cache.flush_user_all
196 #define __cpuc_flush_user_range cpu_cache.flush_user_range
197 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range
198 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range
199 #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page
202 * These are private to the dma-mapping API. Do not use directly.
203 * Their sole purpose is to ensure that data held in the cache
204 * is visible to DMA, or data written by DMA to system memory is
205 * visible to the CPU.
207 #define dmac_inv_range cpu_cache.dma_inv_range
208 #define dmac_clean_range cpu_cache.dma_clean_range
209 #define dmac_flush_range cpu_cache.dma_flush_range
213 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
214 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
215 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
216 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
217 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
218 #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page)
220 extern void __cpuc_flush_kern_all(void);
221 extern void __cpuc_flush_user_all(void);
222 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
223 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
224 extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
225 extern void __cpuc_flush_dcache_page(void *);
228 * These are private to the dma-mapping API. Do not use directly.
229 * Their sole purpose is to ensure that data held in the cache
230 * is visible to DMA, or data written by DMA to system memory is
231 * visible to the CPU.
233 #define dmac_inv_range __glue(_CACHE,_dma_inv_range)
234 #define dmac_clean_range __glue(_CACHE,_dma_clean_range)
235 #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
237 extern void dmac_inv_range(unsigned long, unsigned long);
238 extern void dmac_clean_range(unsigned long, unsigned long);
239 extern void dmac_flush_range(unsigned long, unsigned long);
244 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
245 * vmalloc, ioremap etc) in kernel space for pages. Since the
246 * direct-mappings of these pages may contain cached data, we need
247 * to do a full cache flush to ensure that writebacks don't corrupt
248 * data placed into these pages via the new mappings.
250 #define flush_cache_vmap(start, end) flush_cache_all()
251 #define flush_cache_vunmap(start, end) flush_cache_all()
254 * Copy user data from/to a page which is mapped into a different
255 * processes address space. Really, we want to allow our "user
256 * space" model to handle this.
258 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \
260 memcpy(dst, src, len); \
261 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
264 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
266 memcpy(dst, src, len); \
270 * Convert calls to our calling convention.
272 #define flush_cache_all() __cpuc_flush_kern_all()
273 #ifndef CONFIG_CPU_CACHE_VIPT
274 static inline void flush_cache_mm(struct mm_struct *mm)
276 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
277 __cpuc_flush_user_all();
281 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
283 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
284 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
289 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
291 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
292 unsigned long addr = user_addr & PAGE_MASK;
293 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
298 flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
299 unsigned long uaddr, void *kaddr,
300 unsigned long len, int write)
302 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
303 unsigned long addr = (unsigned long)kaddr;
304 __cpuc_coherent_kern_range(addr, addr + len);
308 extern void flush_cache_mm(struct mm_struct *mm);
309 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
310 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
311 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
312 unsigned long uaddr, void *kaddr,
313 unsigned long len, int write);
317 * flush_cache_user_range is used when we want to ensure that the
318 * Harvard caches are synchronised for the user space address range.
319 * This is used for the ARM private sys_cacheflush system call.
321 #define flush_cache_user_range(vma,start,end) \
322 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
325 * Perform necessary cache operations to ensure that data previously
326 * stored within this range of addresses can be executed by the CPU.
328 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e)
331 * Perform necessary cache operations to ensure that the TLB will
332 * see data written in the specified area.
334 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size)
337 * flush_dcache_page is used when the kernel has written to the page
338 * cache page at virtual address page->virtual.
340 * If this page isn't mapped (ie, page_mapping == NULL), or it might
341 * have userspace mappings, then we _must_ always clean + invalidate
342 * the dcache entries associated with the kernel mapping.
344 * Otherwise we can defer the operation, and clean the cache when we are
345 * about to change to user space. This is the same method as used on SPARC64.
346 * See update_mmu_cache for the user space part.
348 extern void flush_dcache_page(struct page *);
350 #define flush_dcache_mmap_lock(mapping) \
351 write_lock_irq(&(mapping)->tree_lock)
352 #define flush_dcache_mmap_unlock(mapping) \
353 write_unlock_irq(&(mapping)->tree_lock)
355 #define flush_icache_user_range(vma,page,addr,len) \
356 flush_dcache_page(page)
359 * We don't appear to need to do anything here. In fact, if we did, we'd
360 * duplicate cache flushing elsewhere performed by flush_dcache_page().
362 #define flush_icache_page(vma,page) do { } while (0)
364 #define __cacheid_present(val) (val != read_cpuid(CPUID_ID))
365 #define __cacheid_vivt(val) ((val & (15 << 25)) != (14 << 25))
366 #define __cacheid_vipt(val) ((val & (15 << 25)) == (14 << 25))
367 #define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
368 #define __cacheid_vipt_aliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
370 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
372 #define cache_is_vivt() 1
373 #define cache_is_vipt() 0
374 #define cache_is_vipt_nonaliasing() 0
375 #define cache_is_vipt_aliasing() 0
377 #elif defined(CONFIG_CPU_CACHE_VIPT)
379 #define cache_is_vivt() 0
380 #define cache_is_vipt() 1
381 #define cache_is_vipt_nonaliasing() \
383 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
384 __cacheid_vipt_nonaliasing(__val); \
387 #define cache_is_vipt_aliasing() \
389 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
390 __cacheid_vipt_aliasing(__val); \
395 #define cache_is_vivt() \
397 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
398 (!__cacheid_present(__val)) || __cacheid_vivt(__val); \
401 #define cache_is_vipt() \
403 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
404 __cacheid_present(__val) && __cacheid_vipt(__val); \
407 #define cache_is_vipt_nonaliasing() \
409 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
410 __cacheid_present(__val) && \
411 __cacheid_vipt_nonaliasing(__val); \
414 #define cache_is_vipt_aliasing() \
416 unsigned int __val = read_cpuid(CPUID_CACHETYPE); \
417 __cacheid_present(__val) && \
418 __cacheid_vipt_aliasing(__val); \