include/asm-i386/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define         APIC_LVR        0x30
  15 #define                 APIC_LVR_MASK           0xFF00FF
  16 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  17 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  18 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  19 #define         APIC_TASKPRI    0x80
  20 #define                 APIC_TPRI_MASK          0xFF
  21 #define         APIC_ARBPRI     0x90
  22 #define                 APIC_ARBPRI_MASK        0xFF
  23 #define         APIC_PROCPRI    0xA0
  24 #define         APIC_EOI        0xB0
  25 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  26 #define         APIC_RRR        0xC0
  27 #define         APIC_LDR        0xD0
  28 #define                 APIC_LDR_MASK           (0xFF<<24)
  29 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  30 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  31 #define                 APIC_ALL_CPUS           0xFF
  32 #define         APIC_DFR        0xE0
  33 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  34 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  35 #define         APIC_SPIV       0xF0
  36 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  37 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  38 #define         APIC_ISR        0x100
  39 #define         APIC_TMR        0x180
  40 #define         APIC_IRR        0x200
  41 #define         APIC_ESR        0x280
  42 #define                 APIC_ESR_SEND_CS        0x00001
  43 #define                 APIC_ESR_RECV_CS        0x00002
  44 #define                 APIC_ESR_SEND_ACC       0x00004
  45 #define                 APIC_ESR_RECV_ACC       0x00008
  46 #define                 APIC_ESR_SENDILL        0x00020
  47 #define                 APIC_ESR_RECVILL        0x00040
  48 #define                 APIC_ESR_ILLREGA        0x00080
  49 #define         APIC_ICR        0x300
  50 #define                 APIC_DEST_SELF          0x40000
  51 #define                 APIC_DEST_ALLINC        0x80000
  52 #define                 APIC_DEST_ALLBUT        0xC0000
  53 #define                 APIC_ICR_RR_MASK        0x30000
  54 #define                 APIC_ICR_RR_INVALID     0x00000
  55 #define                 APIC_ICR_RR_INPROG      0x10000
  56 #define                 APIC_ICR_RR_VALID       0x20000
  57 #define                 APIC_INT_LEVELTRIG      0x08000
  58 #define                 APIC_INT_ASSERT         0x04000
  59 #define                 APIC_ICR_BUSY           0x01000
  60 #define                 APIC_DEST_LOGICAL       0x00800
  61 #define                 APIC_DM_FIXED           0x00000
  62 #define                 APIC_DM_LOWEST          0x00100
  63 #define                 APIC_DM_SMI             0x00200
  64 #define                 APIC_DM_REMRD           0x00300
  65 #define                 APIC_DM_NMI             0x00400
  66 #define                 APIC_DM_INIT            0x00500
  67 #define                 APIC_DM_STARTUP         0x00600
  68 #define                 APIC_DM_EXTINT          0x00700
  69 #define                 APIC_VECTOR_MASK        0x000FF
  70 #define         APIC_ICR2       0x310
  71 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  72 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  73 #define         APIC_LVTT       0x320
  74 #define         APIC_LVTTHMR    0x330
  75 #define         APIC_LVTPC      0x340
  76 #define         APIC_LVT0       0x350
  77 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  78 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  79 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  80 #define                 APIC_TIMER_BASE_CLKIN           0x0
  81 #define                 APIC_TIMER_BASE_TMBASE          0x1
  82 #define                 APIC_TIMER_BASE_DIV             0x2
  83 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  84 #define                 APIC_LVT_MASKED                 (1<<16)
  85 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  86 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  87 #define                 APIC_INPUT_POLARITY             (1<<13)
  88 #define                 APIC_SEND_PENDING               (1<<12)
  89 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  90 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  91 #define                         APIC_MODE_FIXED         0x0
  92 #define                         APIC_MODE_NMI           0x4
  93 #define                         APIC_MODE_EXINT         0x7
  94 #define         APIC_LVT1       0x360
  95 #define         APIC_LVTERR     0x370
  96 #define         APIC_TMICT      0x380
  97 #define         APIC_TMCCT      0x390
  98 #define         APIC_TDCR       0x3E0
  99 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 100 #define                 APIC_TDR_DIV_1          0xB
 101 #define                 APIC_TDR_DIV_2          0x0
 102 #define                 APIC_TDR_DIV_4          0x1
 103 #define                 APIC_TDR_DIV_8          0x2
 104 #define                 APIC_TDR_DIV_16         0x3
 105 #define                 APIC_TDR_DIV_32         0x8
 106 #define                 APIC_TDR_DIV_64         0x9
 107 #define                 APIC_TDR_DIV_128        0xA
 108
 109 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 110
 111 #ifdef CONFIG_NUMA
 112  #define MAX_IO_APICS 32
 113 #else
 114  #define MAX_IO_APICS 8
 115 #endif
 116
 117 /*
 118  * the local APIC register structure, memory mapped. Not terribly well
 119  * tested, but we might eventually use this one in the future - the
 120  * problem why we cannot use it right now is the P5 APIC, it has an
 121  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 122  */
 123 #define u32 unsigned int
 124
 125 #define lapic ((volatile struct local_apic *)APIC_BASE)
 126
 127 struct local_apic {
 128
 129 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 130
 131 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 132
 133 /*020*/ struct { /* APIC ID Register */
 134                 u32   __reserved_1      : 24,
 135                         phys_apic_id    :  4,
 136                         __reserved_2    :  4;
 137                 u32 __reserved[3];
 138         } id;
 139
 140 /*030*/ const
 141         struct { /* APIC Version Register */
 142                 u32   version           :  8,
 143                         __reserved_1    :  8,
 144                         max_lvt         :  8,
 145                         __reserved_2    :  8;
 146                 u32 __reserved[3];
 147         } version;
 148
 149 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 150
 151 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 152
 153 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 154
 155 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 156
 157 /*080*/ struct { /* Task Priority Register */
 158                 u32   priority  :  8,
 159                         __reserved_1    : 24;
 160                 u32 __reserved_2[3];
 161         } tpr;
 162
 163 /*090*/ const
 164         struct { /* Arbitration Priority Register */
 165                 u32   priority  :  8,
 166                         __reserved_1    : 24;
 167                 u32 __reserved_2[3];
 168         } apr;
 169
 170 /*0A0*/ const
 171         struct { /* Processor Priority Register */
 172                 u32   priority  :  8,
 173                         __reserved_1    : 24;
 174                 u32 __reserved_2[3];
 175         } ppr;
 176
 177 /*0B0*/ struct { /* End Of Interrupt Register */
 178                 u32   eoi;
 179                 u32 __reserved[3];
 180         } eoi;
 181
 182 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 183
 184 /*0D0*/ struct { /* Logical Destination Register */
 185                 u32   __reserved_1      : 24,
 186                         logical_dest    :  8;
 187                 u32 __reserved_2[3];
 188         } ldr;
 189
 190 /*0E0*/ struct { /* Destination Format Register */
 191                 u32   __reserved_1      : 28,
 192                         model           :  4;
 193                 u32 __reserved_2[3];
 194         } dfr;
 195
 196 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 197                 u32     spurious_vector :  8,
 198                         apic_enabled    :  1,
 199                         focus_cpu       :  1,
 200                         __reserved_2    : 22;
 201                 u32 __reserved_3[3];
 202         } svr;
 203
 204 /*100*/ struct { /* In Service Register */
 205 /*170*/         u32 bitfield;
 206                 u32 __reserved[3];
 207         } isr [8];
 208
 209 /*180*/ struct { /* Trigger Mode Register */
 210 /*1F0*/         u32 bitfield;
 211                 u32 __reserved[3];
 212         } tmr [8];
 213
 214 /*200*/ struct { /* Interrupt Request Register */
 215 /*270*/         u32 bitfield;
 216                 u32 __reserved[3];
 217         } irr [8];
 218
 219 /*280*/ union { /* Error Status Register */
 220                 struct {
 221                         u32   send_cs_error                     :  1,
 222                                 receive_cs_error                :  1,
 223                                 send_accept_error               :  1,
 224                                 receive_accept_error            :  1,
 225                                 __reserved_1                    :  1,
 226                                 send_illegal_vector             :  1,
 227                                 receive_illegal_vector          :  1,
 228                                 illegal_register_address        :  1,
 229                                 __reserved_2                    : 24;
 230                         u32 __reserved_3[3];
 231                 } error_bits;
 232                 struct {
 233                         u32 errors;
 234                         u32 __reserved_3[3];
 235                 } all_errors;
 236         } esr;
 237
 238 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 239
 240 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 241
 242 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 243
 244 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 245
 246 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 247
 248 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 249
 250 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 251
 252 /*300*/ struct { /* Interrupt Command Register 1 */
 253                 u32   vector                    :  8,
 254                         delivery_mode           :  3,
 255                         destination_mode        :  1,
 256                         delivery_status         :  1,
 257                         __reserved_1            :  1,
 258                         level                   :  1,
 259                         trigger                 :  1,
 260                         __reserved_2            :  2,
 261                         shorthand               :  2,
 262                         __reserved_3            :  12;
 263                 u32 __reserved_4[3];
 264         } icr1;
 265
 266 /*310*/ struct { /* Interrupt Command Register 2 */
 267                 union {
 268                         u32   __reserved_1      : 24,
 269                                 phys_dest       :  4,
 270                                 __reserved_2    :  4;
 271                         u32   __reserved_3      : 24,
 272                                 logical_dest    :  8;
 273                 } dest;
 274                 u32 __reserved_4[3];
 275         } icr2;
 276
 277 /*320*/ struct { /* LVT - Timer */
 278                 u32   vector            :  8,
 279                         __reserved_1    :  4,
 280                         delivery_status :  1,
 281                         __reserved_2    :  3,
 282                         mask            :  1,
 283                         timer_mode      :  1,
 284                         __reserved_3    : 14;
 285                 u32 __reserved_4[3];
 286         } lvt_timer;
 287
 288 /*330*/ struct { /* LVT - Thermal Sensor */
 289                 u32  vector             :  8,
 290                         delivery_mode   :  3,
 291                         __reserved_1    :  1,
 292                         delivery_status :  1,
 293                         __reserved_2    :  3,
 294                         mask            :  1,
 295                         __reserved_3    : 15;
 296                 u32 __reserved_4[3];
 297         } lvt_thermal;
 298
 299 /*340*/ struct { /* LVT - Performance Counter */
 300                 u32   vector            :  8,
 301                         delivery_mode   :  3,
 302                         __reserved_1    :  1,
 303                         delivery_status :  1,
 304                         __reserved_2    :  3,
 305                         mask            :  1,
 306                         __reserved_3    : 15;
 307                 u32 __reserved_4[3];
 308         } lvt_pc;
 309
 310 /*350*/ struct { /* LVT - LINT0 */
 311                 u32   vector            :  8,
 312                         delivery_mode   :  3,
 313                         __reserved_1    :  1,
 314                         delivery_status :  1,
 315                         polarity        :  1,
 316                         remote_irr      :  1,
 317                         trigger         :  1,
 318                         mask            :  1,
 319                         __reserved_2    : 15;
 320                 u32 __reserved_3[3];
 321         } lvt_lint0;
 322
 323 /*360*/ struct { /* LVT - LINT1 */
 324                 u32   vector            :  8,
 325                         delivery_mode   :  3,
 326                         __reserved_1    :  1,
 327                         delivery_status :  1,
 328                         polarity        :  1,
 329                         remote_irr      :  1,
 330                         trigger         :  1,
 331                         mask            :  1,
 332                         __reserved_2    : 15;
 333                 u32 __reserved_3[3];
 334         } lvt_lint1;
 335
 336 /*370*/ struct { /* LVT - Error */
 337                 u32   vector            :  8,
 338                         __reserved_1    :  4,
 339                         delivery_status :  1,
 340                         __reserved_2    :  3,
 341                         mask            :  1,
 342                         __reserved_3    : 15;
 343                 u32 __reserved_4[3];
 344         } lvt_error;
 345
 346 /*380*/ struct { /* Timer Initial Count Register */
 347                 u32   initial_count;
 348                 u32 __reserved_2[3];
 349         } timer_icr;
 350
 351 /*390*/ const
 352         struct { /* Timer Current Count Register */
 353                 u32   curr_count;
 354                 u32 __reserved_2[3];
 355         } timer_ccr;
 356
 357 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 358
 359 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 360
 361 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 362
 363 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 364
 365 /*3E0*/ struct { /* Timer Divide Configuration Register */
 366                 u32   divisor           :  4,
 367                         __reserved_1    : 28;
 368                 u32 __reserved_2[3];
 369         } timer_dcr;
 370
 371 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 372
 373 } __attribute__ ((packed));
 374
 375 #undef u32
 376
 377 #endif