include/asm-i386/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define         APIC_LVR        0x30
  15 #define                 APIC_LVR_MASK           0xFF00FF
  16 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  17 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  18 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  19 #define         APIC_TASKPRI    0x80
  20 #define                 APIC_TPRI_MASK          0xFF
  21 #define         APIC_ARBPRI     0x90
  22 #define                 APIC_ARBPRI_MASK        0xFF
  23 #define         APIC_PROCPRI    0xA0
  24 #define         APIC_EOI        0xB0
  25 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  26 #define         APIC_RRR        0xC0
  27 #define         APIC_LDR        0xD0
  28 #define                 APIC_LDR_MASK           (0xFF<<24)
  29 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  30 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  31 #define                 APIC_ALL_CPUS           0xFF
  32 #define         APIC_DFR        0xE0
  33 #define                 APIC_DFR_CLUSTER                0x0FFFFFFFul
  34 #define                 APIC_DFR_FLAT                   0xFFFFFFFFul
  35 #define         APIC_SPIV       0xF0
  36 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  37 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  38 #define         APIC_ISR        0x100
  39 #define         APIC_TMR        0x180
  40 #define         APIC_IRR        0x200
  41 #define         APIC_ESR        0x280
  42 #define                 APIC_ESR_SEND_CS        0x00001
  43 #define                 APIC_ESR_RECV_CS        0x00002
  44 #define                 APIC_ESR_SEND_ACC       0x00004
  45 #define                 APIC_ESR_RECV_ACC       0x00008
  46 #define                 APIC_ESR_SENDILL        0x00020
  47 #define                 APIC_ESR_RECVILL        0x00040
  48 #define                 APIC_ESR_ILLREGA        0x00080
  49 #define         APIC_ICR        0x300
  50 #define                 APIC_DEST_SELF          0x40000
  51 #define                 APIC_DEST_ALLINC        0x80000
  52 #define                 APIC_DEST_ALLBUT        0xC0000
  53 #define                 APIC_ICR_RR_MASK        0x30000
  54 #define                 APIC_ICR_RR_INVALID     0x00000
  55 #define                 APIC_ICR_RR_INPROG      0x10000
  56 #define                 APIC_ICR_RR_VALID       0x20000
  57 #define                 APIC_INT_LEVELTRIG      0x08000
  58 #define                 APIC_INT_ASSERT         0x04000
  59 #define                 APIC_ICR_BUSY           0x01000
  60 #define                 APIC_DEST_LOGICAL       0x00800
  61 #define                 APIC_DM_FIXED           0x00000
  62 #define                 APIC_DM_LOWEST          0x00100
  63 #define                 APIC_DM_SMI             0x00200
  64 #define                 APIC_DM_REMRD           0x00300
  65 #define                 APIC_DM_NMI             0x00400
  66 #define                 APIC_DM_INIT            0x00500
  67 #define                 APIC_DM_STARTUP         0x00600
  68 #define                 APIC_DM_EXTINT          0x00700
  69 #define                 APIC_VECTOR_MASK        0x000FF
  70 #define         APIC_ICR2       0x310
  71 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  72 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  73 #define         APIC_LVTT       0x320
  74 #define         APIC_LVTTHMR    0x330
  75 #define         APIC_LVTPC      0x340
  76 #define         APIC_LVT0       0x350
  77 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  78 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  79 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  80 #define                 APIC_TIMER_BASE_CLKIN           0x0
  81 #define                 APIC_TIMER_BASE_TMBASE          0x1
  82 #define                 APIC_TIMER_BASE_DIV             0x2
  83 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  84 #define                 APIC_LVT_MASKED                 (1<<16)
  85 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  86 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  87 #define                 APIC_INPUT_POLARITY             (1<<13)
  88 #define                 APIC_SEND_PENDING               (1<<12)
  89 #define                 APIC_MODE_MASK                  0x700
  90 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  91 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  92 #define                         APIC_MODE_FIXED         0x0
  93 #define                         APIC_MODE_NMI           0x4
  94 #define                         APIC_MODE_EXTINT        0x7
  95 #define         APIC_LVT1       0x360
  96 #define         APIC_LVTERR     0x370
  97 #define         APIC_TMICT      0x380
  98 #define         APIC_TMCCT      0x390
  99 #define         APIC_TDCR       0x3E0
 100 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 101 #define                 APIC_TDR_DIV_1          0xB
 102 #define                 APIC_TDR_DIV_2          0x0
 103 #define                 APIC_TDR_DIV_4          0x1
 104 #define                 APIC_TDR_DIV_8          0x2
 105 #define                 APIC_TDR_DIV_16         0x3
 106 #define                 APIC_TDR_DIV_32         0x8
 107 #define                 APIC_TDR_DIV_64         0x9
 108 #define                 APIC_TDR_DIV_128        0xA
 109
 110 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 111
 112 #define MAX_IO_APICS 64
 113
 114 /*
 115  * the local APIC register structure, memory mapped. Not terribly well
 116  * tested, but we might eventually use this one in the future - the
 117  * problem why we cannot use it right now is the P5 APIC, it has an
 118  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 119  */
 120 #define u32 unsigned int
 121
 122 #define lapic ((volatile struct local_apic *)APIC_BASE)
 123
 124 struct local_apic {
 125
 126 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 127
 128 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 129
 130 /*020*/ struct { /* APIC ID Register */
 131                 u32   __reserved_1      : 24,
 132                         phys_apic_id    :  4,
 133                         __reserved_2    :  4;
 134                 u32 __reserved[3];
 135         } id;
 136
 137 /*030*/ const
 138         struct { /* APIC Version Register */
 139                 u32   version           :  8,
 140                         __reserved_1    :  8,
 141                         max_lvt         :  8,
 142                         __reserved_2    :  8;
 143                 u32 __reserved[3];
 144         } version;
 145
 146 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 147
 148 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 149
 150 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 151
 152 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 153
 154 /*080*/ struct { /* Task Priority Register */
 155                 u32   priority  :  8,
 156                         __reserved_1    : 24;
 157                 u32 __reserved_2[3];
 158         } tpr;
 159
 160 /*090*/ const
 161         struct { /* Arbitration Priority Register */
 162                 u32   priority  :  8,
 163                         __reserved_1    : 24;
 164                 u32 __reserved_2[3];
 165         } apr;
 166
 167 /*0A0*/ const
 168         struct { /* Processor Priority Register */
 169                 u32   priority  :  8,
 170                         __reserved_1    : 24;
 171                 u32 __reserved_2[3];
 172         } ppr;
 173
 174 /*0B0*/ struct { /* End Of Interrupt Register */
 175                 u32   eoi;
 176                 u32 __reserved[3];
 177         } eoi;
 178
 179 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 180
 181 /*0D0*/ struct { /* Logical Destination Register */
 182                 u32   __reserved_1      : 24,
 183                         logical_dest    :  8;
 184                 u32 __reserved_2[3];
 185         } ldr;
 186
 187 /*0E0*/ struct { /* Destination Format Register */
 188                 u32   __reserved_1      : 28,
 189                         model           :  4;
 190                 u32 __reserved_2[3];
 191         } dfr;
 192
 193 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 194                 u32     spurious_vector :  8,
 195                         apic_enabled    :  1,
 196                         focus_cpu       :  1,
 197                         __reserved_2    : 22;
 198                 u32 __reserved_3[3];
 199         } svr;
 200
 201 /*100*/ struct { /* In Service Register */
 202 /*170*/         u32 bitfield;
 203                 u32 __reserved[3];
 204         } isr [8];
 205
 206 /*180*/ struct { /* Trigger Mode Register */
 207 /*1F0*/         u32 bitfield;
 208                 u32 __reserved[3];
 209         } tmr [8];
 210
 211 /*200*/ struct { /* Interrupt Request Register */
 212 /*270*/         u32 bitfield;
 213                 u32 __reserved[3];
 214         } irr [8];
 215
 216 /*280*/ union { /* Error Status Register */
 217                 struct {
 218                         u32   send_cs_error                     :  1,
 219                                 receive_cs_error                :  1,
 220                                 send_accept_error               :  1,
 221                                 receive_accept_error            :  1,
 222                                 __reserved_1                    :  1,
 223                                 send_illegal_vector             :  1,
 224                                 receive_illegal_vector          :  1,
 225                                 illegal_register_address        :  1,
 226                                 __reserved_2                    : 24;
 227                         u32 __reserved_3[3];
 228                 } error_bits;
 229                 struct {
 230                         u32 errors;
 231                         u32 __reserved_3[3];
 232                 } all_errors;
 233         } esr;
 234
 235 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 236
 237 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 238
 239 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 240
 241 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 242
 243 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 244
 245 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 246
 247 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 248
 249 /*300*/ struct { /* Interrupt Command Register 1 */
 250                 u32   vector                    :  8,
 251                         delivery_mode           :  3,
 252                         destination_mode        :  1,
 253                         delivery_status         :  1,
 254                         __reserved_1            :  1,
 255                         level                   :  1,
 256                         trigger                 :  1,
 257                         __reserved_2            :  2,
 258                         shorthand               :  2,
 259                         __reserved_3            :  12;
 260                 u32 __reserved_4[3];
 261         } icr1;
 262
 263 /*310*/ struct { /* Interrupt Command Register 2 */
 264                 union {
 265                         u32   __reserved_1      : 24,
 266                                 phys_dest       :  4,
 267                                 __reserved_2    :  4;
 268                         u32   __reserved_3      : 24,
 269                                 logical_dest    :  8;
 270                 } dest;
 271                 u32 __reserved_4[3];
 272         } icr2;
 273
 274 /*320*/ struct { /* LVT - Timer */
 275                 u32   vector            :  8,
 276                         __reserved_1    :  4,
 277                         delivery_status :  1,
 278                         __reserved_2    :  3,
 279                         mask            :  1,
 280                         timer_mode      :  1,
 281                         __reserved_3    : 14;
 282                 u32 __reserved_4[3];
 283         } lvt_timer;
 284
 285 /*330*/ struct { /* LVT - Thermal Sensor */
 286                 u32  vector             :  8,
 287                         delivery_mode   :  3,
 288                         __reserved_1    :  1,
 289                         delivery_status :  1,
 290                         __reserved_2    :  3,
 291                         mask            :  1,
 292                         __reserved_3    : 15;
 293                 u32 __reserved_4[3];
 294         } lvt_thermal;
 295
 296 /*340*/ struct { /* LVT - Performance Counter */
 297                 u32   vector            :  8,
 298                         delivery_mode   :  3,
 299                         __reserved_1    :  1,
 300                         delivery_status :  1,
 301                         __reserved_2    :  3,
 302                         mask            :  1,
 303                         __reserved_3    : 15;
 304                 u32 __reserved_4[3];
 305         } lvt_pc;
 306
 307 /*350*/ struct { /* LVT - LINT0 */
 308                 u32   vector            :  8,
 309                         delivery_mode   :  3,
 310                         __reserved_1    :  1,
 311                         delivery_status :  1,
 312                         polarity        :  1,
 313                         remote_irr      :  1,
 314                         trigger         :  1,
 315                         mask            :  1,
 316                         __reserved_2    : 15;
 317                 u32 __reserved_3[3];
 318         } lvt_lint0;
 319
 320 /*360*/ struct { /* LVT - LINT1 */
 321                 u32   vector            :  8,
 322                         delivery_mode   :  3,
 323                         __reserved_1    :  1,
 324                         delivery_status :  1,
 325                         polarity        :  1,
 326                         remote_irr      :  1,
 327                         trigger         :  1,
 328                         mask            :  1,
 329                         __reserved_2    : 15;
 330                 u32 __reserved_3[3];
 331         } lvt_lint1;
 332
 333 /*370*/ struct { /* LVT - Error */
 334                 u32   vector            :  8,
 335                         __reserved_1    :  4,
 336                         delivery_status :  1,
 337                         __reserved_2    :  3,
 338                         mask            :  1,
 339                         __reserved_3    : 15;
 340                 u32 __reserved_4[3];
 341         } lvt_error;
 342
 343 /*380*/ struct { /* Timer Initial Count Register */
 344                 u32   initial_count;
 345                 u32 __reserved_2[3];
 346         } timer_icr;
 347
 348 /*390*/ const
 349         struct { /* Timer Current Count Register */
 350                 u32   curr_count;
 351                 u32 __reserved_2[3];
 352         } timer_ccr;
 353
 354 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 355
 356 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 357
 358 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 359
 360 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 361
 362 /*3E0*/ struct { /* Timer Divide Configuration Register */
 363                 u32   divisor           :  4,
 364                         __reserved_1    : 28;
 365                 u32 __reserved_2[3];
 366         } timer_dcr;
 367
 368 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 369
 370 } __attribute__ ((packed));
 371
 372 #undef u32
 373
 374 #endif