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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (C) 1994, 1995 Waldorf GmbH
7  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
10  *      Author: Maciej W. Rozycki <macro@mips.com>
11  */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18
19 #include <asm/addrspace.h>
20 #include <asm/byteorder.h>
21 #include <asm/cpu.h>
22 #include <asm/cpu-features.h>
23 #include <asm-generic/iomap.h>
24 #include <asm/page.h>
25 #include <asm/pgtable-bits.h>
26 #include <asm/processor.h>
27 #include <asm/string.h>
28
29 #include <ioremap.h>
30 #include <mangle-port.h>
31
32 /*
33  * Slowdown I/O port space accesses for antique hardware.
34  */
35 #undef CONF_SLOWDOWN_IO
36
37 /*
38  * Raw operations are never swapped in software.  OTOH values that raw
39  * operations are working on may or may not have been swapped by the bus
40  * hardware.  An example use would be for flash memory that's used for
41  * execute in place.
42  */
43 # define __raw_ioswabb(a,x)     (x)
44 # define __raw_ioswabw(a,x)     (x)
45 # define __raw_ioswabl(a,x)     (x)
46 # define __raw_ioswabq(a,x)     (x)
47 # define ____raw_ioswabq(a,x)   (x)
48
49 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
50
51 #define IO_SPACE_LIMIT 0xffff
52
53 /*
54  * On MIPS I/O ports are memory mapped, so we access them using normal
55  * load/store instructions. mips_io_port_base is the virtual address to
56  * which all ports are being mapped.  For sake of efficiency some code
57  * assumes that this is an address that can be loaded with a single lui
58  * instruction, so the lower 16 bits must be zero.  Should be true on
59  * on any sane architecture; generic code does not use this assumption.
60  */
61 extern const unsigned long mips_io_port_base;
62
63 /*
64  * Gcc will generate code to load the value of mips_io_port_base after each
65  * function call which may be fairly wasteful in some cases.  So we don't
66  * play quite by the book.  We tell gcc mips_io_port_base is a long variable
67  * which solves the code generation issue.  Now we need to violate the
68  * aliasing rules a little to make initialization possible and finally we
69  * will need the barrier() to fight side effects of the aliasing chat.
70  * This trickery will eventually collapse under gcc's optimizer.  Oh well.
71  */
72 static inline void set_io_port_base(unsigned long base)
73 {
74         * (unsigned long *) &mips_io_port_base = base;
75         barrier();
76 }
77
78 /*
79  * Thanks to James van Artsdalen for a better timing-fix than
80  * the two short jumps: using outb's to a nonexistent port seems
81  * to guarantee better timings even on fast machines.
82  *
83  * On the other hand, I'd like to be sure of a non-existent port:
84  * I feel a bit unsafe about using 0x80 (should be safe, though)
85  *
86  *              Linus
87  *
88  */
89
90 #define __SLOW_DOWN_IO \
91         __asm__ __volatile__( \
92                 "sb\t$0,0x80(%0)" \
93                 : : "r" (mips_io_port_base));
94
95 #ifdef CONF_SLOWDOWN_IO
96 #ifdef REALLY_SLOW_IO
97 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
98 #else
99 #define SLOW_DOWN_IO __SLOW_DOWN_IO
100 #endif
101 #else
102 #define SLOW_DOWN_IO
103 #endif
104
105 /*
106  *     virt_to_phys    -       map virtual addresses to physical
107  *     @address: address to remap
108  *
109  *     The returned physical address is the physical (CPU) mapping for
110  *     the memory address given. It is only valid to use this function on
111  *     addresses directly mapped or allocated via kmalloc.
112  *
113  *     This function does not give bus mappings for DMA transfers. In
114  *     almost all conceivable cases a device driver should not be using
115  *     this function
116  */
117 static inline unsigned long virt_to_phys(volatile const void *address)
118 {
119         return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
120 }
121
122 /*
123  *     phys_to_virt    -       map physical address to virtual
124  *     @address: address to remap
125  *
126  *     The returned virtual address is a current CPU mapping for
127  *     the memory address given. It is only valid to use this function on
128  *     addresses that have a kernel mapping
129  *
130  *     This function does not handle bus mappings for DMA transfers. In
131  *     almost all conceivable cases a device driver should not be using
132  *     this function
133  */
134 static inline void * phys_to_virt(unsigned long address)
135 {
136         return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
137 }
138
139 /*
140  * ISA I/O bus memory addresses are 1:1 with the physical address.
141  */
142 static inline unsigned long isa_virt_to_bus(volatile void * address)
143 {
144         return (unsigned long)address - PAGE_OFFSET;
145 }
146
147 static inline void * isa_bus_to_virt(unsigned long address)
148 {
149         return (void *)(address + PAGE_OFFSET);
150 }
151
152 #define isa_page_to_bus page_to_phys
153
154 /*
155  * However PCI ones are not necessarily 1:1 and therefore these interfaces
156  * are forbidden in portable PCI drivers.
157  *
158  * Allow them for x86 for legacy drivers, though.
159  */
160 #define virt_to_bus virt_to_phys
161 #define bus_to_virt phys_to_virt
162
163 /*
164  * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
165  * for the processor.  This implies the assumption that there is only
166  * one of these busses.
167  */
168 extern unsigned long isa_slot_offset;
169
170 /*
171  * Change "struct page" to physical address.
172  */
173 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
174
175 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
176 extern void __iounmap(const volatile void __iomem *addr);
177
178 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
179         unsigned long flags)
180 {
181         void __iomem *addr = plat_ioremap(offset, size, flags);
182
183         if (addr)
184                 return addr;
185
186 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
187
188         if (cpu_has_64bit_addresses) {
189                 u64 base = UNCAC_BASE;
190
191                 /*
192                  * R10000 supports a 2 bit uncached attribute therefore
193                  * UNCAC_BASE may not equal IO_BASE.
194                  */
195                 if (flags == _CACHE_UNCACHED)
196                         base = (u64) IO_BASE;
197                 return (void __iomem *) (unsigned long) (base + offset);
198         } else if (__builtin_constant_p(offset) &&
199                    __builtin_constant_p(size) && __builtin_constant_p(flags)) {
200                 phys_t phys_addr, last_addr;
201
202                 phys_addr = fixup_bigphys_addr(offset, size);
203
204                 /* Don't allow wraparound or zero size. */
205                 last_addr = phys_addr + size - 1;
206                 if (!size || last_addr < phys_addr)
207                         return NULL;
208
209                 /*
210                  * Map uncached objects in the low 512MB of address
211                  * space using KSEG1.
212                  */
213                 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
214                     flags == _CACHE_UNCACHED)
215                         return (void __iomem *)CKSEG1ADDR(phys_addr);
216         }
217
218         return __ioremap(offset, size, flags);
219
220 #undef __IS_LOW512
221 }
222
223 /*
224  * ioremap     -   map bus memory into CPU space
225  * @offset:    bus address of the memory
226  * @size:      size of the resource to map
227  *
228  * ioremap performs a platform specific sequence of operations to
229  * make bus memory CPU accessible via the readb/readw/readl/writeb/
230  * writew/writel functions and the other mmio helpers. The returned
231  * address is not guaranteed to be usable directly as a virtual
232  * address.
233  */
234 #define ioremap(offset, size)                                           \
235         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
236
237 /*
238  * ioremap_nocache     -   map bus memory into CPU space
239  * @offset:    bus address of the memory
240  * @size:      size of the resource to map
241  *
242  * ioremap_nocache performs a platform specific sequence of operations to
243  * make bus memory CPU accessible via the readb/readw/readl/writeb/
244  * writew/writel functions and the other mmio helpers. The returned
245  * address is not guaranteed to be usable directly as a virtual
246  * address.
247  *
248  * This version of ioremap ensures that the memory is marked uncachable
249  * on the CPU as well as honouring existing caching rules from things like
250  * the PCI bus. Note that there are other caches and buffers on many
251  * busses. In paticular driver authors should read up on PCI writes
252  *
253  * It's useful if some control registers are in such an area and
254  * write combining or read caching is not desirable:
255  */
256 #define ioremap_nocache(offset, size)                                   \
257         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
258
259 /*
260  * ioremap_cachable -   map bus memory into CPU space
261  * @offset:         bus address of the memory
262  * @size:           size of the resource to map
263  *
264  * ioremap_nocache performs a platform specific sequence of operations to
265  * make bus memory CPU accessible via the readb/readw/readl/writeb/
266  * writew/writel functions and the other mmio helpers. The returned
267  * address is not guaranteed to be usable directly as a virtual
268  * address.
269  *
270  * This version of ioremap ensures that the memory is marked cachable by
271  * the CPU.  Also enables full write-combining.  Useful for some
272  * memory-like regions on I/O busses.
273  */
274 #define ioremap_cachable(offset, size)                                  \
275         __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
276
277 /*
278  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
279  * requests a cachable mapping, ioremap_uncached_accelerated requests a
280  * mapping using the uncached accelerated mode which isn't supported on
281  * all processors.
282  */
283 #define ioremap_cacheable_cow(offset, size)                             \
284         __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
285 #define ioremap_uncached_accelerated(offset, size)                      \
286         __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
287
288 static inline void iounmap(const volatile void __iomem *addr)
289 {
290         if (plat_iounmap(addr))
291                 return;
292
293 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
294
295         if (cpu_has_64bit_addresses ||
296             (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
297                 return;
298
299         __iounmap(addr);
300
301 #undef __IS_KSEG1
302 }
303
304 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
305                                                                         \
306 static inline void pfx##write##bwlq(type val,                           \
307                                     volatile void __iomem *mem)         \
308 {                                                                       \
309         volatile type *__mem;                                           \
310         type __val;                                                     \
311                                                                         \
312         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
313                                                                         \
314         __val = pfx##ioswab##bwlq(__mem, val);                          \
315                                                                         \
316         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
317                 *__mem = __val;                                         \
318         else if (cpu_has_64bits) {                                      \
319                 unsigned long __flags;                                  \
320                 type __tmp;                                             \
321                                                                         \
322                 if (irq)                                                \
323                         local_irq_save(__flags);                        \
324                 __asm__ __volatile__(                                   \
325                         ".set   mips3"          "\t\t# __writeq""\n\t"  \
326                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
327                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
328                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
329                         "or     %L0, %L0, %M0"                  "\n\t"  \
330                         "sd     %L0, %2"                        "\n\t"  \
331                         ".set   mips0"                          "\n"    \
332                         : "=r" (__tmp)                                  \
333                         : "0" (__val), "m" (*__mem));                   \
334                 if (irq)                                                \
335                         local_irq_restore(__flags);                     \
336         } else                                                          \
337                 BUG();                                                  \
338 }                                                                       \
339                                                                         \
340 static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
341 {                                                                       \
342         volatile type *__mem;                                           \
343         type __val;                                                     \
344                                                                         \
345         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
346                                                                         \
347         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
348                 __val = *__mem;                                         \
349         else if (cpu_has_64bits) {                                      \
350                 unsigned long __flags;                                  \
351                                                                         \
352                 if (irq)                                                \
353                         local_irq_save(__flags);                        \
354                 __asm__ __volatile__(                                   \
355                         ".set   mips3"          "\t\t# __readq" "\n\t"  \
356                         "ld     %L0, %1"                        "\n\t"  \
357                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
358                         "sll    %L0, %L0, 0"                    "\n\t"  \
359                         ".set   mips0"                          "\n"    \
360                         : "=r" (__val)                                  \
361                         : "m" (*__mem));                                \
362                 if (irq)                                                \
363                         local_irq_restore(__flags);                     \
364         } else {                                                        \
365                 __val = 0;                                              \
366                 BUG();                                                  \
367         }                                                               \
368                                                                         \
369         return pfx##ioswab##bwlq(__mem, __val);                         \
370 }
371
372 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
373                                                                         \
374 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
375 {                                                                       \
376         volatile type *__addr;                                          \
377         type __val;                                                     \
378                                                                         \
379         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
380                                                                         \
381         __val = pfx##ioswab##bwlq(__addr, val);                         \
382                                                                         \
383         /* Really, we want this to be atomic */                         \
384         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
385                                                                         \
386         *__addr = __val;                                                \
387         slow;                                                           \
388 }                                                                       \
389                                                                         \
390 static inline type pfx##in##bwlq##p(unsigned long port)                 \
391 {                                                                       \
392         volatile type *__addr;                                          \
393         type __val;                                                     \
394                                                                         \
395         __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
396                                                                         \
397         BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
398                                                                         \
399         __val = *__addr;                                                \
400         slow;                                                           \
401                                                                         \
402         return pfx##ioswab##bwlq(__addr, __val);                        \
403 }
404
405 #define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
406                                                                         \
407 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
408
409 #define BUILDIO_MEM(bwlq, type)                                         \
410                                                                         \
411 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
412 __BUILD_MEMORY_PFX(, bwlq, type)                                        \
413 __BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
414
415 BUILDIO_MEM(b, u8)
416 BUILDIO_MEM(w, u16)
417 BUILDIO_MEM(l, u32)
418 BUILDIO_MEM(q, u64)
419
420 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
421         __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
422         __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
423
424 #define BUILDIO_IOPORT(bwlq, type)                                      \
425         __BUILD_IOPORT_PFX(, bwlq, type)                                \
426         __BUILD_IOPORT_PFX(__mem_, bwlq, type)
427
428 BUILDIO_IOPORT(b, u8)
429 BUILDIO_IOPORT(w, u16)
430 BUILDIO_IOPORT(l, u32)
431 #ifdef CONFIG_64BIT
432 BUILDIO_IOPORT(q, u64)
433 #endif
434
435 #define __BUILDIO(bwlq, type)                                           \
436                                                                         \
437 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
438
439 __BUILDIO(q, u64)
440
441 #define readb_relaxed                   readb
442 #define readw_relaxed                   readw
443 #define readl_relaxed                   readl
444 #define readq_relaxed                   readq
445
446 /*
447  * Some code tests for these symbols
448  */
449 #define readq                           readq
450 #define writeq                          writeq
451
452 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
453                                                                         \
454 static inline void writes##bwlq(volatile void __iomem *mem,             \
455                                 const void *addr, unsigned int count)   \
456 {                                                                       \
457         const volatile type *__addr = addr;                             \
458                                                                         \
459         while (count--) {                                               \
460                 __mem_write##bwlq(*__addr, mem);                        \
461                 __addr++;                                               \
462         }                                                               \
463 }                                                                       \
464                                                                         \
465 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
466                                unsigned int count)                      \
467 {                                                                       \
468         volatile type *__addr = addr;                                   \
469                                                                         \
470         while (count--) {                                               \
471                 *__addr = __mem_read##bwlq(mem);                        \
472                 __addr++;                                               \
473         }                                                               \
474 }
475
476 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
477                                                                         \
478 static inline void outs##bwlq(unsigned long port, const void *addr,     \
479                               unsigned int count)                       \
480 {                                                                       \
481         const volatile type *__addr = addr;                             \
482                                                                         \
483         while (count--) {                                               \
484                 __mem_out##bwlq(*__addr, port);                         \
485                 __addr++;                                               \
486         }                                                               \
487 }                                                                       \
488                                                                         \
489 static inline void ins##bwlq(unsigned long port, void *addr,            \
490                              unsigned int count)                        \
491 {                                                                       \
492         volatile type *__addr = addr;                                   \
493                                                                         \
494         while (count--) {                                               \
495                 *__addr = __mem_in##bwlq(port);                         \
496                 __addr++;                                               \
497         }                                                               \
498 }
499
500 #define BUILDSTRING(bwlq, type)                                         \
501                                                                         \
502 __BUILD_MEMORY_STRING(bwlq, type)                                       \
503 __BUILD_IOPORT_STRING(bwlq, type)
504
505 BUILDSTRING(b, u8)
506 BUILDSTRING(w, u16)
507 BUILDSTRING(l, u32)
508 #ifdef CONFIG_64BIT
509 BUILDSTRING(q, u64)
510 #endif
511
512
513 /* Depends on MIPS II instruction set */
514 #define mmiowb() asm volatile ("sync" ::: "memory")
515
516 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
517 {
518         memset((void __force *) addr, val, count);
519 }
520 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
521 {
522         memcpy(dst, (void __force *) src, count);
523 }
524 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
525 {
526         memcpy((void __force *) dst, src, count);
527 }
528
529 /*
530  * ISA space is 'always mapped' on currently supported MIPS systems, no need
531  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
532  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
533  * are physical addresses. The following constant pointer can be
534  * used as the IO-area pointer (it can be iounmapped as well, so the
535  * analogy with PCI is quite large):
536  */
537 #define __ISA_IO_base ((char *)(isa_slot_offset))
538
539 /*
540  * The caches on some architectures aren't dma-coherent and have need to
541  * handle this in software.  There are three types of operations that
542  * can be applied to dma buffers.
543  *
544  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
545  *    writing the content of the caches back to memory, if necessary.
546  *    The function also invalidates the affected part of the caches as
547  *    necessary before DMA transfers from outside to memory.
548  *  - dma_cache_wback(start, size) makes caches and coherent by
549  *    writing the content of the caches back to memory, if necessary.
550  *    The function also invalidates the affected part of the caches as
551  *    necessary before DMA transfers from outside to memory.
552  *  - dma_cache_inv(start, size) invalidates the affected parts of the
553  *    caches.  Dirty lines of the caches may be written back or simply
554  *    be discarded.  This operation is necessary before dma operations
555  *    to the memory.
556  */
557 #ifdef CONFIG_DMA_NONCOHERENT
558
559 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
560 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
561 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
562
563 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start,size)
564 #define dma_cache_wback(start, size)            _dma_cache_wback(start,size)
565 #define dma_cache_inv(start, size)              _dma_cache_inv(start,size)
566
567 #else /* Sane hardware */
568
569 #define dma_cache_wback_inv(start,size) \
570         do { (void) (start); (void) (size); } while (0)
571 #define dma_cache_wback(start,size)     \
572         do { (void) (start); (void) (size); } while (0)
573 #define dma_cache_inv(start,size)       \
574         do { (void) (start); (void) (size); } while (0)
575
576 #endif /* CONFIG_DMA_NONCOHERENT */
577
578 /*
579  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
580  * Avoid interrupt mucking, just adjust the address for 4-byte access.
581  * Assume the addresses are 8-byte aligned.
582  */
583 #ifdef __MIPSEB__
584 #define __CSR_32_ADJUST 4
585 #else
586 #define __CSR_32_ADJUST 0
587 #endif
588
589 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
590 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
591
592 /*
593  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
594  * access
595  */
596 #define xlate_dev_mem_ptr(p)    __va(p)
597
598 /*
599  * Convert a virtual cached pointer to an uncached pointer
600  */
601 #define xlate_dev_kmem_ptr(p)   p
602
603 #endif /* _ASM_IO_H */