2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H
16 #include <linux/config.h>
17 #include <linux/linkage.h>
18 #include <asm/hazards.h>
21 * The following macros are especially useful for __asm__
28 #define STR(x) __STR(x)
37 #define _ULCAST_ (unsigned long)
40 #include <asm/mipsmtregs.h>
43 * Coprocessor 0 register names
47 #define CP0_ENTRYLO0 $2
48 #define CP0_ENTRYLO1 $3
50 #define CP0_CONTEXT $4
51 #define CP0_PAGEMASK $5
54 #define CP0_BADVADDR $8
56 #define CP0_ENTRYHI $10
57 #define CP0_COMPARE $11
58 #define CP0_STATUS $12
62 #define CP0_CONFIG $16
63 #define CP0_LLADDR $17
64 #define CP0_WATCHLO $18
65 #define CP0_WATCHHI $19
66 #define CP0_XCONTEXT $20
67 #define CP0_FRAMEMASK $21
68 #define CP0_DIAGNOSTIC $22
71 #define CP0_PERFORMANCE $25
73 #define CP0_CACHEERR $27
76 #define CP0_ERROREPC $30
77 #define CP0_DESAVE $31
80 * R4640/R4650 cp0 register names. These registers are listed
81 * here only for completeness; without MMU these CPUs are not useable
82 * by Linux. A future ELKS port might take make Linux run on them
90 #define CP0_IWATCH $18
91 #define CP0_DWATCH $19
94 * Coprocessor 0 Set 1 register names
96 #define CP0_S1_DERRADDR0 $26
97 #define CP0_S1_DERRADDR1 $27
98 #define CP0_S1_INTCONTROL $20
101 * Coprocessor 0 Set 2 register names
103 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
106 * Coprocessor 0 Set 3 register names
108 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
113 #define CP0_TX39_CACHE $7
116 * Coprocessor 1 (FPU) register names
118 #define CP1_REVISION $0
119 #define CP1_STATUS $31
122 * FPU Status Register Values
125 * Status Register Values
128 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
129 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
130 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
131 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
132 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
133 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
134 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
135 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
136 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
137 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
140 * X the exception cause indicator
141 * E the exception enable
142 * S the sticky/flag bit
144 #define FPU_CSR_ALL_X 0x0003f000
145 #define FPU_CSR_UNI_X 0x00020000
146 #define FPU_CSR_INV_X 0x00010000
147 #define FPU_CSR_DIV_X 0x00008000
148 #define FPU_CSR_OVF_X 0x00004000
149 #define FPU_CSR_UDF_X 0x00002000
150 #define FPU_CSR_INE_X 0x00001000
152 #define FPU_CSR_ALL_E 0x00000f80
153 #define FPU_CSR_INV_E 0x00000800
154 #define FPU_CSR_DIV_E 0x00000400
155 #define FPU_CSR_OVF_E 0x00000200
156 #define FPU_CSR_UDF_E 0x00000100
157 #define FPU_CSR_INE_E 0x00000080
159 #define FPU_CSR_ALL_S 0x0000007c
160 #define FPU_CSR_INV_S 0x00000040
161 #define FPU_CSR_DIV_S 0x00000020
162 #define FPU_CSR_OVF_S 0x00000010
163 #define FPU_CSR_UDF_S 0x00000008
164 #define FPU_CSR_INE_S 0x00000004
167 #define FPU_CSR_RN 0x0 /* nearest */
168 #define FPU_CSR_RZ 0x1 /* towards zero */
169 #define FPU_CSR_RU 0x2 /* towards +Infinity */
170 #define FPU_CSR_RD 0x3 /* towards -Infinity */
174 * Values for PageMask register
176 #ifdef CONFIG_CPU_VR41XX
178 /* Why doesn't stupidity hurt ... */
180 #define PM_1K 0x00000000
181 #define PM_4K 0x00001800
182 #define PM_16K 0x00007800
183 #define PM_64K 0x0001f800
184 #define PM_256K 0x0007f800
188 #define PM_4K 0x00000000
189 #define PM_16K 0x00006000
190 #define PM_64K 0x0001e000
191 #define PM_256K 0x0007e000
192 #define PM_1M 0x001fe000
193 #define PM_4M 0x007fe000
194 #define PM_16M 0x01ffe000
195 #define PM_64M 0x07ffe000
196 #define PM_256M 0x1fffe000
201 * Default page size for a given kernel configuration
203 #ifdef CONFIG_PAGE_SIZE_4KB
204 #define PM_DEFAULT_MASK PM_4K
205 #elif defined(CONFIG_PAGE_SIZE_16KB)
206 #define PM_DEFAULT_MASK PM_16K
207 #elif defined(CONFIG_PAGE_SIZE_64KB)
208 #define PM_DEFAULT_MASK PM_64K
210 #error Bad page size configuration!
215 * Values used for computation of new tlb entries
228 * R4x00 interrupt enable / cause bits
230 #define IE_SW0 (_ULCAST_(1) << 8)
231 #define IE_SW1 (_ULCAST_(1) << 9)
232 #define IE_IRQ0 (_ULCAST_(1) << 10)
233 #define IE_IRQ1 (_ULCAST_(1) << 11)
234 #define IE_IRQ2 (_ULCAST_(1) << 12)
235 #define IE_IRQ3 (_ULCAST_(1) << 13)
236 #define IE_IRQ4 (_ULCAST_(1) << 14)
237 #define IE_IRQ5 (_ULCAST_(1) << 15)
240 * R4x00 interrupt cause bits
242 #define C_SW0 (_ULCAST_(1) << 8)
243 #define C_SW1 (_ULCAST_(1) << 9)
244 #define C_IRQ0 (_ULCAST_(1) << 10)
245 #define C_IRQ1 (_ULCAST_(1) << 11)
246 #define C_IRQ2 (_ULCAST_(1) << 12)
247 #define C_IRQ3 (_ULCAST_(1) << 13)
248 #define C_IRQ4 (_ULCAST_(1) << 14)
249 #define C_IRQ5 (_ULCAST_(1) << 15)
252 * Bitfields in the R4xx0 cp0 status register
254 #define ST0_IE 0x00000001
255 #define ST0_EXL 0x00000002
256 #define ST0_ERL 0x00000004
257 #define ST0_KSU 0x00000018
258 # define KSU_USER 0x00000010
259 # define KSU_SUPERVISOR 0x00000008
260 # define KSU_KERNEL 0x00000000
261 #define ST0_UX 0x00000020
262 #define ST0_SX 0x00000040
263 #define ST0_KX 0x00000080
264 #define ST0_DE 0x00010000
265 #define ST0_CE 0x00020000
268 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
269 * cacheops in userspace. This bit exists only on RM7000 and RM9000
272 #define ST0_CO 0x08000000
275 * Bitfields in the R[23]000 cp0 status register.
277 #define ST0_IEC 0x00000001
278 #define ST0_KUC 0x00000002
279 #define ST0_IEP 0x00000004
280 #define ST0_KUP 0x00000008
281 #define ST0_IEO 0x00000010
282 #define ST0_KUO 0x00000020
283 /* bits 6 & 7 are reserved on R[23]000 */
284 #define ST0_ISC 0x00010000
285 #define ST0_SWC 0x00020000
286 #define ST0_CM 0x00080000
289 * Bits specific to the R4640/R4650
291 #define ST0_UM (_ULCAST_(1) << 4)
292 #define ST0_IL (_ULCAST_(1) << 23)
293 #define ST0_DL (_ULCAST_(1) << 24)
296 * Enable the MIPS DSP ASE
298 #define ST0_MX 0x01000000
301 * Bitfields in the TX39 family CP0 Configuration Register 3
303 #define TX39_CONF_ICS_SHIFT 19
304 #define TX39_CONF_ICS_MASK 0x00380000
305 #define TX39_CONF_ICS_1KB 0x00000000
306 #define TX39_CONF_ICS_2KB 0x00080000
307 #define TX39_CONF_ICS_4KB 0x00100000
308 #define TX39_CONF_ICS_8KB 0x00180000
309 #define TX39_CONF_ICS_16KB 0x00200000
311 #define TX39_CONF_DCS_SHIFT 16
312 #define TX39_CONF_DCS_MASK 0x00070000
313 #define TX39_CONF_DCS_1KB 0x00000000
314 #define TX39_CONF_DCS_2KB 0x00010000
315 #define TX39_CONF_DCS_4KB 0x00020000
316 #define TX39_CONF_DCS_8KB 0x00030000
317 #define TX39_CONF_DCS_16KB 0x00040000
319 #define TX39_CONF_CWFON 0x00004000
320 #define TX39_CONF_WBON 0x00002000
321 #define TX39_CONF_RF_SHIFT 10
322 #define TX39_CONF_RF_MASK 0x00000c00
323 #define TX39_CONF_DOZE 0x00000200
324 #define TX39_CONF_HALT 0x00000100
325 #define TX39_CONF_LOCK 0x00000080
326 #define TX39_CONF_ICE 0x00000020
327 #define TX39_CONF_DCE 0x00000010
328 #define TX39_CONF_IRSIZE_SHIFT 2
329 #define TX39_CONF_IRSIZE_MASK 0x0000000c
330 #define TX39_CONF_DRSIZE_SHIFT 0
331 #define TX39_CONF_DRSIZE_MASK 0x00000003
334 * Status register bits available in all MIPS CPUs.
336 #define ST0_IM 0x0000ff00
337 #define STATUSB_IP0 8
338 #define STATUSF_IP0 (_ULCAST_(1) << 8)
339 #define STATUSB_IP1 9
340 #define STATUSF_IP1 (_ULCAST_(1) << 9)
341 #define STATUSB_IP2 10
342 #define STATUSF_IP2 (_ULCAST_(1) << 10)
343 #define STATUSB_IP3 11
344 #define STATUSF_IP3 (_ULCAST_(1) << 11)
345 #define STATUSB_IP4 12
346 #define STATUSF_IP4 (_ULCAST_(1) << 12)
347 #define STATUSB_IP5 13
348 #define STATUSF_IP5 (_ULCAST_(1) << 13)
349 #define STATUSB_IP6 14
350 #define STATUSF_IP6 (_ULCAST_(1) << 14)
351 #define STATUSB_IP7 15
352 #define STATUSF_IP7 (_ULCAST_(1) << 15)
353 #define STATUSB_IP8 0
354 #define STATUSF_IP8 (_ULCAST_(1) << 0)
355 #define STATUSB_IP9 1
356 #define STATUSF_IP9 (_ULCAST_(1) << 1)
357 #define STATUSB_IP10 2
358 #define STATUSF_IP10 (_ULCAST_(1) << 2)
359 #define STATUSB_IP11 3
360 #define STATUSF_IP11 (_ULCAST_(1) << 3)
361 #define STATUSB_IP12 4
362 #define STATUSF_IP12 (_ULCAST_(1) << 4)
363 #define STATUSB_IP13 5
364 #define STATUSF_IP13 (_ULCAST_(1) << 5)
365 #define STATUSB_IP14 6
366 #define STATUSF_IP14 (_ULCAST_(1) << 6)
367 #define STATUSB_IP15 7
368 #define STATUSF_IP15 (_ULCAST_(1) << 7)
369 #define ST0_CH 0x00040000
370 #define ST0_SR 0x00100000
371 #define ST0_TS 0x00200000
372 #define ST0_BEV 0x00400000
373 #define ST0_RE 0x02000000
374 #define ST0_FR 0x04000000
375 #define ST0_CU 0xf0000000
376 #define ST0_CU0 0x10000000
377 #define ST0_CU1 0x20000000
378 #define ST0_CU2 0x40000000
379 #define ST0_CU3 0x80000000
380 #define ST0_XX 0x80000000 /* MIPS IV naming */
383 * Bitfields and bit numbers in the coprocessor 0 cause register.
385 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
387 #define CAUSEB_EXCCODE 2
388 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
390 #define CAUSEF_IP (_ULCAST_(255) << 8)
392 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
394 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
395 #define CAUSEB_IP2 10
396 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
397 #define CAUSEB_IP3 11
398 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
399 #define CAUSEB_IP4 12
400 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
401 #define CAUSEB_IP5 13
402 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
403 #define CAUSEB_IP6 14
404 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
405 #define CAUSEB_IP7 15
406 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
408 #define CAUSEF_IV (_ULCAST_(1) << 23)
410 #define CAUSEF_CE (_ULCAST_(3) << 28)
412 #define CAUSEF_BD (_ULCAST_(1) << 31)
415 * Bits in the coprocessor 0 config register.
418 #define CONF_CM_CACHABLE_NO_WA 0
419 #define CONF_CM_CACHABLE_WA 1
420 #define CONF_CM_UNCACHED 2
421 #define CONF_CM_CACHABLE_NONCOHERENT 3
422 #define CONF_CM_CACHABLE_CE 4
423 #define CONF_CM_CACHABLE_COW 5
424 #define CONF_CM_CACHABLE_CUW 6
425 #define CONF_CM_CACHABLE_ACCELERATED 7
426 #define CONF_CM_CMASK 7
427 #define CONF_BE (_ULCAST_(1) << 15)
429 /* Bits common to various processors. */
430 #define CONF_CU (_ULCAST_(1) << 3)
431 #define CONF_DB (_ULCAST_(1) << 4)
432 #define CONF_IB (_ULCAST_(1) << 5)
433 #define CONF_DC (_ULCAST_(7) << 6)
434 #define CONF_IC (_ULCAST_(7) << 9)
435 #define CONF_EB (_ULCAST_(1) << 13)
436 #define CONF_EM (_ULCAST_(1) << 14)
437 #define CONF_SM (_ULCAST_(1) << 16)
438 #define CONF_SC (_ULCAST_(1) << 17)
439 #define CONF_EW (_ULCAST_(3) << 18)
440 #define CONF_EP (_ULCAST_(15)<< 24)
441 #define CONF_EC (_ULCAST_(7) << 28)
442 #define CONF_CM (_ULCAST_(1) << 31)
444 /* Bits specific to the R4xx0. */
445 #define R4K_CONF_SW (_ULCAST_(1) << 20)
446 #define R4K_CONF_SS (_ULCAST_(1) << 21)
447 #define R4K_CONF_SB (_ULCAST_(3) << 22)
449 /* Bits specific to the R5000. */
450 #define R5K_CONF_SE (_ULCAST_(1) << 12)
451 #define R5K_CONF_SS (_ULCAST_(3) << 20)
453 /* Bits specific to the RM7000. */
454 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
455 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
456 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
457 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
458 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
459 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
461 /* Bits specific to the R10000. */
462 #define R10K_CONF_DN (_ULCAST_(3) << 3)
463 #define R10K_CONF_CT (_ULCAST_(1) << 5)
464 #define R10K_CONF_PE (_ULCAST_(1) << 6)
465 #define R10K_CONF_PM (_ULCAST_(3) << 7)
466 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
467 #define R10K_CONF_SB (_ULCAST_(1) << 13)
468 #define R10K_CONF_SK (_ULCAST_(1) << 14)
469 #define R10K_CONF_SS (_ULCAST_(7) << 16)
470 #define R10K_CONF_SC (_ULCAST_(7) << 19)
471 #define R10K_CONF_DC (_ULCAST_(7) << 26)
472 #define R10K_CONF_IC (_ULCAST_(7) << 29)
474 /* Bits specific to the VR41xx. */
475 #define VR41_CONF_CS (_ULCAST_(1) << 12)
476 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
477 #define VR41_CONF_AD (_ULCAST_(1) << 23)
479 /* Bits specific to the R30xx. */
480 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
481 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
482 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
483 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
484 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
485 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
486 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
487 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
488 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
490 /* Bits specific to the TX49. */
491 #define TX49_CONF_DC (_ULCAST_(1) << 16)
492 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
493 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
494 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
496 /* Bits specific to the MIPS32/64 PRA. */
497 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
498 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
499 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
500 #define MIPS_CONF_M (_ULCAST_(1) << 31)
503 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
505 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
506 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
507 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
508 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
509 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
510 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
511 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
512 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
513 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
514 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
515 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
516 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
517 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
518 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
520 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
521 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
522 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
523 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
524 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
525 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
526 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
527 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
529 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
530 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
531 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
532 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
533 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
534 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
535 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
536 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
539 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
541 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
542 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
543 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
544 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
545 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
546 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
547 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
550 * R10000 performance counter definitions.
552 * FIXME: The R10000 performance counter opens a nice way to implement CPU
553 * time accounting with a precission of one cycle. I don't have
554 * R10000 silicon but just a manual, so ...
558 * Events counted by counter #0
561 #define CE0_INSN_ISSUED 1
562 #define CE0_LPSC_ISSUED 2
563 #define CE0_S_ISSUED 3
564 #define CE0_SC_ISSUED 4
565 #define CE0_SC_FAILED 5
566 #define CE0_BRANCH_DECODED 6
567 #define CE0_QW_WB_SECONDARY 7
568 #define CE0_CORRECTED_ECC_ERRORS 8
569 #define CE0_ICACHE_MISSES 9
570 #define CE0_SCACHE_I_MISSES 10
571 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
572 #define CE0_EXT_INTERVENTIONS_REQ 12
573 #define CE0_EXT_INVALIDATE_REQ 13
574 #define CE0_VIRTUAL_COHERENCY_COND 14
575 #define CE0_INSN_GRADUATED 15
578 * Events counted by counter #1
581 #define CE1_INSN_GRADUATED 1
582 #define CE1_LPSC_GRADUATED 2
583 #define CE1_S_GRADUATED 3
584 #define CE1_SC_GRADUATED 4
585 #define CE1_FP_INSN_GRADUATED 5
586 #define CE1_QW_WB_PRIMARY 6
587 #define CE1_TLB_REFILL 7
588 #define CE1_BRANCH_MISSPREDICTED 8
589 #define CE1_DCACHE_MISS 9
590 #define CE1_SCACHE_D_MISSES 10
591 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
592 #define CE1_EXT_INTERVENTION_HITS 12
593 #define CE1_EXT_INVALIDATE_REQ 13
594 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
595 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
598 * These flags define in which privilege mode the counters count events
600 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
601 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
602 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
603 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
608 * Functions to access the R10000 performance counters. These are basically
609 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
610 * performance counter number encoded into bits 1 ... 5 of the instruction.
611 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
612 * disassembler these will look like an access to sel 0 or 1.
614 #define read_r10k_perf_cntr(counter) \
616 unsigned int __res; \
617 __asm__ __volatile__( \
625 #define write_r10k_perf_cntr(counter,val) \
627 __asm__ __volatile__( \
630 : "r" (val), "i" (counter)); \
633 #define read_r10k_perf_event(counter) \
635 unsigned int __res; \
636 __asm__ __volatile__( \
644 #define write_r10k_perf_cntl(counter,val) \
646 __asm__ __volatile__( \
649 : "r" (val), "i" (counter)); \
654 * Macros to access the system control coprocessor
657 #define __read_32bit_c0_register(source, sel) \
660 __asm__ __volatile__( \
661 "mfc0\t%0, " #source "\n\t" \
664 __asm__ __volatile__( \
666 "mfc0\t%0, " #source ", " #sel "\n\t" \
672 #define __read_64bit_c0_register(source, sel) \
673 ({ unsigned long long __res; \
674 if (sizeof(unsigned long) == 4) \
675 __res = __read_64bit_c0_split(source, sel); \
677 __asm__ __volatile__( \
679 "dmfc0\t%0, " #source "\n\t" \
683 __asm__ __volatile__( \
685 "dmfc0\t%0, " #source ", " #sel "\n\t" \
691 #define __write_32bit_c0_register(register, sel, value) \
694 __asm__ __volatile__( \
695 "mtc0\t%z0, " #register "\n\t" \
696 : : "Jr" ((unsigned int)value)); \
698 __asm__ __volatile__( \
700 "mtc0\t%z0, " #register ", " #sel "\n\t" \
702 : : "Jr" ((unsigned int)value)); \
705 #define __write_64bit_c0_register(register, sel, value) \
707 if (sizeof(unsigned long) == 4) \
708 __write_64bit_c0_split(register, sel, value); \
710 __asm__ __volatile__( \
712 "dmtc0\t%z0, " #register "\n\t" \
716 __asm__ __volatile__( \
718 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
723 #define __read_ulong_c0_register(reg, sel) \
724 ((sizeof(unsigned long) == 4) ? \
725 (unsigned long) __read_32bit_c0_register(reg, sel) : \
726 (unsigned long) __read_64bit_c0_register(reg, sel))
728 #define __write_ulong_c0_register(reg, sel, val) \
730 if (sizeof(unsigned long) == 4) \
731 __write_32bit_c0_register(reg, sel, val); \
733 __write_64bit_c0_register(reg, sel, val); \
737 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
739 #define __read_32bit_c0_ctrl_register(source) \
741 __asm__ __volatile__( \
742 "cfc0\t%0, " #source "\n\t" \
747 #define __write_32bit_c0_ctrl_register(register, value) \
749 __asm__ __volatile__( \
750 "ctc0\t%z0, " #register "\n\t" \
751 : : "Jr" ((unsigned int)value)); \
755 * These versions are only needed for systems with more than 38 bits of
756 * physical address space running the 32-bit kernel. That's none atm :-)
758 #define __read_64bit_c0_split(source, sel) \
760 unsigned long long val; \
761 unsigned long flags; \
763 local_irq_save(flags); \
765 __asm__ __volatile__( \
767 "dmfc0\t%M0, " #source "\n\t" \
768 "dsll\t%L0, %M0, 32\n\t" \
769 "dsrl\t%M0, %M0, 32\n\t" \
770 "dsrl\t%L0, %L0, 32\n\t" \
774 __asm__ __volatile__( \
776 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
777 "dsll\t%L0, %M0, 32\n\t" \
778 "dsrl\t%M0, %M0, 32\n\t" \
779 "dsrl\t%L0, %L0, 32\n\t" \
782 local_irq_restore(flags); \
787 #define __write_64bit_c0_split(source, sel, val) \
789 unsigned long flags; \
791 local_irq_save(flags); \
793 __asm__ __volatile__( \
795 "dsll\t%L0, %L0, 32\n\t" \
796 "dsrl\t%L0, %L0, 32\n\t" \
797 "dsll\t%M0, %M0, 32\n\t" \
798 "or\t%L0, %L0, %M0\n\t" \
799 "dmtc0\t%L0, " #source "\n\t" \
803 __asm__ __volatile__( \
805 "dsll\t%L0, %L0, 32\n\t" \
806 "dsrl\t%L0, %L0, 32\n\t" \
807 "dsll\t%M0, %M0, 32\n\t" \
808 "or\t%L0, %L0, %M0\n\t" \
809 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
812 local_irq_restore(flags); \
815 #define read_c0_index() __read_32bit_c0_register($0, 0)
816 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
818 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
819 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
821 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
822 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
824 #define read_c0_conf() __read_32bit_c0_register($3, 0)
825 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
827 #define read_c0_context() __read_ulong_c0_register($4, 0)
828 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
830 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
831 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
833 #define read_c0_wired() __read_32bit_c0_register($6, 0)
834 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
836 #define read_c0_info() __read_32bit_c0_register($7, 0)
838 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
839 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
841 #define read_c0_count() __read_32bit_c0_register($9, 0)
842 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
844 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
845 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
847 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
848 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
850 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
851 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
853 #define read_c0_compare() __read_32bit_c0_register($11, 0)
854 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
856 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
857 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
859 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
860 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
862 #define read_c0_status() __read_32bit_c0_register($12, 0)
863 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
865 #define read_c0_cause() __read_32bit_c0_register($13, 0)
866 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
868 #define read_c0_epc() __read_ulong_c0_register($14, 0)
869 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
871 #define read_c0_prid() __read_32bit_c0_register($15, 0)
873 #define read_c0_config() __read_32bit_c0_register($16, 0)
874 #define read_c0_config1() __read_32bit_c0_register($16, 1)
875 #define read_c0_config2() __read_32bit_c0_register($16, 2)
876 #define read_c0_config3() __read_32bit_c0_register($16, 3)
877 #define read_c0_config4() __read_32bit_c0_register($16, 4)
878 #define read_c0_config5() __read_32bit_c0_register($16, 5)
879 #define read_c0_config6() __read_32bit_c0_register($16, 6)
880 #define read_c0_config7() __read_32bit_c0_register($16, 7)
881 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
882 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
883 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
884 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
885 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
886 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
887 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
888 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
891 * The WatchLo register. There may be upto 8 of them.
893 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
894 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
895 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
896 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
897 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
898 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
899 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
900 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
901 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
902 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
903 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
904 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
905 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
906 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
907 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
908 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
911 * The WatchHi register. There may be upto 8 of them.
913 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
914 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
915 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
916 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
917 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
918 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
919 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
920 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
922 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
923 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
924 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
925 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
926 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
927 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
928 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
929 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
931 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
932 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
934 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
935 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
937 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
938 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
940 /* RM9000 PerfControl performance counter control register */
941 #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0)
942 #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
944 #define read_c0_diag() __read_32bit_c0_register($22, 0)
945 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
947 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
948 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
950 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
951 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
953 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
954 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
956 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
957 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
959 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
960 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
962 #define read_c0_debug() __read_32bit_c0_register($23, 0)
963 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
965 #define read_c0_depc() __read_ulong_c0_register($24, 0)
966 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
969 * MIPS32 / MIPS64 performance counters
971 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
972 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
973 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
974 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
975 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
976 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
977 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
978 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
979 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
980 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
981 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
982 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
983 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
984 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
985 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
986 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
988 /* RM9000 PerfCount performance counter register */
989 #define read_c0_perfcount() __read_64bit_c0_register($25, 0)
990 #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
992 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
993 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
995 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
996 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
998 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1000 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1001 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1003 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1004 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1006 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1007 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1009 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1010 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1013 #define read_c0_hwrena() __read_32bit_c0_register($7,0)
1014 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1016 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1017 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1019 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1020 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1022 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1023 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1025 #define read_c0_ebase() __read_32bit_c0_register($15,1)
1026 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1029 * Macros to access the floating point coprocessor control registers
1031 #define read_32bit_cp1_register(source) \
1033 __asm__ __volatile__( \
1035 ".set\treorder\n\t" \
1036 "cfc1\t%0,"STR(source)"\n\t" \
1041 #define rddsp(mask) \
1043 unsigned int __res; \
1045 __asm__ __volatile__( \
1048 " # rddsp $1, %x1 \n" \
1049 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1057 #define wrdsp(val, mask) \
1059 __asm__ __volatile__( \
1063 " # wrdsp $1, %x1 \n" \
1064 " .word 0x7c2004f8 | (%x1 << 15) \n" \
1067 : "r" (val), "i" (mask)); \
1070 #if 0 /* Need DSP ASE capable assembler ... */
1071 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1072 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1073 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
1074 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
1076 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
1077 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
1078 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
1079 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
1081 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
1082 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
1083 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
1084 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
1086 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
1087 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
1088 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
1089 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1095 unsigned long __treg; \
1097 __asm__ __volatile__( \
1100 " # mfhi %0, $ac0 \n" \
1101 " .word 0x00000810 \n" \
1110 unsigned long __treg; \
1112 __asm__ __volatile__( \
1115 " # mfhi %0, $ac1 \n" \
1116 " .word 0x00200810 \n" \
1125 unsigned long __treg; \
1127 __asm__ __volatile__( \
1130 " # mfhi %0, $ac2 \n" \
1131 " .word 0x00400810 \n" \
1140 unsigned long __treg; \
1142 __asm__ __volatile__( \
1145 " # mfhi %0, $ac3 \n" \
1146 " .word 0x00600810 \n" \
1155 unsigned long __treg; \
1157 __asm__ __volatile__( \
1160 " # mflo %0, $ac0 \n" \
1161 " .word 0x00000812 \n" \
1170 unsigned long __treg; \
1172 __asm__ __volatile__( \
1175 " # mflo %0, $ac1 \n" \
1176 " .word 0x00200812 \n" \
1185 unsigned long __treg; \
1187 __asm__ __volatile__( \
1190 " # mflo %0, $ac2 \n" \
1191 " .word 0x00400812 \n" \
1200 unsigned long __treg; \
1202 __asm__ __volatile__( \
1205 " # mflo %0, $ac3 \n" \
1206 " .word 0x00600812 \n" \
1215 __asm__ __volatile__( \
1219 " # mthi $1, $ac0 \n" \
1220 " .word 0x00200011 \n" \
1228 __asm__ __volatile__( \
1232 " # mthi $1, $ac1 \n" \
1233 " .word 0x00200811 \n" \
1241 __asm__ __volatile__( \
1245 " # mthi $1, $ac2 \n" \
1246 " .word 0x00201011 \n" \
1254 __asm__ __volatile__( \
1258 " # mthi $1, $ac3 \n" \
1259 " .word 0x00201811 \n" \
1267 __asm__ __volatile__( \
1271 " # mtlo $1, $ac0 \n" \
1272 " .word 0x00200013 \n" \
1280 __asm__ __volatile__( \
1284 " # mtlo $1, $ac1 \n" \
1285 " .word 0x00200813 \n" \
1293 __asm__ __volatile__( \
1297 " # mtlo $1, $ac2 \n" \
1298 " .word 0x00201013 \n" \
1306 __asm__ __volatile__( \
1310 " # mtlo $1, $ac3 \n" \
1311 " .word 0x00201813 \n" \
1322 * It is responsibility of the caller to take care of any TLB hazards.
1324 static inline void tlb_probe(void)
1326 __asm__ __volatile__(
1327 ".set noreorder\n\t"
1332 static inline void tlb_read(void)
1334 __asm__ __volatile__(
1335 ".set noreorder\n\t"
1340 static inline void tlb_write_indexed(void)
1342 __asm__ __volatile__(
1343 ".set noreorder\n\t"
1348 static inline void tlb_write_random(void)
1350 __asm__ __volatile__(
1351 ".set noreorder\n\t"
1357 * Manipulate bits in a c0 register.
1359 #define __BUILD_SET_C0(name) \
1360 static inline unsigned int \
1361 set_c0_##name(unsigned int set) \
1365 res = read_c0_##name(); \
1367 write_c0_##name(res); \
1372 static inline unsigned int \
1373 clear_c0_##name(unsigned int clear) \
1377 res = read_c0_##name(); \
1379 write_c0_##name(res); \
1384 static inline unsigned int \
1385 change_c0_##name(unsigned int change, unsigned int new) \
1389 res = read_c0_##name(); \
1391 res |= (new & change); \
1392 write_c0_##name(res); \
1397 __BUILD_SET_C0(status)
1398 __BUILD_SET_C0(cause)
1399 __BUILD_SET_C0(config)
1400 __BUILD_SET_C0(intcontrol)
1401 __BUILD_SET_C0(intctl)
1402 __BUILD_SET_C0(srsmap)
1404 #endif /* !__ASSEMBLY__ */
1406 #endif /* _ASM_MIPSREGS_H */