include/asm-mips/system.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
   7  * Copyright (C) 1996 by Paul M. Antoine
   8  * Copyright (C) 1999 Silicon Graphics
   9  * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.
  11  */
  12 #ifndef _ASM_SYSTEM_H
  13 #define _ASM_SYSTEM_H
  14
  15 #include <linux/config.h>
  16 #include <linux/types.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/cpu-features.h>
  20 #include <asm/dsp.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/war.h>
  23 #include <asm/interrupt.h>
  24
  25 /*
  26  * read_barrier_depends - Flush all pending reads that subsequents reads
  27  * depend on.
  28  *
  29  * No data-dependent reads from memory-like regions are ever reordered
  30  * over this barrier.  All reads preceding this primitive are guaranteed
  31  * to access memory (but not necessarily other CPUs' caches) before any
  32  * reads following this primitive that depend on the data return by
  33  * any of the preceding reads.  This primitive is much lighter weight than
  34  * rmb() on most CPUs, and is never heavier weight than is
  35  * rmb().
  36  *
  37  * These ordering constraints are respected by both the local CPU
  38  * and the compiler.
  39  *
  40  * Ordering is not guaranteed by anything other than these primitives,
  41  * not even by data dependencies.  See the documentation for
  42  * memory_barrier() for examples and URLs to more information.
  43  *
  44  * For example, the following code would force ordering (the initial
  45  * value of "a" is zero, "b" is one, and "p" is "&a"):
  46  *
  47  * <programlisting>
  48  *      CPU 0                           CPU 1
  49  *
  50  *      b = 2;
  51  *      memory_barrier();
  52  *      p = &b;                         q = p;
  53  *                                      read_barrier_depends();
  54  *                                      d = *q;
  55  * </programlisting>
  56  *
  57  * because the read of "*q" depends on the read of "p" and these
  58  * two reads are separated by a read_barrier_depends().  However,
  59  * the following code, with the same initial values for "a" and "b":
  60  *
  61  * <programlisting>
  62  *      CPU 0                           CPU 1
  63  *
  64  *      a = 2;
  65  *      memory_barrier();
  66  *      b = 3;                          y = b;
  67  *                                      read_barrier_depends();
  68  *                                      x = a;
  69  * </programlisting>
  70  *
  71  * does not enforce ordering, since there is no data dependency between
  72  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
  73  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
  74  * in cases like thiswhere there are no data dependencies.
  75  */
  76
  77 #define read_barrier_depends()  do { } while(0)
  78
  79 #ifdef CONFIG_CPU_HAS_SYNC
  80 #define __sync()                                \
  81         __asm__ __volatile__(                   \
  82                 ".set   push\n\t"               \
  83                 ".set   noreorder\n\t"          \
  84                 ".set   mips2\n\t"              \
  85                 "sync\n\t"                      \
  86                 ".set   pop"                    \
  87                 : /* no output */               \
  88                 : /* no input */                \
  89                 : "memory")
  90 #else
  91 #define __sync()        do { } while(0)
  92 #endif
  93
  94 #define __fast_iob()                            \
  95         __asm__ __volatile__(                   \
  96                 ".set   push\n\t"               \
  97                 ".set   noreorder\n\t"          \
  98                 "lw     $0,%0\n\t"              \
  99                 "nop\n\t"                       \
 100                 ".set   pop"                    \
 101                 : /* no output */               \
 102                 : "m" (*(int *)CKSEG1)          \
 103                 : "memory")
 104
 105 #define fast_wmb()      __sync()
 106 #define fast_rmb()      __sync()
 107 #define fast_mb()       __sync()
 108 #define fast_iob()                              \
 109         do {                                    \
 110                 __sync();                       \
 111                 __fast_iob();                   \
 112         } while (0)
 113
 114 #ifdef CONFIG_CPU_HAS_WB
 115
 116 #include <asm/wbflush.h>
 117
 118 #define wmb()           fast_wmb()
 119 #define rmb()           fast_rmb()
 120 #define mb()            wbflush()
 121 #define iob()           wbflush()
 122
 123 #else /* !CONFIG_CPU_HAS_WB */
 124
 125 #define wmb()           fast_wmb()
 126 #define rmb()           fast_rmb()
 127 #define mb()            fast_mb()
 128 #define iob()           fast_iob()
 129
 130 #endif /* !CONFIG_CPU_HAS_WB */
 131
 132 #ifdef CONFIG_SMP
 133 #define smp_mb()        mb()
 134 #define smp_rmb()       rmb()
 135 #define smp_wmb()       wmb()
 136 #define smp_read_barrier_depends()      read_barrier_depends()
 137 #else
 138 #define smp_mb()        barrier()
 139 #define smp_rmb()       barrier()
 140 #define smp_wmb()       barrier()
 141 #define smp_read_barrier_depends()      do { } while(0)
 142 #endif
 143
 144 #define set_mb(var, value) \
 145 do { var = value; mb(); } while (0)
 146
 147 #define set_wmb(var, value) \
 148 do { var = value; wmb(); } while (0)
 149
 150 /*
 151  * switch_to(n) should switch tasks to task nr n, first
 152  * checking that n isn't the current task, in which case it does nothing.
 153  */
 154 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
 155
 156 struct task_struct;
 157
 158 #define switch_to(prev,next,last)                                       \
 159 do {                                                                    \
 160         if (cpu_has_dsp)                                                \
 161                 __save_dsp(prev);                                       \
 162         (last) = resume(prev, next, next->thread_info);                 \
 163         if (cpu_has_dsp)                                                \
 164                 __restore_dsp(current);                                 \
 165 } while(0)
 166
 167 #define ROT_IN_PIECES                                                   \
 168         "       .set    noreorder       \n"                             \
 169         "       .set    reorder         \n"
 170
 171 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 172 {
 173         __u32 retval;
 174
 175         if (cpu_has_llsc && R10000_LLSC_WAR) {
 176                 unsigned long dummy;
 177
 178                 __asm__ __volatile__(
 179                 "       .set    mips3                                   \n"
 180                 "1:     ll      %0, %3                  # xchg_u32      \n"
 181                 "       .set    mips0                                   \n"
 182                 "       move    %2, %z4                                 \n"
 183                 "       .set    mips3                                   \n"
 184                 "       sc      %2, %1                                  \n"
 185                 "       beqzl   %2, 1b                                  \n"
 186                 ROT_IN_PIECES
 187 #ifdef CONFIG_SMP
 188                 "       sync                                            \n"
 189 #endif
 190                 "       .set    mips0                                   \n"
 191                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 192                 : "R" (*m), "Jr" (val)
 193                 : "memory");
 194         } else if (cpu_has_llsc) {
 195                 unsigned long dummy;
 196
 197                 __asm__ __volatile__(
 198                 "       .set    mips3                                   \n"
 199                 "1:     ll      %0, %3                  # xchg_u32      \n"
 200                 "       .set    mips0                                   \n"
 201                 "       move    %2, %z4                                 \n"
 202                 "       .set    mips3                                   \n"
 203                 "       sc      %2, %1                                  \n"
 204                 "       beqz    %2, 1b                                  \n"
 205 #ifdef CONFIG_SMP
 206                 "       sync                                            \n"
 207 #endif
 208                 "       .set    mips0                                   \n"
 209                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 210                 : "R" (*m), "Jr" (val)
 211                 : "memory");
 212         } else {
 213                 unsigned long flags;
 214
 215                 local_irq_save(flags);
 216                 retval = *m;
 217                 *m = val;
 218                 local_irq_restore(flags);       /* implies memory barrier  */
 219         }
 220
 221         return retval;
 222 }
 223
 224 #ifdef CONFIG_64BIT
 225 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 226 {
 227         __u64 retval;
 228
 229         if (cpu_has_llsc && R10000_LLSC_WAR) {
 230                 unsigned long dummy;
 231
 232                 __asm__ __volatile__(
 233                 "       .set    mips3                                   \n"
 234                 "1:     lld     %0, %3                  # xchg_u64      \n"
 235                 "       move    %2, %z4                                 \n"
 236                 "       scd     %2, %1                                  \n"
 237                 "       beqzl   %2, 1b                                  \n"
 238                 ROT_IN_PIECES
 239 #ifdef CONFIG_SMP
 240                 "       sync                                            \n"
 241 #endif
 242                 "       .set    mips0                                   \n"
 243                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 244                 : "R" (*m), "Jr" (val)
 245                 : "memory");
 246         } else if (cpu_has_llsc) {
 247                 unsigned long dummy;
 248
 249                 __asm__ __volatile__(
 250                 "       .set    mips3                                   \n"
 251                 "1:     lld     %0, %3                  # xchg_u64      \n"
 252                 "       move    %2, %z4                                 \n"
 253                 "       scd     %2, %1                                  \n"
 254                 "       beqz    %2, 1b                                  \n"
 255 #ifdef CONFIG_SMP
 256                 "       sync                                            \n"
 257 #endif
 258                 "       .set    mips0                                   \n"
 259                 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
 260                 : "R" (*m), "Jr" (val)
 261                 : "memory");
 262         } else {
 263                 unsigned long flags;
 264
 265                 local_irq_save(flags);
 266                 retval = *m;
 267                 *m = val;
 268                 local_irq_restore(flags);       /* implies memory barrier  */
 269         }
 270
 271         return retval;
 272 }
 273 #else
 274 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
 275 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
 276 #endif
 277
 278 /* This function doesn't exist, so you'll get a linker error
 279    if something tries to do an invalid xchg().  */
 280 extern void __xchg_called_with_bad_pointer(void);
 281
 282 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 283 {
 284         switch (size) {
 285                 case 4:
 286                         return __xchg_u32(ptr, x);
 287                 case 8:
 288                         return __xchg_u64(ptr, x);
 289         }
 290         __xchg_called_with_bad_pointer();
 291         return x;
 292 }
 293
 294 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 295 #define tas(ptr) (xchg((ptr),1))
 296
 297 #define __HAVE_ARCH_CMPXCHG 1
 298
 299 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 300         unsigned long new)
 301 {
 302         __u32 retval;
 303
 304         if (cpu_has_llsc && R10000_LLSC_WAR) {
 305                 __asm__ __volatile__(
 306                 "       .set    push                                    \n"
 307                 "       .set    noat                                    \n"
 308                 "       .set    mips3                                   \n"
 309                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 310                 "       bne     %0, %z3, 2f                             \n"
 311                 "       move    $1, %z4                                 \n"
 312                 "       sc      $1, %1                                  \n"
 313                 "       beqzl   $1, 1b                                  \n"
 314                 ROT_IN_PIECES
 315 #ifdef CONFIG_SMP
 316                 "       sync                                            \n"
 317 #endif
 318                 "2:                                                     \n"
 319                 "       .set    pop                                     \n"
 320                 : "=&r" (retval), "=m" (*m)
 321                 : "R" (*m), "Jr" (old), "Jr" (new)
 322                 : "memory");
 323         } else if (cpu_has_llsc) {
 324                 __asm__ __volatile__(
 325                 "       .set    push                                    \n"
 326                 "       .set    noat                                    \n"
 327                 "       .set    mips3                                   \n"
 328                 "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
 329                 "       bne     %0, %z3, 2f                             \n"
 330                 "       move    $1, %z4                                 \n"
 331                 "       sc      $1, %1                                  \n"
 332                 "       beqz    $1, 1b                                  \n"
 333 #ifdef CONFIG_SMP
 334                 "       sync                                            \n"
 335 #endif
 336                 "2:                                                     \n"
 337                 "       .set    pop                                     \n"
 338                 : "=&r" (retval), "=m" (*m)
 339                 : "R" (*m), "Jr" (old), "Jr" (new)
 340                 : "memory");
 341         } else {
 342                 unsigned long flags;
 343
 344                 local_irq_save(flags);
 345                 retval = *m;
 346                 if (retval == old)
 347                         *m = new;
 348                 local_irq_restore(flags);       /* implies memory barrier  */
 349         }
 350
 351         return retval;
 352 }
 353
 354 #ifdef CONFIG_64BIT
 355 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 356         unsigned long new)
 357 {
 358         __u64 retval;
 359
 360         if (cpu_has_llsc) {
 361                 __asm__ __volatile__(
 362                 "       .set    push                                    \n"
 363                 "       .set    noat                                    \n"
 364                 "       .set    mips3                                   \n"
 365                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 366                 "       bne     %0, %z3, 2f                             \n"
 367                 "       move    $1, %z4                                 \n"
 368                 "       scd     $1, %1                                  \n"
 369                 "       beqzl   $1, 1b                                  \n"
 370                 ROT_IN_PIECES
 371 #ifdef CONFIG_SMP
 372                 "       sync                                            \n"
 373 #endif
 374                 "2:                                                     \n"
 375                 "       .set    pop                                     \n"
 376                 : "=&r" (retval), "=m" (*m)
 377                 : "R" (*m), "Jr" (old), "Jr" (new)
 378                 : "memory");
 379         } else if (cpu_has_llsc) {
 380                 __asm__ __volatile__(
 381                 "       .set    push                                    \n"
 382                 "       .set    noat                                    \n"
 383                 "       .set    mips3                                   \n"
 384                 "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
 385                 "       bne     %0, %z3, 2f                             \n"
 386                 "       move    $1, %z4                                 \n"
 387                 "       scd     $1, %1                                  \n"
 388                 "       beqz    $1, 1b                                  \n"
 389 #ifdef CONFIG_SMP
 390                 "       sync                                            \n"
 391 #endif
 392                 "2:                                                     \n"
 393                 "       .set    pop                                     \n"
 394                 : "=&r" (retval), "=m" (*m)
 395                 : "R" (*m), "Jr" (old), "Jr" (new)
 396                 : "memory");
 397         } else {
 398                 unsigned long flags;
 399
 400                 local_irq_save(flags);
 401                 retval = *m;
 402                 if (retval == old)
 403                         *m = new;
 404                 local_irq_restore(flags);       /* implies memory barrier  */
 405         }
 406
 407         return retval;
 408 }
 409 #else
 410 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
 411         volatile int * m, unsigned long old, unsigned long new);
 412 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
 413 #endif
 414
 415 /* This function doesn't exist, so you'll get a linker error
 416    if something tries to do an invalid cmpxchg().  */
 417 extern void __cmpxchg_called_with_bad_pointer(void);
 418
 419 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 420         unsigned long new, int size)
 421 {
 422         switch (size) {
 423         case 4:
 424                 return __cmpxchg_u32(ptr, old, new);
 425         case 8:
 426                 return __cmpxchg_u64(ptr, old, new);
 427         }
 428         __cmpxchg_called_with_bad_pointer();
 429         return old;
 430 }
 431
 432 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
 433
 434 extern void *set_except_vector(int n, void *addr);
 435 extern void per_cpu_trap_init(void);
 436
 437 extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file,
 438         const char *func, unsigned long line) ATTRIB_NORET;
 439 extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
 440         const char *func, unsigned long line);
 441
 442 #define die(msg, regs)                                                  \
 443         __die(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
 444 #define die_if_kernel(msg, regs)                                        \
 445         __die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
 446
 447 extern int stop_a_enabled;
 448
 449 /*
 450  * See include/asm-ia64/system.h; prevents deadlock on SMP
 451  * systems.
 452  */
 453 #define __ARCH_WANT_UNLOCKED_CTXSW
 454
 455 #define arch_align_stack(x) (x)
 456
 457 #endif /* _ASM_SYSTEM_H */