include/asm-x86/apicdef.h

   1 #ifndef _ASM_X86_APICDEF_H
   2 #define _ASM_X86_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define APIC_ID         0x20
  14
  15 #ifdef CONFIG_X86_64
  16 # define        APIC_ID_MASK            (0xFFu<<24)
  17 # define        GET_APIC_ID(x)          (((x)>>24)&0xFFu)
  18 # define        SET_APIC_ID(x)          (((x)<<24))
  19 #endif
  20
  21 #define APIC_LVR        0x30
  22 #define         APIC_LVR_MASK           0xFF00FF
  23 #define         GET_APIC_VERSION(x)     ((x)&0xFFu)
  24 #define         GET_APIC_MAXLVT(x)      (((x)>>16)&0xFFu)
  25 #define         APIC_INTEGRATED(x)      ((x)&0xF0u)
  26 #define         APIC_XAPIC(x)           ((x) >= 0x14)
  27 #define APIC_TASKPRI    0x80
  28 #define         APIC_TPRI_MASK          0xFFu
  29 #define APIC_ARBPRI     0x90
  30 #define         APIC_ARBPRI_MASK        0xFFu
  31 #define APIC_PROCPRI    0xA0
  32 #define APIC_EOI        0xB0
  33 #define         APIC_EIO_ACK            0x0
  34 #define APIC_RRR        0xC0
  35 #define APIC_LDR        0xD0
  36 #define         APIC_LDR_MASK           (0xFFu<<24)
  37 #define         GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFFu)
  38 #define         SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  39 #define         APIC_ALL_CPUS           0xFFu
  40 #define APIC_DFR        0xE0
  41 #define         APIC_DFR_CLUSTER                0x0FFFFFFFul
  42 #define         APIC_DFR_FLAT                   0xFFFFFFFFul
  43 #define APIC_SPIV       0xF0
  44 #define         APIC_SPIV_FOCUS_DISABLED        (1<<9)
  45 #define         APIC_SPIV_APIC_ENABLED          (1<<8)
  46 #define APIC_ISR        0x100
  47 #define APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
  48 #define APIC_TMR        0x180
  49 #define APIC_IRR        0x200
  50 #define APIC_ESR        0x280
  51 #define         APIC_ESR_SEND_CS        0x00001
  52 #define         APIC_ESR_RECV_CS        0x00002
  53 #define         APIC_ESR_SEND_ACC       0x00004
  54 #define         APIC_ESR_RECV_ACC       0x00008
  55 #define         APIC_ESR_SENDILL        0x00020
  56 #define         APIC_ESR_RECVILL        0x00040
  57 #define         APIC_ESR_ILLREGA        0x00080
  58 #define APIC_ICR        0x300
  59 #define         APIC_DEST_SELF          0x40000
  60 #define         APIC_DEST_ALLINC        0x80000
  61 #define         APIC_DEST_ALLBUT        0xC0000
  62 #define         APIC_ICR_RR_MASK        0x30000
  63 #define         APIC_ICR_RR_INVALID     0x00000
  64 #define         APIC_ICR_RR_INPROG      0x10000
  65 #define         APIC_ICR_RR_VALID       0x20000
  66 #define         APIC_INT_LEVELTRIG      0x08000
  67 #define         APIC_INT_ASSERT         0x04000
  68 #define         APIC_ICR_BUSY           0x01000
  69 #define         APIC_DEST_LOGICAL       0x00800
  70 #define         APIC_DEST_PHYSICAL      0x00000
  71 #define         APIC_DM_FIXED           0x00000
  72 #define         APIC_DM_LOWEST          0x00100
  73 #define         APIC_DM_SMI             0x00200
  74 #define         APIC_DM_REMRD           0x00300
  75 #define         APIC_DM_NMI             0x00400
  76 #define         APIC_DM_INIT            0x00500
  77 #define         APIC_DM_STARTUP         0x00600
  78 #define         APIC_DM_EXTINT          0x00700
  79 #define         APIC_VECTOR_MASK        0x000FF
  80 #define APIC_ICR2       0x310
  81 #define         GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  82 #define         SET_APIC_DEST_FIELD(x)  ((x)<<24)
  83 #define APIC_LVTT       0x320
  84 #define APIC_LVTTHMR    0x330
  85 #define APIC_LVTPC      0x340
  86 #define APIC_LVT0       0x350
  87 #define         APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  88 #define         GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  89 #define         SET_APIC_TIMER_BASE(x)          (((x)<<18))
  90 #define         APIC_TIMER_BASE_CLKIN           0x0
  91 #define         APIC_TIMER_BASE_TMBASE          0x1
  92 #define         APIC_TIMER_BASE_DIV             0x2
  93 #define         APIC_LVT_TIMER_PERIODIC         (1<<17)
  94 #define         APIC_LVT_MASKED                 (1<<16)
  95 #define         APIC_LVT_LEVEL_TRIGGER          (1<<15)
  96 #define         APIC_LVT_REMOTE_IRR             (1<<14)
  97 #define         APIC_INPUT_POLARITY             (1<<13)
  98 #define         APIC_SEND_PENDING               (1<<12)
  99 #define         APIC_MODE_MASK                  0x700
 100 #define         GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
 101 #define         SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
 102 #define                 APIC_MODE_FIXED         0x0
 103 #define                 APIC_MODE_NMI           0x4
 104 #define                 APIC_MODE_EXTINT        0x7
 105 #define APIC_LVT1       0x360
 106 #define APIC_LVTERR     0x370
 107 #define APIC_TMICT      0x380
 108 #define APIC_TMCCT      0x390
 109 #define APIC_TDCR       0x3E0
 110 #define         APIC_TDR_DIV_TMBASE     (1<<2)
 111 #define         APIC_TDR_DIV_1          0xB
 112 #define         APIC_TDR_DIV_2          0x0
 113 #define         APIC_TDR_DIV_4          0x1
 114 #define         APIC_TDR_DIV_8          0x2
 115 #define         APIC_TDR_DIV_16         0x3
 116 #define         APIC_TDR_DIV_32         0x8
 117 #define         APIC_TDR_DIV_64         0x9
 118 #define         APIC_TDR_DIV_128        0xA
 119 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 120
 121 #ifdef CONFIG_X86_32
 122 # define MAX_IO_APICS 64
 123 #else
 124 # define MAX_IO_APICS 128
 125 # define MAX_LOCAL_APIC 256
 126 #endif
 127
 128 /*
 129  * All x86-64 systems are xAPIC compatible.
 130  * In the following, "apicid" is a physical APIC ID.
 131  */
 132 #define XAPIC_DEST_CPUS_SHIFT   4
 133 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
 134 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
 135 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
 136 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
 137 #define APIC_CPUID(apicid)      ((apicid) & XAPIC_DEST_CPUS_MASK)
 138 #define NUM_APIC_CLUSTERS       ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 139
 140 /*
 141  * the local APIC register structure, memory mapped. Not terribly well
 142  * tested, but we might eventually use this one in the future - the
 143  * problem why we cannot use it right now is the P5 APIC, it has an
 144  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 145  */
 146 #define u32 unsigned int
 147
 148 struct local_apic {
 149
 150 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 151
 152 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 153
 154 /*020*/ struct { /* APIC ID Register */
 155                 u32   __reserved_1      : 24,
 156                         phys_apic_id    :  4,
 157                         __reserved_2    :  4;
 158                 u32 __reserved[3];
 159         } id;
 160
 161 /*030*/ const
 162         struct { /* APIC Version Register */
 163                 u32   version           :  8,
 164                         __reserved_1    :  8,
 165                         max_lvt         :  8,
 166                         __reserved_2    :  8;
 167                 u32 __reserved[3];
 168         } version;
 169
 170 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 171
 172 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 173
 174 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 175
 176 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 177
 178 /*080*/ struct { /* Task Priority Register */
 179                 u32   priority  :  8,
 180                         __reserved_1    : 24;
 181                 u32 __reserved_2[3];
 182         } tpr;
 183
 184 /*090*/ const
 185         struct { /* Arbitration Priority Register */
 186                 u32   priority  :  8,
 187                         __reserved_1    : 24;
 188                 u32 __reserved_2[3];
 189         } apr;
 190
 191 /*0A0*/ const
 192         struct { /* Processor Priority Register */
 193                 u32   priority  :  8,
 194                         __reserved_1    : 24;
 195                 u32 __reserved_2[3];
 196         } ppr;
 197
 198 /*0B0*/ struct { /* End Of Interrupt Register */
 199                 u32   eoi;
 200                 u32 __reserved[3];
 201         } eoi;
 202
 203 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 204
 205 /*0D0*/ struct { /* Logical Destination Register */
 206                 u32   __reserved_1      : 24,
 207                         logical_dest    :  8;
 208                 u32 __reserved_2[3];
 209         } ldr;
 210
 211 /*0E0*/ struct { /* Destination Format Register */
 212                 u32   __reserved_1      : 28,
 213                         model           :  4;
 214                 u32 __reserved_2[3];
 215         } dfr;
 216
 217 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 218                 u32     spurious_vector :  8,
 219                         apic_enabled    :  1,
 220                         focus_cpu       :  1,
 221                         __reserved_2    : 22;
 222                 u32 __reserved_3[3];
 223         } svr;
 224
 225 /*100*/ struct { /* In Service Register */
 226 /*170*/         u32 bitfield;
 227                 u32 __reserved[3];
 228         } isr [8];
 229
 230 /*180*/ struct { /* Trigger Mode Register */
 231 /*1F0*/         u32 bitfield;
 232                 u32 __reserved[3];
 233         } tmr [8];
 234
 235 /*200*/ struct { /* Interrupt Request Register */
 236 /*270*/         u32 bitfield;
 237                 u32 __reserved[3];
 238         } irr [8];
 239
 240 /*280*/ union { /* Error Status Register */
 241                 struct {
 242                         u32   send_cs_error                     :  1,
 243                                 receive_cs_error                :  1,
 244                                 send_accept_error               :  1,
 245                                 receive_accept_error            :  1,
 246                                 __reserved_1                    :  1,
 247                                 send_illegal_vector             :  1,
 248                                 receive_illegal_vector          :  1,
 249                                 illegal_register_address        :  1,
 250                                 __reserved_2                    : 24;
 251                         u32 __reserved_3[3];
 252                 } error_bits;
 253                 struct {
 254                         u32 errors;
 255                         u32 __reserved_3[3];
 256                 } all_errors;
 257         } esr;
 258
 259 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 260
 261 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 262
 263 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 264
 265 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 266
 267 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 268
 269 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 270
 271 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 272
 273 /*300*/ struct { /* Interrupt Command Register 1 */
 274                 u32   vector                    :  8,
 275                         delivery_mode           :  3,
 276                         destination_mode        :  1,
 277                         delivery_status         :  1,
 278                         __reserved_1            :  1,
 279                         level                   :  1,
 280                         trigger                 :  1,
 281                         __reserved_2            :  2,
 282                         shorthand               :  2,
 283                         __reserved_3            :  12;
 284                 u32 __reserved_4[3];
 285         } icr1;
 286
 287 /*310*/ struct { /* Interrupt Command Register 2 */
 288                 union {
 289                         u32   __reserved_1      : 24,
 290                                 phys_dest       :  4,
 291                                 __reserved_2    :  4;
 292                         u32   __reserved_3      : 24,
 293                                 logical_dest    :  8;
 294                 } dest;
 295                 u32 __reserved_4[3];
 296         } icr2;
 297
 298 /*320*/ struct { /* LVT - Timer */
 299                 u32   vector            :  8,
 300                         __reserved_1    :  4,
 301                         delivery_status :  1,
 302                         __reserved_2    :  3,
 303                         mask            :  1,
 304                         timer_mode      :  1,
 305                         __reserved_3    : 14;
 306                 u32 __reserved_4[3];
 307         } lvt_timer;
 308
 309 /*330*/ struct { /* LVT - Thermal Sensor */
 310                 u32  vector             :  8,
 311                         delivery_mode   :  3,
 312                         __reserved_1    :  1,
 313                         delivery_status :  1,
 314                         __reserved_2    :  3,
 315                         mask            :  1,
 316                         __reserved_3    : 15;
 317                 u32 __reserved_4[3];
 318         } lvt_thermal;
 319
 320 /*340*/ struct { /* LVT - Performance Counter */
 321                 u32   vector            :  8,
 322                         delivery_mode   :  3,
 323                         __reserved_1    :  1,
 324                         delivery_status :  1,
 325                         __reserved_2    :  3,
 326                         mask            :  1,
 327                         __reserved_3    : 15;
 328                 u32 __reserved_4[3];
 329         } lvt_pc;
 330
 331 /*350*/ struct { /* LVT - LINT0 */
 332                 u32   vector            :  8,
 333                         delivery_mode   :  3,
 334                         __reserved_1    :  1,
 335                         delivery_status :  1,
 336                         polarity        :  1,
 337                         remote_irr      :  1,
 338                         trigger         :  1,
 339                         mask            :  1,
 340                         __reserved_2    : 15;
 341                 u32 __reserved_3[3];
 342         } lvt_lint0;
 343
 344 /*360*/ struct { /* LVT - LINT1 */
 345                 u32   vector            :  8,
 346                         delivery_mode   :  3,
 347                         __reserved_1    :  1,
 348                         delivery_status :  1,
 349                         polarity        :  1,
 350                         remote_irr      :  1,
 351                         trigger         :  1,
 352                         mask            :  1,
 353                         __reserved_2    : 15;
 354                 u32 __reserved_3[3];
 355         } lvt_lint1;
 356
 357 /*370*/ struct { /* LVT - Error */
 358                 u32   vector            :  8,
 359                         __reserved_1    :  4,
 360                         delivery_status :  1,
 361                         __reserved_2    :  3,
 362                         mask            :  1,
 363                         __reserved_3    : 15;
 364                 u32 __reserved_4[3];
 365         } lvt_error;
 366
 367 /*380*/ struct { /* Timer Initial Count Register */
 368                 u32   initial_count;
 369                 u32 __reserved_2[3];
 370         } timer_icr;
 371
 372 /*390*/ const
 373         struct { /* Timer Current Count Register */
 374                 u32   curr_count;
 375                 u32 __reserved_2[3];
 376         } timer_ccr;
 377
 378 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 379
 380 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 381
 382 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 383
 384 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 385
 386 /*3E0*/ struct { /* Timer Divide Configuration Register */
 387                 u32   divisor           :  4,
 388                         __reserved_1    : 28;
 389                 u32 __reserved_2[3];
 390         } timer_dcr;
 391
 392 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 393
 394 } __attribute__ ((packed));
 395
 396 #undef u32
 397
 398 #define BAD_APICID 0xFFu
 399
 400 #endif