5 #include <asm/desc_defs.h>
10 static inline void fill_ldt(struct desc_struct *desc, struct user_desc *info)
12 desc->limit0 = info->limit & 0x0ffff;
13 desc->base0 = info->base_addr & 0x0000ffff;
15 desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
16 desc->type = (info->read_exec_only ^ 1) << 1;
17 desc->type |= info->contents << 2;
20 desc->p = info->seg_not_present ^ 1;
21 desc->limit = (info->limit & 0xf0000) >> 16;
22 desc->avl = info->useable;
23 desc->d = info->seg_32bit;
24 desc->g = info->limit_in_pages;
25 desc->base2 = (info->base_addr & 0xff000000) >> 24;
28 extern struct desc_ptr idt_descr;
29 extern gate_desc idt_table[];
32 extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
33 extern struct desc_ptr cpu_gdt_descr[];
34 /* the cpu gdt accessor */
35 #define get_cpu_gdt_table(x) ((struct desc_struct *)cpu_gdt_descr[x].address)
37 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
38 unsigned dpl, unsigned ist, unsigned seg)
40 gate->offset_low = PTR_LOW(func);
41 gate->segment = __KERNEL_CS;
48 gate->offset_middle = PTR_MIDDLE(func);
49 gate->offset_high = PTR_HIGH(func);
54 struct desc_struct gdt[GDT_ENTRIES];
55 } __attribute__((aligned(PAGE_SIZE)));
56 DECLARE_PER_CPU(struct gdt_page, gdt_page);
58 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
60 return per_cpu(gdt_page, cpu).gdt;
63 static inline void pack_gate(gate_desc *gate, unsigned char type,
64 unsigned long base, unsigned dpl, unsigned flags, unsigned short seg)
67 gate->a = (seg << 16) | (base & 0xffff);
68 gate->b = (base & 0xffff0000) |
69 (((0x80 | type | (dpl << 5)) & 0xff) << 8);
74 static inline int desc_empty(const void *ptr)
76 const u32 *desc = ptr;
77 return !(desc[0] | desc[1]);
80 #ifdef CONFIG_PARAVIRT
81 #include <asm/paravirt.h>
83 #define load_TR_desc() native_load_tr_desc()
84 #define load_gdt(dtr) native_load_gdt(dtr)
85 #define load_idt(dtr) native_load_idt(dtr)
86 #define load_tr(tr) __asm__ __volatile("ltr %0"::"m" (tr))
87 #define load_ldt(ldt) __asm__ __volatile("lldt %0"::"m" (ldt))
89 #define store_gdt(dtr) native_store_gdt(dtr)
90 #define store_idt(dtr) native_store_idt(dtr)
91 #define store_tr(tr) (tr = native_store_tr())
92 #define store_ldt(ldt) __asm__ ("sldt %0":"=m" (ldt))
94 #define load_TLS(t, cpu) native_load_tls(t, cpu)
95 #define set_ldt native_set_ldt
97 #define write_ldt_entry(dt, entry, desc) \
98 native_write_ldt_entry(dt, entry, desc)
99 #define write_gdt_entry(dt, entry, desc, type) \
100 native_write_gdt_entry(dt, entry, desc, type)
101 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
104 static inline void native_write_idt_entry(gate_desc *idt, int entry,
105 const gate_desc *gate)
107 memcpy(&idt[entry], gate, sizeof(*gate));
110 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
113 memcpy(&ldt[entry], desc, 8);
116 static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
117 const void *desc, int type)
122 size = sizeof(tss_desc);
125 size = sizeof(ldt_desc);
128 size = sizeof(struct desc_struct);
131 memcpy(&gdt[entry], desc, size);
134 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
135 unsigned long limit, unsigned char type,
138 desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
139 desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
140 (limit & 0x000f0000) | ((type & 0xff) << 8) |
141 ((flags & 0xf) << 20);
146 static inline void set_tssldt_descriptor(void *d, unsigned long addr,
147 unsigned type, unsigned size)
150 struct ldttss_desc64 *desc = d;
151 memset(desc, 0, sizeof(*desc));
152 desc->limit0 = size & 0xFFFF;
153 desc->base0 = PTR_LOW(addr);
154 desc->base1 = PTR_MIDDLE(addr) & 0xFF;
157 desc->limit1 = (size >> 16) & 0xF;
158 desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
159 desc->base3 = PTR_HIGH(addr);
162 pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
166 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
168 struct desc_struct *d = get_cpu_gdt_table(cpu);
172 * sizeof(unsigned long) coming from an extra "long" at the end
173 * of the iobitmap. See tss_struct definition in processor.h
175 * -1? seg base+limit should be pointing to the address of the
178 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
179 IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1);
180 write_gdt_entry(d, entry, &tss, DESC_TSS);
183 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
185 static inline void native_set_ldt(const void *addr, unsigned int entries)
187 if (likely(entries == 0))
188 __asm__ __volatile__("lldt %w0"::"q" (0));
190 unsigned cpu = smp_processor_id();
193 set_tssldt_descriptor(&ldt, (unsigned long)addr,
194 DESC_LDT, entries * sizeof(ldt) - 1);
195 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
197 __asm__ __volatile__("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
201 static inline void native_load_tr_desc(void)
203 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
206 static inline void native_load_gdt(const struct desc_ptr *dtr)
208 asm volatile("lgdt %0"::"m" (*dtr));
211 static inline void native_load_idt(const struct desc_ptr *dtr)
213 asm volatile("lidt %0"::"m" (*dtr));
216 static inline void native_store_gdt(struct desc_ptr *dtr)
218 asm volatile("sgdt %0":"=m" (*dtr));
221 static inline void native_store_idt(struct desc_ptr *dtr)
223 asm volatile("sidt %0":"=m" (*dtr));
226 static inline unsigned long native_store_tr(void)
229 asm volatile("str %0":"=r" (tr));
233 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
236 struct desc_struct *gdt = get_cpu_gdt_table(cpu);
238 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
239 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
242 #define _LDT_empty(info) (\
243 (info)->base_addr == 0 && \
244 (info)->limit == 0 && \
245 (info)->contents == 0 && \
246 (info)->read_exec_only == 1 && \
247 (info)->seg_32bit == 0 && \
248 (info)->limit_in_pages == 0 && \
249 (info)->seg_not_present == 1 && \
250 (info)->useable == 0)
253 #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
255 #define LDT_empty(info) (_LDT_empty(info))
258 static inline void clear_LDT(void)
264 * load one particular LDT into the current CPU
266 static inline void load_LDT_nolock(mm_context_t *pc)
268 set_ldt(pc->ldt, pc->size);
271 static inline void load_LDT(mm_context_t *pc)
278 static inline unsigned long get_desc_base(struct desc_struct *desc)
280 return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
282 static inline void _set_gate(int gate, unsigned type, void *addr,
283 unsigned dpl, unsigned ist, unsigned seg)
286 pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
288 * does not need to be atomic because it is only done once at
291 write_idt_entry(idt_table, gate, &s);
295 * This needs to use 'idt_table' rather than 'idt', and
296 * thus use the _nonmapped_ version of the IDT, as the
297 * Pentium F0 0F bugfix can have resulted in the mapped
298 * IDT being write-protected.
300 static inline void set_intr_gate(unsigned int n, void *addr)
302 BUG_ON((unsigned)n > 0xFF);
303 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
307 * This routine sets up an interrupt gate at directory privilege level 3.
309 static inline void set_system_intr_gate(unsigned int n, void *addr)
311 BUG_ON((unsigned)n > 0xFF);
312 _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
315 static inline void set_trap_gate(unsigned int n, void *addr)
317 BUG_ON((unsigned)n > 0xFF);
318 _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
321 static inline void set_system_gate(unsigned int n, void *addr)
323 BUG_ON((unsigned)n > 0xFF);
325 _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
327 _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
331 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
333 BUG_ON((unsigned)n > 0xFF);
334 _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
337 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
339 BUG_ON((unsigned)n > 0xFF);
340 _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
343 static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
345 BUG_ON((unsigned)n > 0xFF);
346 _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
351 * GET_DESC_BASE reads the descriptor base of the specified segment.
354 * idx - descriptor index
356 * base - 32bit register to which the base will be written
357 * lo_w - lo word of the "base" register
358 * lo_b - lo byte of the "base" register
359 * hi_b - hi byte of the low word of the "base" register
362 * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
363 * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
365 #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
366 movb idx*8+4(gdt), lo_b; \
367 movb idx*8+7(gdt), hi_b; \
369 movw idx*8+2(gdt), lo_w;
372 #endif /* __ASSEMBLY__ */