9 int domain; /* PCI domain */
10 int node; /* NUMA node */
11 void* iommu; /* IOMMU private data */
14 extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
16 static inline int pci_domain_nr(struct pci_bus *bus)
18 struct pci_sysdata *sd = bus->sysdata;
22 static inline int pci_proc_domain(struct pci_bus *bus)
24 return pci_domain_nr(bus);
27 #ifdef CONFIG_CALGARY_IOMMU
28 static inline void* pci_iommu(struct pci_bus *bus)
30 struct pci_sysdata *sd = bus->sysdata;
34 static inline void set_pci_iommu(struct pci_bus *bus, void *val)
36 struct pci_sysdata *sd = bus->sysdata;
39 #endif /* CONFIG_CALGARY_IOMMU */
41 #include <linux/mm.h> /* for struct page */
43 /* Can be used to override the logic in pci_scan_bus for skipping
44 already-configured bus numbers - to be used for buggy BIOSes
45 or architectures with incomplete PCI setup by the loader */
48 extern unsigned int pcibios_assign_all_busses(void);
50 #define pcibios_assign_all_busses() 0
52 #define pcibios_scan_all_fns(a, b) 0
54 extern unsigned long pci_mem_start;
55 #define PCIBIOS_MIN_IO 0x1000
56 #define PCIBIOS_MIN_MEM (pci_mem_start)
58 #define PCIBIOS_MIN_CARDBUS_IO 0x4000
60 void pcibios_config_init(void);
61 struct pci_bus * pcibios_scan_root(int bus);
62 extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
63 extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
65 void pcibios_set_master(struct pci_dev *dev);
66 void pcibios_penalize_isa_irq(int irq, int active);
67 struct irq_routing_table *pcibios_get_irq_routing_table(void);
68 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
70 #include <linux/types.h>
71 #include <linux/slab.h>
72 #include <asm/scatterlist.h>
73 #include <linux/string.h>
76 extern void pci_iommu_alloc(void);
77 extern int iommu_setup(char *opt);
79 /* The PCI address space does equal the physical memory
80 * address space. The networking and block device layers use
81 * this boolean for bounce buffer decisions
83 * On AMD64 it mostly equals, but we set it to zero if a hardware
84 * IOMMU (gart) of sotware IOMMU (swiotlb) is available.
86 #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
88 #if defined(CONFIG_IOMMU) || defined(CONFIG_CALGARY_IOMMU)
90 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
92 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
94 #define pci_unmap_addr(PTR, ADDR_NAME) \
96 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
97 (((PTR)->ADDR_NAME) = (VAL))
98 #define pci_unmap_len(PTR, LEN_NAME) \
100 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
101 (((PTR)->LEN_NAME) = (VAL))
106 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
107 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
108 #define pci_unmap_addr(PTR, ADDR_NAME) (0)
109 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
110 #define pci_unmap_len(PTR, LEN_NAME) (0)
111 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
115 #include <asm-generic/pci-dma-compat.h>
118 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
119 enum pci_dma_burst_strategy *strat,
120 unsigned long *strategy_parameter)
122 *strat = PCI_DMA_BURST_INFINITY;
123 *strategy_parameter = ~0UL;
127 #define HAVE_PCI_MMAP
128 extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
129 enum pci_mmap_state mmap_state, int write_combine);
131 #endif /* __KERNEL__ */
133 /* generic pci stuff */
135 #include <asm-generic/pci.h>
138 #endif /* __x8664_PCI_H */