1 #ifndef ASM_X86__PROCESSOR_H
2 #define ASM_X86__PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/init.h>
32 * Default implementation of macro that returns current
33 * instruction pointer ("program counter").
35 static inline void *current_text_addr(void)
39 asm volatile("mov $1f, %0; 1:":"=r" (pc));
44 #ifdef CONFIG_X86_VSMP
45 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
46 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
48 # define ARCH_MIN_TASKALIGN 16
49 # define ARCH_MIN_MMSTRUCT_ALIGN 0
53 * CPU type and hardware bug flags. Kept separately for each CPU.
54 * Members of this structure are referenced in head.S, so think twice
55 * before touching them. [mj]
59 __u8 x86; /* CPU family */
60 __u8 x86_vendor; /* CPU vendor */
64 char wp_works_ok; /* It doesn't on 386's */
66 /* Problems on some 486Dx4's and old 386's: */
75 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
80 /* CPUID returned core id bits: */
82 /* Max extended CPUID function supported: */
83 __u32 extended_cpuid_level;
84 /* Maximum supported CPUID level, -1=no CPUID: */
86 __u32 x86_capability[NCAPINTS];
87 char x86_vendor_id[16];
88 char x86_model_id[64];
89 /* in KB - valid for CPUS which support this call: */
91 int x86_cache_alignment; /* In bytes */
93 unsigned long loops_per_jiffy;
95 /* cpus sharing the last level cache: */
96 cpumask_t llc_shared_map;
98 /* cpuid returned max cores value: */
102 u16 x86_clflush_size;
104 /* number of cores as seen by the OS: */
106 /* Physical processor id: */
110 /* Index into per_cpu list: */
113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
115 #define X86_VENDOR_INTEL 0
116 #define X86_VENDOR_CYRIX 1
117 #define X86_VENDOR_AMD 2
118 #define X86_VENDOR_UMC 3
119 #define X86_VENDOR_CENTAUR 5
120 #define X86_VENDOR_TRANSMETA 7
121 #define X86_VENDOR_NSC 8
122 #define X86_VENDOR_NUM 9
124 #define X86_VENDOR_UNKNOWN 0xff
127 * capabilities of CPUs
129 extern struct cpuinfo_x86 boot_cpu_data;
130 extern struct cpuinfo_x86 new_cpu_data;
132 extern struct tss_struct doublefault_tss;
133 extern __u32 cleared_cpu_caps[NCAPINTS];
136 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
137 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
138 #define current_cpu_data __get_cpu_var(cpu_info)
140 #define cpu_data(cpu) boot_cpu_data
141 #define current_cpu_data boot_cpu_data
144 extern const struct seq_operations cpuinfo_op;
146 static inline int hlt_works(int cpu)
149 return cpu_data(cpu).hlt_works_ok;
155 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
157 extern void cpu_detect(struct cpuinfo_x86 *c);
159 extern struct pt_regs *idle_regs(struct pt_regs *);
161 extern void early_cpu_init(void);
162 extern void identify_boot_cpu(void);
163 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
164 extern void print_cpu_info(struct cpuinfo_x86 *);
165 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
166 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
167 extern unsigned short num_cache_leaves;
169 extern void detect_extended_topology(struct cpuinfo_x86 *c);
170 extern void detect_ht(struct cpuinfo_x86 *c);
172 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
173 unsigned int *ecx, unsigned int *edx)
175 /* ecx is often an input as well as an output. */
181 : "0" (*eax), "2" (*ecx));
184 static inline void load_cr3(pgd_t *pgdir)
186 write_cr3(__pa(pgdir));
190 /* This is the TSS defined by the hardware. */
192 unsigned short back_link, __blh;
194 unsigned short ss0, __ss0h;
196 /* ss1 caches MSR_IA32_SYSENTER_CS: */
197 unsigned short ss1, __ss1h;
199 unsigned short ss2, __ss2h;
211 unsigned short es, __esh;
212 unsigned short cs, __csh;
213 unsigned short ss, __ssh;
214 unsigned short ds, __dsh;
215 unsigned short fs, __fsh;
216 unsigned short gs, __gsh;
217 unsigned short ldt, __ldth;
218 unsigned short trace;
219 unsigned short io_bitmap_base;
221 } __attribute__((packed));
235 } __attribute__((packed)) ____cacheline_aligned;
241 #define IO_BITMAP_BITS 65536
242 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
243 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
244 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
245 #define INVALID_IO_BITMAP_OFFSET 0x8000
246 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
250 * The hardware state:
252 struct x86_hw_tss x86_tss;
255 * The extra 1 is there because the CPU will access an
256 * additional byte beyond the end of the IO permission
257 * bitmap. The extra byte must be all 1 bits, and must
258 * be within the limit.
260 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
262 * Cache the current maximum and the last task that used the bitmap:
264 unsigned long io_bitmap_max;
265 struct thread_struct *io_bitmap_owner;
268 * .. and then another 0x100 bytes for the emergency kernel stack:
270 unsigned long stack[64];
272 } ____cacheline_aligned;
274 DECLARE_PER_CPU(struct tss_struct, init_tss);
277 * Save the original ist values for checking stack pointers during debugging
280 unsigned long ist[7];
283 #define MXCSR_DEFAULT 0x1f80
285 struct i387_fsave_struct {
286 u32 cwd; /* FPU Control Word */
287 u32 swd; /* FPU Status Word */
288 u32 twd; /* FPU Tag Word */
289 u32 fip; /* FPU IP Offset */
290 u32 fcs; /* FPU IP Selector */
291 u32 foo; /* FPU Operand Pointer Offset */
292 u32 fos; /* FPU Operand Pointer Selector */
294 /* 8*10 bytes for each FP-reg = 80 bytes: */
297 /* Software status information [not touched by FSAVE ]: */
301 struct i387_fxsave_struct {
302 u16 cwd; /* Control Word */
303 u16 swd; /* Status Word */
304 u16 twd; /* Tag Word */
305 u16 fop; /* Last Instruction Opcode */
308 u64 rip; /* Instruction Pointer */
309 u64 rdp; /* Data Pointer */
312 u32 fip; /* FPU IP Offset */
313 u32 fcs; /* FPU IP Selector */
314 u32 foo; /* FPU Operand Offset */
315 u32 fos; /* FPU Operand Selector */
318 u32 mxcsr; /* MXCSR Register State */
319 u32 mxcsr_mask; /* MXCSR Mask */
321 /* 8*16 bytes for each FP-reg = 128 bytes: */
324 /* 16*16 bytes for each XMM-reg = 256 bytes: */
334 } __attribute__((aligned(16)));
336 struct i387_soft_struct {
344 /* 8*10 bytes for each FP-reg = 80 bytes: */
356 struct xsave_hdr_struct {
360 } __attribute__((packed));
362 struct xsave_struct {
363 struct i387_fxsave_struct i387;
364 struct xsave_hdr_struct xsave_hdr;
365 /* new processor state extensions will go here */
366 } __attribute__ ((packed, aligned (64)));
368 union thread_xstate {
369 struct i387_fsave_struct fsave;
370 struct i387_fxsave_struct fxsave;
371 struct i387_soft_struct soft;
372 struct xsave_struct xsave;
376 DECLARE_PER_CPU(struct orig_ist, orig_ist);
379 extern void print_cpu_info(struct cpuinfo_x86 *);
380 extern unsigned int xstate_size;
381 extern void free_thread_xstate(struct task_struct *);
382 extern struct kmem_cache *task_xstate_cachep;
383 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
384 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
385 extern unsigned short num_cache_leaves;
387 struct thread_struct {
388 /* Cached TLS descriptors: */
389 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
393 unsigned long sysenter_cs;
395 unsigned long usersp; /* Copy from PDA */
398 unsigned short fsindex;
399 unsigned short gsindex;
404 /* Hardware debugging registers: */
405 unsigned long debugreg0;
406 unsigned long debugreg1;
407 unsigned long debugreg2;
408 unsigned long debugreg3;
409 unsigned long debugreg6;
410 unsigned long debugreg7;
413 unsigned long trap_no;
414 unsigned long error_code;
415 /* floating point and extended processor state */
416 union thread_xstate *xstate;
418 /* Virtual 86 mode info */
419 struct vm86_struct __user *vm86_info;
420 unsigned long screen_bitmap;
421 unsigned long v86flags;
422 unsigned long v86mask;
423 unsigned long saved_sp0;
424 unsigned int saved_fs;
425 unsigned int saved_gs;
427 /* IO permissions: */
428 unsigned long *io_bitmap_ptr;
430 /* Max allowed port in the bitmap, in bytes: */
431 unsigned io_bitmap_max;
432 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
433 unsigned long debugctlmsr;
435 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
436 struct ds_context *ds_ctx;
437 #endif /* CONFIG_X86_DS */
438 #ifdef CONFIG_X86_PTRACE_BTS
439 /* the signal to send on a bts buffer overflow */
440 unsigned int bts_ovfl_signal;
441 #endif /* CONFIG_X86_PTRACE_BTS */
444 static inline unsigned long native_get_debugreg(int regno)
446 unsigned long val = 0; /* Damn you, gcc! */
450 asm("mov %%db0, %0" :"=r" (val));
453 asm("mov %%db1, %0" :"=r" (val));
456 asm("mov %%db2, %0" :"=r" (val));
459 asm("mov %%db3, %0" :"=r" (val));
462 asm("mov %%db6, %0" :"=r" (val));
465 asm("mov %%db7, %0" :"=r" (val));
473 static inline void native_set_debugreg(int regno, unsigned long value)
477 asm("mov %0, %%db0" ::"r" (value));
480 asm("mov %0, %%db1" ::"r" (value));
483 asm("mov %0, %%db2" ::"r" (value));
486 asm("mov %0, %%db3" ::"r" (value));
489 asm("mov %0, %%db6" ::"r" (value));
492 asm("mov %0, %%db7" ::"r" (value));
500 * Set IOPL bits in EFLAGS from given mask
502 static inline void native_set_iopl_mask(unsigned mask)
507 asm volatile ("pushfl;"
514 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
519 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
521 tss->x86_tss.sp0 = thread->sp0;
523 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
524 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
525 tss->x86_tss.ss1 = thread->sysenter_cs;
526 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
531 static inline void native_swapgs(void)
534 asm volatile("swapgs" ::: "memory");
538 #ifdef CONFIG_PARAVIRT
539 #include <asm/paravirt.h>
541 #define __cpuid native_cpuid
542 #define paravirt_enabled() 0
545 * These special macros can be used to get or set a debugging register
547 #define get_debugreg(var, register) \
548 (var) = native_get_debugreg(register)
549 #define set_debugreg(value, register) \
550 native_set_debugreg(register, value)
552 static inline void load_sp0(struct tss_struct *tss,
553 struct thread_struct *thread)
555 native_load_sp0(tss, thread);
558 #define set_iopl_mask native_set_iopl_mask
559 #endif /* CONFIG_PARAVIRT */
562 * Save the cr4 feature set we're using (ie
563 * Pentium 4MB enable and PPro Global page
564 * enable), so that any CPU's that boot up
565 * after us can get the correct flags.
567 extern unsigned long mmu_cr4_features;
569 static inline void set_in_cr4(unsigned long mask)
573 mmu_cr4_features |= mask;
579 static inline void clear_in_cr4(unsigned long mask)
583 mmu_cr4_features &= ~mask;
589 struct microcode_header {
597 unsigned int datasize;
598 unsigned int totalsize;
599 unsigned int reserved[3];
603 struct microcode_header hdr;
604 unsigned int bits[0];
607 typedef struct microcode microcode_t;
608 typedef struct microcode_header microcode_header_t;
610 /* microcode format is extended from prescott processors */
611 struct extended_signature {
617 struct extended_sigtable {
620 unsigned int reserved[3];
621 struct extended_signature sigs[0];
630 * create a kernel thread without removing it from tasklists
632 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
634 /* Free all resources held by a thread. */
635 extern void release_thread(struct task_struct *);
637 /* Prepare to copy thread state - unlazy all lazy state */
638 extern void prepare_to_copy(struct task_struct *tsk);
640 unsigned long get_wchan(struct task_struct *p);
643 * Generic CPUID function
644 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
645 * resulting in stale register contents being returned.
647 static inline void cpuid(unsigned int op,
648 unsigned int *eax, unsigned int *ebx,
649 unsigned int *ecx, unsigned int *edx)
653 __cpuid(eax, ebx, ecx, edx);
656 /* Some CPUID calls want 'count' to be placed in ecx */
657 static inline void cpuid_count(unsigned int op, int count,
658 unsigned int *eax, unsigned int *ebx,
659 unsigned int *ecx, unsigned int *edx)
663 __cpuid(eax, ebx, ecx, edx);
667 * CPUID functions returning a single datum
669 static inline unsigned int cpuid_eax(unsigned int op)
671 unsigned int eax, ebx, ecx, edx;
673 cpuid(op, &eax, &ebx, &ecx, &edx);
678 static inline unsigned int cpuid_ebx(unsigned int op)
680 unsigned int eax, ebx, ecx, edx;
682 cpuid(op, &eax, &ebx, &ecx, &edx);
687 static inline unsigned int cpuid_ecx(unsigned int op)
689 unsigned int eax, ebx, ecx, edx;
691 cpuid(op, &eax, &ebx, &ecx, &edx);
696 static inline unsigned int cpuid_edx(unsigned int op)
698 unsigned int eax, ebx, ecx, edx;
700 cpuid(op, &eax, &ebx, &ecx, &edx);
705 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
706 static inline void rep_nop(void)
708 asm volatile("rep; nop" ::: "memory");
711 static inline void cpu_relax(void)
716 /* Stop speculative execution: */
717 static inline void sync_core(void)
721 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
722 : "ebx", "ecx", "edx", "memory");
725 static inline void __monitor(const void *eax, unsigned long ecx,
728 /* "monitor %eax, %ecx, %edx;" */
729 asm volatile(".byte 0x0f, 0x01, 0xc8;"
730 :: "a" (eax), "c" (ecx), "d"(edx));
733 static inline void __mwait(unsigned long eax, unsigned long ecx)
735 /* "mwait %eax, %ecx;" */
736 asm volatile(".byte 0x0f, 0x01, 0xc9;"
737 :: "a" (eax), "c" (ecx));
740 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
743 /* "mwait %eax, %ecx;" */
744 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
745 :: "a" (eax), "c" (ecx));
748 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
750 extern void select_idle_routine(const struct cpuinfo_x86 *c);
752 extern unsigned long boot_option_idle_override;
753 extern unsigned long idle_halt;
754 extern unsigned long idle_nomwait;
757 * on systems with caches, caches must be flashed as the absolute
758 * last instruction before going into a suspended halt. Otherwise,
759 * dirty data can linger in the cache and become stale on resume,
760 * leading to strange errors.
762 * perform a variety of operations to guarantee that the compiler
763 * will not reorder instructions. wbinvd itself is serializing
764 * so the processor will not reorder.
766 * Systems without cache can just go into halt.
768 static inline void wbinvd_halt(void)
771 /* check for clflush to determine if wbinvd is legal */
773 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
779 extern void enable_sep_cpu(void);
780 extern int sysenter_setup(void);
782 /* Defined in head.S */
783 extern struct desc_ptr early_gdt_descr;
785 extern void cpu_set_gdt(int);
786 extern void switch_to_new_gdt(void);
787 extern void cpu_init(void);
788 extern void init_gdt(int cpu);
790 static inline void update_debugctlmsr(unsigned long debugctlmsr)
792 #ifndef CONFIG_X86_DEBUGCTLMSR
793 if (boot_cpu_data.x86 < 6)
796 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
800 * from system description table in BIOS. Mostly for MCA use, but
801 * others may find it useful:
803 extern unsigned int machine_id;
804 extern unsigned int machine_submodel_id;
805 extern unsigned int BIOS_revision;
807 /* Boot loader type from the setup header: */
808 extern int bootloader_type;
810 extern char ignore_fpu_irq;
812 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
813 #define ARCH_HAS_PREFETCHW
814 #define ARCH_HAS_SPINLOCK_PREFETCH
817 # define BASE_PREFETCH ASM_NOP4
818 # define ARCH_HAS_PREFETCH
820 # define BASE_PREFETCH "prefetcht0 (%1)"
824 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
826 * It's not worth to care about 3dnow prefetches for the K6
827 * because they are microcoded there and very slow.
829 static inline void prefetch(const void *x)
831 alternative_input(BASE_PREFETCH,
838 * 3dnow prefetch to get an exclusive cache line.
839 * Useful for spinlocks to avoid one state transition in the
840 * cache coherency protocol:
842 static inline void prefetchw(const void *x)
844 alternative_input(BASE_PREFETCH,
850 static inline void spin_lock_prefetch(const void *x)
857 * User space process size: 3GB (default).
859 #define TASK_SIZE PAGE_OFFSET
860 #define STACK_TOP TASK_SIZE
861 #define STACK_TOP_MAX STACK_TOP
863 #define INIT_THREAD { \
864 .sp0 = sizeof(init_stack) + (long)&init_stack, \
866 .sysenter_cs = __KERNEL_CS, \
867 .io_bitmap_ptr = NULL, \
868 .fs = __KERNEL_PERCPU, \
872 * Note that the .io_bitmap member must be extra-big. This is because
873 * the CPU will access an additional byte beyond the end of the IO
874 * permission bitmap. The extra byte must be all 1 bits, and must
875 * be within the limit.
879 .sp0 = sizeof(init_stack) + (long)&init_stack, \
880 .ss0 = __KERNEL_DS, \
881 .ss1 = __KERNEL_CS, \
882 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
884 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
887 extern unsigned long thread_saved_pc(struct task_struct *tsk);
889 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
890 #define KSTK_TOP(info) \
892 unsigned long *__ptr = (unsigned long *)(info); \
893 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
897 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
898 * This is necessary to guarantee that the entire "struct pt_regs"
899 * is accessable even if the CPU haven't stored the SS/ESP registers
900 * on the stack (interrupt gate does not save these registers
901 * when switching to the same priv ring).
902 * Therefore beware: accessing the ss/esp fields of the
903 * "struct pt_regs" is possible, but they may contain the
904 * completely wrong values.
906 #define task_pt_regs(task) \
908 struct pt_regs *__regs__; \
909 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
913 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
917 * User space process size. 47bits minus one guard page.
919 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
921 /* This decides where the kernel will search for a free chunk of vm
922 * space during mmap's.
924 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
925 0xc0000000 : 0xFFFFe000)
927 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
928 IA32_PAGE_OFFSET : TASK_SIZE64)
929 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
930 IA32_PAGE_OFFSET : TASK_SIZE64)
932 #define STACK_TOP TASK_SIZE
933 #define STACK_TOP_MAX TASK_SIZE64
935 #define INIT_THREAD { \
936 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
940 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
944 * Return saved PC of a blocked thread.
945 * What is this good for? it will be always the scheduler or ret_from_fork.
947 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
949 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
950 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
951 #endif /* CONFIG_X86_64 */
953 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
954 unsigned long new_sp);
957 * This decides where the kernel will search for a free chunk of vm
958 * space during mmap's.
960 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
962 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
964 /* Get/set a process' ability to use the timestamp counter instruction */
965 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
966 #define SET_TSC_CTL(val) set_tsc_mode((val))
968 extern int get_tsc_mode(unsigned long adr);
969 extern int set_tsc_mode(unsigned int val);
971 #endif /* ASM_X86__PROCESSOR_H */