1 #ifndef ASM_X86__PROCESSOR_H
2 #define ASM_X86__PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
24 #include <linux/personality.h>
25 #include <linux/cpumask.h>
26 #include <linux/cache.h>
27 #include <linux/threads.h>
28 #include <linux/init.h>
31 * Default implementation of macro that returns current
32 * instruction pointer ("program counter").
34 static inline void *current_text_addr(void)
38 asm volatile("mov $1f, %0; 1:":"=r" (pc));
43 #ifdef CONFIG_X86_VSMP
44 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
45 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
47 # define ARCH_MIN_TASKALIGN 16
48 # define ARCH_MIN_MMSTRUCT_ALIGN 0
52 * CPU type and hardware bug flags. Kept separately for each CPU.
53 * Members of this structure are referenced in head.S, so think twice
54 * before touching them. [mj]
58 __u8 x86; /* CPU family */
59 __u8 x86_vendor; /* CPU vendor */
63 char wp_works_ok; /* It doesn't on 386's */
65 /* Problems on some 486Dx4's and old 386's: */
74 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
78 /* CPUID returned core id bits: */
81 /* Max extended CPUID function supported: */
82 __u32 extended_cpuid_level;
83 /* Maximum supported CPUID level, -1=no CPUID: */
85 __u32 x86_capability[NCAPINTS];
86 char x86_vendor_id[16];
87 char x86_model_id[64];
88 /* in KB - valid for CPUS which support this call: */
90 int x86_cache_alignment; /* In bytes */
92 unsigned long loops_per_jiffy;
94 /* cpus sharing the last level cache: */
95 cpumask_t llc_shared_map;
97 /* cpuid returned max cores value: */
101 u16 x86_clflush_size;
103 /* number of cores as seen by the OS: */
105 /* Physical processor id: */
109 /* Index into per_cpu list: */
112 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
114 #define X86_VENDOR_INTEL 0
115 #define X86_VENDOR_CYRIX 1
116 #define X86_VENDOR_AMD 2
117 #define X86_VENDOR_UMC 3
118 #define X86_VENDOR_CENTAUR 5
119 #define X86_VENDOR_TRANSMETA 7
120 #define X86_VENDOR_NSC 8
121 #define X86_VENDOR_NUM 9
123 #define X86_VENDOR_UNKNOWN 0xff
126 * capabilities of CPUs
128 extern struct cpuinfo_x86 boot_cpu_data;
129 extern struct cpuinfo_x86 new_cpu_data;
131 extern struct tss_struct doublefault_tss;
132 extern __u32 cleared_cpu_caps[NCAPINTS];
135 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
136 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
137 #define current_cpu_data __get_cpu_var(cpu_info)
139 #define cpu_data(cpu) boot_cpu_data
140 #define current_cpu_data boot_cpu_data
143 extern const struct seq_operations cpuinfo_op;
145 static inline int hlt_works(int cpu)
148 return cpu_data(cpu).hlt_works_ok;
154 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
156 extern void cpu_detect(struct cpuinfo_x86 *c);
158 extern struct pt_regs *idle_regs(struct pt_regs *);
160 extern void early_cpu_init(void);
161 extern void identify_boot_cpu(void);
162 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
163 extern void print_cpu_info(struct cpuinfo_x86 *);
164 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
165 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
166 extern unsigned short num_cache_leaves;
168 extern void detect_extended_topology(struct cpuinfo_x86 *c);
169 #if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
170 extern void detect_ht(struct cpuinfo_x86 *c);
172 static inline void detect_ht(struct cpuinfo_x86 *c) {}
175 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
176 unsigned int *ecx, unsigned int *edx)
178 /* ecx is often an input as well as an output. */
184 : "0" (*eax), "2" (*ecx));
187 static inline void load_cr3(pgd_t *pgdir)
189 write_cr3(__pa(pgdir));
193 /* This is the TSS defined by the hardware. */
195 unsigned short back_link, __blh;
197 unsigned short ss0, __ss0h;
199 /* ss1 caches MSR_IA32_SYSENTER_CS: */
200 unsigned short ss1, __ss1h;
202 unsigned short ss2, __ss2h;
214 unsigned short es, __esh;
215 unsigned short cs, __csh;
216 unsigned short ss, __ssh;
217 unsigned short ds, __dsh;
218 unsigned short fs, __fsh;
219 unsigned short gs, __gsh;
220 unsigned short ldt, __ldth;
221 unsigned short trace;
222 unsigned short io_bitmap_base;
224 } __attribute__((packed));
238 } __attribute__((packed)) ____cacheline_aligned;
244 #define IO_BITMAP_BITS 65536
245 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
246 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
247 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
248 #define INVALID_IO_BITMAP_OFFSET 0x8000
249 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
253 * The hardware state:
255 struct x86_hw_tss x86_tss;
258 * The extra 1 is there because the CPU will access an
259 * additional byte beyond the end of the IO permission
260 * bitmap. The extra byte must be all 1 bits, and must
261 * be within the limit.
263 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
265 * Cache the current maximum and the last task that used the bitmap:
267 unsigned long io_bitmap_max;
268 struct thread_struct *io_bitmap_owner;
271 * .. and then another 0x100 bytes for the emergency kernel stack:
273 unsigned long stack[64];
275 } ____cacheline_aligned;
277 DECLARE_PER_CPU(struct tss_struct, init_tss);
280 * Save the original ist values for checking stack pointers during debugging
283 unsigned long ist[7];
286 #define MXCSR_DEFAULT 0x1f80
288 struct i387_fsave_struct {
289 u32 cwd; /* FPU Control Word */
290 u32 swd; /* FPU Status Word */
291 u32 twd; /* FPU Tag Word */
292 u32 fip; /* FPU IP Offset */
293 u32 fcs; /* FPU IP Selector */
294 u32 foo; /* FPU Operand Pointer Offset */
295 u32 fos; /* FPU Operand Pointer Selector */
297 /* 8*10 bytes for each FP-reg = 80 bytes: */
300 /* Software status information [not touched by FSAVE ]: */
304 struct i387_fxsave_struct {
305 u16 cwd; /* Control Word */
306 u16 swd; /* Status Word */
307 u16 twd; /* Tag Word */
308 u16 fop; /* Last Instruction Opcode */
311 u64 rip; /* Instruction Pointer */
312 u64 rdp; /* Data Pointer */
315 u32 fip; /* FPU IP Offset */
316 u32 fcs; /* FPU IP Selector */
317 u32 foo; /* FPU Operand Offset */
318 u32 fos; /* FPU Operand Selector */
321 u32 mxcsr; /* MXCSR Register State */
322 u32 mxcsr_mask; /* MXCSR Mask */
324 /* 8*16 bytes for each FP-reg = 128 bytes: */
327 /* 16*16 bytes for each XMM-reg = 256 bytes: */
337 } __attribute__((aligned(16)));
339 struct i387_soft_struct {
347 /* 8*10 bytes for each FP-reg = 80 bytes: */
359 struct xsave_hdr_struct {
363 } __attribute__((packed));
365 struct xsave_struct {
366 struct i387_fxsave_struct i387;
367 struct xsave_hdr_struct xsave_hdr;
368 /* new processor state extensions will go here */
369 } __attribute__ ((packed, aligned (64)));
371 union thread_xstate {
372 struct i387_fsave_struct fsave;
373 struct i387_fxsave_struct fxsave;
374 struct i387_soft_struct soft;
375 struct xsave_struct xsave;
379 DECLARE_PER_CPU(struct orig_ist, orig_ist);
382 extern void print_cpu_info(struct cpuinfo_x86 *);
383 extern unsigned int xstate_size;
384 extern void free_thread_xstate(struct task_struct *);
385 extern struct kmem_cache *task_xstate_cachep;
386 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
387 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
388 extern unsigned short num_cache_leaves;
390 struct thread_struct {
391 /* Cached TLS descriptors: */
392 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
396 unsigned long sysenter_cs;
398 unsigned long usersp; /* Copy from PDA */
401 unsigned short fsindex;
402 unsigned short gsindex;
407 /* Hardware debugging registers: */
408 unsigned long debugreg0;
409 unsigned long debugreg1;
410 unsigned long debugreg2;
411 unsigned long debugreg3;
412 unsigned long debugreg6;
413 unsigned long debugreg7;
416 unsigned long trap_no;
417 unsigned long error_code;
418 /* floating point and extended processor state */
419 union thread_xstate *xstate;
421 /* Virtual 86 mode info */
422 struct vm86_struct __user *vm86_info;
423 unsigned long screen_bitmap;
424 unsigned long v86flags;
425 unsigned long v86mask;
426 unsigned long saved_sp0;
427 unsigned int saved_fs;
428 unsigned int saved_gs;
430 /* IO permissions: */
431 unsigned long *io_bitmap_ptr;
433 /* Max allowed port in the bitmap, in bytes: */
434 unsigned io_bitmap_max;
435 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set. */
436 unsigned long debugctlmsr;
437 /* Debug Store - if not 0 points to a DS Save Area configuration;
438 * goes into MSR_IA32_DS_AREA */
439 unsigned long ds_area_msr;
442 static inline unsigned long native_get_debugreg(int regno)
444 unsigned long val = 0; /* Damn you, gcc! */
448 asm("mov %%db0, %0" :"=r" (val));
451 asm("mov %%db1, %0" :"=r" (val));
454 asm("mov %%db2, %0" :"=r" (val));
457 asm("mov %%db3, %0" :"=r" (val));
460 asm("mov %%db6, %0" :"=r" (val));
463 asm("mov %%db7, %0" :"=r" (val));
471 static inline void native_set_debugreg(int regno, unsigned long value)
475 asm("mov %0, %%db0" ::"r" (value));
478 asm("mov %0, %%db1" ::"r" (value));
481 asm("mov %0, %%db2" ::"r" (value));
484 asm("mov %0, %%db3" ::"r" (value));
487 asm("mov %0, %%db6" ::"r" (value));
490 asm("mov %0, %%db7" ::"r" (value));
498 * Set IOPL bits in EFLAGS from given mask
500 static inline void native_set_iopl_mask(unsigned mask)
505 asm volatile ("pushfl;"
512 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
517 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
519 tss->x86_tss.sp0 = thread->sp0;
521 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
522 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
523 tss->x86_tss.ss1 = thread->sysenter_cs;
524 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
529 static inline void native_swapgs(void)
532 asm volatile("swapgs" ::: "memory");
536 #ifdef CONFIG_PARAVIRT
537 #include <asm/paravirt.h>
539 #define __cpuid native_cpuid
540 #define paravirt_enabled() 0
543 * These special macros can be used to get or set a debugging register
545 #define get_debugreg(var, register) \
546 (var) = native_get_debugreg(register)
547 #define set_debugreg(value, register) \
548 native_set_debugreg(register, value)
550 static inline void load_sp0(struct tss_struct *tss,
551 struct thread_struct *thread)
553 native_load_sp0(tss, thread);
556 #define set_iopl_mask native_set_iopl_mask
557 #endif /* CONFIG_PARAVIRT */
560 * Save the cr4 feature set we're using (ie
561 * Pentium 4MB enable and PPro Global page
562 * enable), so that any CPU's that boot up
563 * after us can get the correct flags.
565 extern unsigned long mmu_cr4_features;
567 static inline void set_in_cr4(unsigned long mask)
571 mmu_cr4_features |= mask;
577 static inline void clear_in_cr4(unsigned long mask)
581 mmu_cr4_features &= ~mask;
587 struct microcode_header {
595 unsigned int datasize;
596 unsigned int totalsize;
597 unsigned int reserved[3];
601 struct microcode_header hdr;
602 unsigned int bits[0];
605 typedef struct microcode microcode_t;
606 typedef struct microcode_header microcode_header_t;
608 /* microcode format is extended from prescott processors */
609 struct extended_signature {
615 struct extended_sigtable {
618 unsigned int reserved[3];
619 struct extended_signature sigs[0];
628 * create a kernel thread without removing it from tasklists
630 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
632 /* Free all resources held by a thread. */
633 extern void release_thread(struct task_struct *);
635 /* Prepare to copy thread state - unlazy all lazy state */
636 extern void prepare_to_copy(struct task_struct *tsk);
638 unsigned long get_wchan(struct task_struct *p);
641 * Generic CPUID function
642 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
643 * resulting in stale register contents being returned.
645 static inline void cpuid(unsigned int op,
646 unsigned int *eax, unsigned int *ebx,
647 unsigned int *ecx, unsigned int *edx)
651 __cpuid(eax, ebx, ecx, edx);
654 /* Some CPUID calls want 'count' to be placed in ecx */
655 static inline void cpuid_count(unsigned int op, int count,
656 unsigned int *eax, unsigned int *ebx,
657 unsigned int *ecx, unsigned int *edx)
661 __cpuid(eax, ebx, ecx, edx);
665 * CPUID functions returning a single datum
667 static inline unsigned int cpuid_eax(unsigned int op)
669 unsigned int eax, ebx, ecx, edx;
671 cpuid(op, &eax, &ebx, &ecx, &edx);
676 static inline unsigned int cpuid_ebx(unsigned int op)
678 unsigned int eax, ebx, ecx, edx;
680 cpuid(op, &eax, &ebx, &ecx, &edx);
685 static inline unsigned int cpuid_ecx(unsigned int op)
687 unsigned int eax, ebx, ecx, edx;
689 cpuid(op, &eax, &ebx, &ecx, &edx);
694 static inline unsigned int cpuid_edx(unsigned int op)
696 unsigned int eax, ebx, ecx, edx;
698 cpuid(op, &eax, &ebx, &ecx, &edx);
703 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
704 static inline void rep_nop(void)
706 asm volatile("rep; nop" ::: "memory");
709 static inline void cpu_relax(void)
714 /* Stop speculative execution: */
715 static inline void sync_core(void)
719 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
720 : "ebx", "ecx", "edx", "memory");
723 static inline void __monitor(const void *eax, unsigned long ecx,
726 /* "monitor %eax, %ecx, %edx;" */
727 asm volatile(".byte 0x0f, 0x01, 0xc8;"
728 :: "a" (eax), "c" (ecx), "d"(edx));
731 static inline void __mwait(unsigned long eax, unsigned long ecx)
733 /* "mwait %eax, %ecx;" */
734 asm volatile(".byte 0x0f, 0x01, 0xc9;"
735 :: "a" (eax), "c" (ecx));
738 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
741 /* "mwait %eax, %ecx;" */
742 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
743 :: "a" (eax), "c" (ecx));
746 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
748 extern void select_idle_routine(const struct cpuinfo_x86 *c);
750 extern unsigned long boot_option_idle_override;
751 extern unsigned long idle_halt;
752 extern unsigned long idle_nomwait;
755 * on systems with caches, caches must be flashed as the absolute
756 * last instruction before going into a suspended halt. Otherwise,
757 * dirty data can linger in the cache and become stale on resume,
758 * leading to strange errors.
760 * perform a variety of operations to guarantee that the compiler
761 * will not reorder instructions. wbinvd itself is serializing
762 * so the processor will not reorder.
764 * Systems without cache can just go into halt.
766 static inline void wbinvd_halt(void)
769 /* check for clflush to determine if wbinvd is legal */
771 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
777 extern void enable_sep_cpu(void);
778 extern int sysenter_setup(void);
780 /* Defined in head.S */
781 extern struct desc_ptr early_gdt_descr;
783 extern void cpu_set_gdt(int);
784 extern void switch_to_new_gdt(void);
785 extern void cpu_init(void);
786 extern void init_gdt(int cpu);
788 static inline void update_debugctlmsr(unsigned long debugctlmsr)
790 #ifndef CONFIG_X86_DEBUGCTLMSR
791 if (boot_cpu_data.x86 < 6)
794 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
798 * from system description table in BIOS. Mostly for MCA use, but
799 * others may find it useful:
801 extern unsigned int machine_id;
802 extern unsigned int machine_submodel_id;
803 extern unsigned int BIOS_revision;
805 /* Boot loader type from the setup header: */
806 extern int bootloader_type;
808 extern char ignore_fpu_irq;
810 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
811 #define ARCH_HAS_PREFETCHW
812 #define ARCH_HAS_SPINLOCK_PREFETCH
815 # define BASE_PREFETCH ASM_NOP4
816 # define ARCH_HAS_PREFETCH
818 # define BASE_PREFETCH "prefetcht0 (%1)"
822 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
824 * It's not worth to care about 3dnow prefetches for the K6
825 * because they are microcoded there and very slow.
827 static inline void prefetch(const void *x)
829 alternative_input(BASE_PREFETCH,
836 * 3dnow prefetch to get an exclusive cache line.
837 * Useful for spinlocks to avoid one state transition in the
838 * cache coherency protocol:
840 static inline void prefetchw(const void *x)
842 alternative_input(BASE_PREFETCH,
848 static inline void spin_lock_prefetch(const void *x)
855 * User space process size: 3GB (default).
857 #define TASK_SIZE PAGE_OFFSET
858 #define STACK_TOP TASK_SIZE
859 #define STACK_TOP_MAX STACK_TOP
861 #define INIT_THREAD { \
862 .sp0 = sizeof(init_stack) + (long)&init_stack, \
864 .sysenter_cs = __KERNEL_CS, \
865 .io_bitmap_ptr = NULL, \
866 .fs = __KERNEL_PERCPU, \
870 * Note that the .io_bitmap member must be extra-big. This is because
871 * the CPU will access an additional byte beyond the end of the IO
872 * permission bitmap. The extra byte must be all 1 bits, and must
873 * be within the limit.
877 .sp0 = sizeof(init_stack) + (long)&init_stack, \
878 .ss0 = __KERNEL_DS, \
879 .ss1 = __KERNEL_CS, \
880 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
882 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
885 extern unsigned long thread_saved_pc(struct task_struct *tsk);
887 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
888 #define KSTK_TOP(info) \
890 unsigned long *__ptr = (unsigned long *)(info); \
891 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
895 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
896 * This is necessary to guarantee that the entire "struct pt_regs"
897 * is accessable even if the CPU haven't stored the SS/ESP registers
898 * on the stack (interrupt gate does not save these registers
899 * when switching to the same priv ring).
900 * Therefore beware: accessing the ss/esp fields of the
901 * "struct pt_regs" is possible, but they may contain the
902 * completely wrong values.
904 #define task_pt_regs(task) \
906 struct pt_regs *__regs__; \
907 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
911 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
915 * User space process size. 47bits minus one guard page.
917 #define TASK_SIZE64 ((1UL << 47) - PAGE_SIZE)
919 /* This decides where the kernel will search for a free chunk of vm
920 * space during mmap's.
922 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
923 0xc0000000 : 0xFFFFe000)
925 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
926 IA32_PAGE_OFFSET : TASK_SIZE64)
927 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
928 IA32_PAGE_OFFSET : TASK_SIZE64)
930 #define STACK_TOP TASK_SIZE
931 #define STACK_TOP_MAX TASK_SIZE64
933 #define INIT_THREAD { \
934 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
938 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
942 * Return saved PC of a blocked thread.
943 * What is this good for? it will be always the scheduler or ret_from_fork.
945 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
947 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
948 #define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
949 #endif /* CONFIG_X86_64 */
951 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
952 unsigned long new_sp);
955 * This decides where the kernel will search for a free chunk of vm
956 * space during mmap's.
958 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
960 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
962 /* Get/set a process' ability to use the timestamp counter instruction */
963 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
964 #define SET_TSC_CTL(val) set_tsc_mode((val))
966 extern int get_tsc_mode(unsigned long adr);
967 extern int set_tsc_mode(unsigned int val);
969 #endif /* ASM_X86__PROCESSOR_H */