2 * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
6 * Copyright (C) 2001 ARM Limited
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
12 #include <linux/config.h>
16 * CLCD Controller Internal Register addresses
18 #define CLCD_TIM0 0x00000000
19 #define CLCD_TIM1 0x00000004
20 #define CLCD_TIM2 0x00000008
21 #define CLCD_TIM3 0x0000000c
22 #define CLCD_UBAS 0x00000010
23 #define CLCD_LBAS 0x00000014
25 #if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
26 #define CLCD_IENB 0x00000018
27 #define CLCD_CNTL 0x0000001c
30 * Someone rearranged these two registers on the Versatile
33 #define CLCD_IENB 0x0000001c
34 #define CLCD_CNTL 0x00000018
37 #define CLCD_STAT 0x00000020
38 #define CLCD_INTR 0x00000024
39 #define CLCD_UCUR 0x00000028
40 #define CLCD_LCUR 0x0000002C
41 #define CLCD_PALL 0x00000200
42 #define CLCD_PALETTE 0x00000200
44 #define TIM2_CLKSEL (1 << 5)
45 #define TIM2_IVS (1 << 11)
46 #define TIM2_IHS (1 << 12)
47 #define TIM2_IPC (1 << 13)
48 #define TIM2_IOE (1 << 14)
49 #define TIM2_BCD (1 << 26)
51 #define CNTL_LCDEN (1 << 0)
52 #define CNTL_LCDBPP1 (0 << 1)
53 #define CNTL_LCDBPP2 (1 << 1)
54 #define CNTL_LCDBPP4 (2 << 1)
55 #define CNTL_LCDBPP8 (3 << 1)
56 #define CNTL_LCDBPP16 (4 << 1)
57 #define CNTL_LCDBPP16_565 (6 << 1)
58 #define CNTL_LCDBPP24 (5 << 1)
59 #define CNTL_LCDBW (1 << 4)
60 #define CNTL_LCDTFT (1 << 5)
61 #define CNTL_LCDMONO8 (1 << 6)
62 #define CNTL_LCDDUAL (1 << 7)
63 #define CNTL_BGR (1 << 8)
64 #define CNTL_BEBO (1 << 9)
65 #define CNTL_BEPO (1 << 10)
66 #define CNTL_LCDPWR (1 << 11)
67 #define CNTL_LCDVCOMP(x) ((x) << 12)
68 #define CNTL_LDMAFIFOTIME (1 << 15)
69 #define CNTL_WATERMARK (1 << 16)
72 struct fb_videomode mode;
73 signed short width; /* width in mm */
74 signed short height; /* height in mm */
81 unsigned int connector;
90 unsigned long pixclock;
96 * the board-type specific routines
102 * Optional. Check whether the var structure is acceptable
105 int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
108 * Compulsary. Decode fb->fb.var into regs->*. In the case of
109 * fixed timing, set regs->* to the register values required.
111 void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
114 * Optional. Disable any extra display hardware.
116 void (*disable)(struct clcd_fb *);
119 * Optional. Enable any extra display hardware.
121 void (*enable)(struct clcd_fb *);
124 * Setup platform specific parts of CLCD driver
126 int (*setup)(struct clcd_fb *);
129 * mmap the framebuffer memory
131 int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
134 * Remove platform specific parts of CLCD driver
136 void (*remove)(struct clcd_fb *);
142 /* this data structure describes each frame buffer device we find */
145 struct amba_device *dev;
147 struct clcd_panel *panel;
148 struct clcd_board *board;
155 static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
160 * Program the CLCD controller registers and start the CLCD
162 val = ((fb->fb.var.xres / 16) - 1) << 2;
163 val |= (fb->fb.var.hsync_len - 1) << 8;
164 val |= (fb->fb.var.right_margin - 1) << 16;
165 val |= (fb->fb.var.left_margin - 1) << 24;
168 val = fb->fb.var.yres;
169 if (fb->panel->cntl & CNTL_LCDDUAL)
172 val |= (fb->fb.var.vsync_len - 1) << 10;
173 val |= fb->fb.var.lower_margin << 16;
174 val |= fb->fb.var.upper_margin << 24;
177 val = fb->panel->tim2;
178 val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
179 val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
181 cpl = fb->fb.var.xres_virtual;
182 if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
184 else if (!fb->fb.var.grayscale) /* STN color */
186 else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
188 else /* STN monochrome, 4bit */
191 regs->tim2 = val | ((cpl - 1) << 16);
193 regs->tim3 = fb->panel->tim3;
195 val = fb->panel->cntl;
196 if (fb->fb.var.grayscale)
199 switch (fb->fb.var.bits_per_pixel) {
214 * PL110 cannot choose between 5551 and 565 modes in
215 * its control register
217 if ((fb->dev->periphid & 0x000fffff) == 0x00041110)
218 val |= CNTL_LCDBPP16;
219 else if (fb->fb.var.green.length == 5)
220 val |= CNTL_LCDBPP16;
222 val |= CNTL_LCDBPP16_565;
225 val |= CNTL_LCDBPP24;
230 regs->pixclock = fb->fb.var.pixclock;
233 static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
235 var->xres_virtual = var->xres = (var->xres + 15) & ~15;
236 var->yres_virtual = var->yres = (var->yres + 1) & ~1;
238 #define CHECK(e,l,h) (var->e < l || var->e > h)
239 if (CHECK(right_margin, (5+1), 256) || /* back porch */
240 CHECK(left_margin, (5+1), 256) || /* front porch */
241 CHECK(hsync_len, (5+1), 256) ||
243 var->lower_margin > 255 || /* back porch */
244 var->upper_margin > 255 || /* front porch */
245 var->vsync_len > 32 ||
250 /* single panel mode: PCD = max(PCD, 1) */
251 /* dual panel mode: PCD = max(PCD, 5) */
254 * You can't change the grayscale setting, and
255 * we can only do non-interlaced video.
257 if (var->grayscale != fb->fb.var.grayscale ||
258 (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
261 #define CHECK(e) (var->e != fb->fb.var.e)
262 if (fb->panel->fixedtimings &&
265 CHECK(bits_per_pixel) ||
267 CHECK(left_margin) ||
268 CHECK(right_margin) ||
269 CHECK(upper_margin) ||
270 CHECK(lower_margin) ||
278 var->accel_flags = 0;