1 #ifndef __SOUND_AD1848_H
2 #define __SOUND_AD1848_H
5 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
6 * Definitions for AD1847/AD1848/CS4248 chips
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/interrupt.h>
28 #include "wss.h" /* temporary till the driver is removed */
32 #define AD1848P( chip, x ) ( (chip) -> port + c_d_c_AD1848##x )
34 #define c_d_c_AD1848REGSEL 0
35 #define c_d_c_AD1848REG 1
36 #define c_d_c_AD1848STATUS 2
37 #define c_d_c_AD1848PIO 3
41 #define AD1848_LEFT_INPUT 0x00 /* left input control */
42 #define AD1848_RIGHT_INPUT 0x01 /* right input control */
43 #define AD1848_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
44 #define AD1848_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
45 #define AD1848_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
46 #define AD1848_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
47 #define AD1848_LEFT_OUTPUT 0x06 /* left output control register */
48 #define AD1848_RIGHT_OUTPUT 0x07 /* right output control register */
49 #define AD1848_DATA_FORMAT 0x08 /* clock and data format - playback/capture - bits 7-0 MCE */
50 #define AD1848_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
51 #define AD1848_PIN_CTRL 0x0a /* pin control */
52 #define AD1848_TEST_INIT 0x0b /* test and initialization */
53 #define AD1848_MISC_INFO 0x0c /* miscellaneous information */
54 #define AD1848_LOOPBACK 0x0d /* loopback control */
55 #define AD1848_DATA_UPR_CNT 0x0e /* playback/capture upper base count */
56 #define AD1848_DATA_LWR_CNT 0x0f /* playback/capture lower base count */
58 /* definitions for codec register select port - CODECP( REGSEL ) */
60 #define AD1848_INIT 0x80 /* CODEC is initializing */
61 #define AD1848_MCE 0x40 /* mode change enable */
62 #define AD1848_TRD 0x20 /* transfer request disable */
64 /* definitions for codec status register - CODECP( STATUS ) */
66 #define AD1848_GLOBALIRQ 0x01 /* IRQ is active */
68 /* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */
70 #define AD1848_ENABLE_MIC_GAIN 0x20
72 #define AD1848_MIXS_LINE1 0x00
73 #define AD1848_MIXS_AUX1 0x40
74 #define AD1848_MIXS_LINE2 0x80
75 #define AD1848_MIXS_ALL 0xc0
77 /* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */
79 #define AD1848_LINEAR_8 0x00 /* 8-bit unsigned data */
80 #define AD1848_ALAW_8 0x60 /* 8-bit A-law companded */
81 #define AD1848_ULAW_8 0x20 /* 8-bit U-law companded */
82 #define AD1848_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
83 #define AD1848_STEREO 0x10 /* stereo mode */
84 /* bits 3-1 define frequency divisor */
85 #define AD1848_XTAL1 0x00 /* 24.576 crystal */
86 #define AD1848_XTAL2 0x01 /* 16.9344 crystal */
88 /* definitions for interface control register - AD1848_IFACE_CTRL */
90 #define AD1848_CAPTURE_PIO 0x80 /* capture PIO enable */
91 #define AD1848_PLAYBACK_PIO 0x40 /* playback PIO enable */
92 #define AD1848_CALIB_MODE 0x18 /* calibration mode bits */
93 #define AD1848_AUTOCALIB 0x08 /* auto calibrate */
94 #define AD1848_SINGLE_DMA 0x04 /* use single DMA channel */
95 #define AD1848_CAPTURE_ENABLE 0x02 /* capture enable */
96 #define AD1848_PLAYBACK_ENABLE 0x01 /* playback enable */
98 /* definitions for pin control register - AD1848_PIN_CTRL */
100 #define AD1848_IRQ_ENABLE 0x02 /* enable IRQ */
101 #define AD1848_XCTL1 0x40 /* external control #1 */
102 #define AD1848_XCTL0 0x80 /* external control #0 */
104 /* definitions for test and init register - AD1848_TEST_INIT */
106 #define AD1848_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
107 #define AD1848_DMA_REQUEST 0x10 /* DMA request in progress */
109 /* IBM Thinkpad specific stuff */
110 #define AD1848_THINKPAD_CTL_PORT1 0x15e8
111 #define AD1848_THINKPAD_CTL_PORT2 0x15e9
112 #define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02
114 /* exported functions */
116 void snd_ad1848_out(struct snd_wss *chip, unsigned char reg,
117 unsigned char value);
119 int snd_ad1848_create(struct snd_card *card,
122 unsigned short hardware,
123 struct snd_wss **chip);
125 int snd_ad1848_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm);
126 const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction);
127 int snd_ad1848_mixer(struct snd_wss *chip);
129 /* exported mixer stuffs */
130 enum { AD1848_MIX_SINGLE, AD1848_MIX_DOUBLE, AD1848_MIX_CAPTURE };
132 #define AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) \
133 ((reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24))
134 #define AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) \
135 ((left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22))
137 /* for ease of use */
138 struct ad1848_mix_elem {
142 unsigned long private_value;
143 const unsigned int *tlv;
146 #define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
149 .type = AD1848_MIX_SINGLE, \
150 .private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) }
152 #define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
155 .type = AD1848_MIX_DOUBLE, \
156 .private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) }
158 int snd_ad1848_add_ctl_elem(struct snd_wss *chip,
159 const struct ad1848_mix_elem *c);
161 #endif /* __SOUND_AD1848_H */