sound/pci/ens1370.c

   1 /*
   2  *  Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
   3  *  Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
   4  *                   Thomas Sailer <sailer@ife.ee.ethz.ch>
   5  *
   6  *   This program is free software; you can redistribute it and/or modify
   7  *   it under the terms of the GNU General Public License as published by
   8  *   the Free Software Foundation; either version 2 of the License, or
   9  *   (at your option) any later version.
  10  *
  11  *   This program is distributed in the hope that it will be useful,
  12  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *   GNU General Public License for more details.
  15  *
  16  *   You should have received a copy of the GNU General Public License
  17  *   along with this program; if not, write to the Free Software
  18  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  19  *
  20  */
  21
  22 /* Power-Management-Code ( CONFIG_PM )
  23  * for ens1371 only ( FIXME )
  24  * derived from cs4281.c, atiixp.c and via82xx.c
  25  * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
  26  * by Kurt J. Bosch
  27  */
  28
  29 #include <sound/driver.h>
  30 #include <asm/io.h>
  31 #include <linux/delay.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/slab.h>
  36 #include <linux/gameport.h>
  37 #include <linux/moduleparam.h>
  38 #include <linux/mutex.h>
  39
  40 #include <sound/core.h>
  41 #include <sound/control.h>
  42 #include <sound/pcm.h>
  43 #include <sound/rawmidi.h>
  44 #ifdef CHIP1371
  45 #include <sound/ac97_codec.h>
  46 #else
  47 #include <sound/ak4531_codec.h>
  48 #endif
  49 #include <sound/initval.h>
  50 #include <sound/asoundef.h>
  51
  52 #ifndef CHIP1371
  53 #undef CHIP1370
  54 #define CHIP1370
  55 #endif
  56
  57 #ifdef CHIP1370
  58 #define DRIVER_NAME "ENS1370"
  59 #else
  60 #define DRIVER_NAME "ENS1371"
  61 #endif
  62
  63
  64 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
  65 MODULE_LICENSE("GPL");
  66 #ifdef CHIP1370
  67 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
  68 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
  69                 "{Creative Labs,SB PCI64/128 (ES1370)}}");
  70 #endif
  71 #ifdef CHIP1371
  72 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
  73 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
  74                 "{Ensoniq,AudioPCI ES1373},"
  75                 "{Creative Labs,Ectiva EV1938},"
  76                 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
  77                 "{Creative Labs,Vibra PCI128},"
  78                 "{Ectiva,EV1938}}");
  79 #endif
  80
  81 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  82 #define SUPPORT_JOYSTICK
  83 #endif
  84
  85 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  86 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  87 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;      /* Enable switches */
  88 #ifdef SUPPORT_JOYSTICK
  89 #ifdef CHIP1371
  90 static int joystick_port[SNDRV_CARDS];
  91 #else
  92 static int joystick[SNDRV_CARDS];
  93 #endif
  94 #endif
  95 #ifdef CHIP1371
  96 static int spdif[SNDRV_CARDS];
  97 static int lineio[SNDRV_CARDS];
  98 #endif
  99
 100 module_param_array(index, int, NULL, 0444);
 101 MODULE_PARM_DESC(index, "Index value for Ensoniq AudioPCI soundcard.");
 102 module_param_array(id, charp, NULL, 0444);
 103 MODULE_PARM_DESC(id, "ID string for Ensoniq AudioPCI soundcard.");
 104 module_param_array(enable, bool, NULL, 0444);
 105 MODULE_PARM_DESC(enable, "Enable Ensoniq AudioPCI soundcard.");
 106 #ifdef SUPPORT_JOYSTICK
 107 #ifdef CHIP1371
 108 module_param_array(joystick_port, int, NULL, 0444);
 109 MODULE_PARM_DESC(joystick_port, "Joystick port address.");
 110 #else
 111 module_param_array(joystick, bool, NULL, 0444);
 112 MODULE_PARM_DESC(joystick, "Enable joystick.");
 113 #endif
 114 #endif /* SUPPORT_JOYSTICK */
 115 #ifdef CHIP1371
 116 module_param_array(spdif, int, NULL, 0444);
 117 MODULE_PARM_DESC(spdif, "S/PDIF output (-1 = none, 0 = auto, 1 = force).");
 118 module_param_array(lineio, int, NULL, 0444);
 119 MODULE_PARM_DESC(lineio, "Line In to Rear Out (0 = auto, 1 = force).");
 120 #endif
 121
 122 /* ES1371 chip ID */
 123 /* This is a little confusing because all ES1371 compatible chips have the
 124    same DEVICE_ID, the only thing differentiating them is the REV_ID field.
 125    This is only significant if you want to enable features on the later parts.
 126    Yes, I know it's stupid and why didn't we use the sub IDs?
 127 */
 128 #define ES1371REV_ES1373_A  0x04
 129 #define ES1371REV_ES1373_B  0x06
 130 #define ES1371REV_CT5880_A  0x07
 131 #define CT5880REV_CT5880_C  0x02
 132 #define CT5880REV_CT5880_D  0x03        /* ??? -jk */
 133 #define CT5880REV_CT5880_E  0x04        /* mw */
 134 #define ES1371REV_ES1371_B  0x09
 135 #define EV1938REV_EV1938_A  0x00
 136 #define ES1371REV_ES1373_8  0x08
 137
 138 /*
 139  * Direct registers
 140  */
 141
 142 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
 143
 144 #define ES_REG_CONTROL  0x00    /* R/W: Interrupt/Chip select control register */
 145 #define   ES_1370_ADC_STOP      (1<<31)         /* disable capture buffer transfers */
 146 #define   ES_1370_XCTL1         (1<<30)         /* general purpose output bit */
 147 #define   ES_1373_BYPASS_P1     (1<<31)         /* bypass SRC for PB1 */
 148 #define   ES_1373_BYPASS_P2     (1<<30)         /* bypass SRC for PB2 */
 149 #define   ES_1373_BYPASS_R      (1<<29)         /* bypass SRC for REC */
 150 #define   ES_1373_TEST_BIT      (1<<28)         /* should be set to 0 for normal operation */
 151 #define   ES_1373_RECEN_B       (1<<27)         /* mix record with playback for I2S/SPDIF out */
 152 #define   ES_1373_SPDIF_THRU    (1<<26)         /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
 153 #define   ES_1371_JOY_ASEL(o)   (((o)&0x03)<<24)/* joystick port mapping */
 154 #define   ES_1371_JOY_ASELM     (0x03<<24)      /* mask for above */
 155 #define   ES_1371_JOY_ASELI(i)  (((i)>>24)&0x03)
 156 #define   ES_1371_GPIO_IN(i)    (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
 157 #define   ES_1370_PCLKDIVO(o)   (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
 158 #define   ES_1370_PCLKDIVM      ((0x1fff)<<16)  /* mask for above */
 159 #define   ES_1370_PCLKDIVI(i)   (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
 160 #define   ES_1371_GPIO_OUT(o)   (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
 161 #define   ES_1371_GPIO_OUTM     (0x0f<<16)      /* mask for above */
 162 #define   ES_MSFMTSEL           (1<<15)         /* MPEG serial data format; 0 = SONY, 1 = I2S */
 163 #define   ES_1370_M_SBB         (1<<14)         /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
 164 #define   ES_1371_SYNC_RES      (1<<14)         /* Warm AC97 reset */
 165 #define   ES_1370_WTSRSEL(o)    (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
 166 #define   ES_1370_WTSRSELM      (0x03<<12)      /* mask for above */
 167 #define   ES_1371_ADC_STOP      (1<<13)         /* disable CCB transfer capture information */
 168 #define   ES_1371_PWR_INTRM     (1<<12)         /* power level change interrupts enable */
 169 #define   ES_1370_DAC_SYNC      (1<<11)         /* DAC's are synchronous */
 170 #define   ES_1371_M_CB          (1<<11)         /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
 171 #define   ES_CCB_INTRM          (1<<10)         /* CCB voice interrupts enable */
 172 #define   ES_1370_M_CB          (1<<9)          /* capture clock source; 0 = ADC; 1 = MPEG */
 173 #define   ES_1370_XCTL0         (1<<8)          /* generap purpose output bit */
 174 #define   ES_1371_PDLEV(o)      (((o)&0x03)<<8) /* current power down level */
 175 #define   ES_1371_PDLEVM        (0x03<<8)       /* mask for above */
 176 #define   ES_BREQ               (1<<7)          /* memory bus request enable */
 177 #define   ES_DAC1_EN            (1<<6)          /* DAC1 playback channel enable */
 178 #define   ES_DAC2_EN            (1<<5)          /* DAC2 playback channel enable */
 179 #define   ES_ADC_EN             (1<<4)          /* ADC capture channel enable */
 180 #define   ES_UART_EN            (1<<3)          /* UART enable */
 181 #define   ES_JYSTK_EN           (1<<2)          /* Joystick module enable */
 182 #define   ES_1370_CDC_EN        (1<<1)          /* Codec interface enable */
 183 #define   ES_1371_XTALCKDIS     (1<<1)          /* Xtal clock disable */
 184 #define   ES_1370_SERR_DISABLE  (1<<0)          /* PCI serr signal disable */
 185 #define   ES_1371_PCICLKDIS     (1<<0)          /* PCI clock disable */
 186 #define ES_REG_STATUS   0x04    /* R/O: Interrupt/Chip select status register */
 187 #define   ES_INTR               (1<<31)         /* Interrupt is pending */
 188 #define   ES_1371_ST_AC97_RST   (1<<29)         /* CT5880 AC'97 Reset bit */
 189 #define   ES_1373_REAR_BIT27    (1<<27)         /* rear bits: 000 - front, 010 - mirror, 101 - separate */
 190 #define   ES_1373_REAR_BIT26    (1<<26)
 191 #define   ES_1373_REAR_BIT24    (1<<24)
 192 #define   ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
 193 #define   ES_1373_SPDIF_EN      (1<<18)         /* SPDIF enable */
 194 #define   ES_1373_SPDIF_TEST    (1<<17)         /* SPDIF test */
 195 #define   ES_1371_TEST          (1<<16)         /* test ASIC */
 196 #define   ES_1373_GPIO_INT(i)   (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
 197 #define   ES_1370_CSTAT         (1<<10)         /* CODEC is busy or register write in progress */
 198 #define   ES_1370_CBUSY         (1<<9)          /* CODEC is busy */
 199 #define   ES_1370_CWRIP         (1<<8)          /* CODEC register write in progress */
 200 #define   ES_1371_SYNC_ERR      (1<<8)          /* CODEC synchronization error occurred */
 201 #define   ES_1371_VC(i)         (((i)>>6)&0x03) /* voice code from CCB module */
 202 #define   ES_1370_VC(i)         (((i)>>5)&0x03) /* voice code from CCB module */
 203 #define   ES_1371_MPWR          (1<<5)          /* power level interrupt pending */
 204 #define   ES_MCCB               (1<<4)          /* CCB interrupt pending */
 205 #define   ES_UART               (1<<3)          /* UART interrupt pending */
 206 #define   ES_DAC1               (1<<2)          /* DAC1 channel interrupt pending */
 207 #define   ES_DAC2               (1<<1)          /* DAC2 channel interrupt pending */
 208 #define   ES_ADC                (1<<0)          /* ADC channel interrupt pending */
 209 #define ES_REG_UART_DATA 0x08   /* R/W: UART data register */
 210 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
 211 #define   ES_RXINT              (1<<7)          /* RX interrupt occurred */
 212 #define   ES_TXINT              (1<<2)          /* TX interrupt occurred */
 213 #define   ES_TXRDY              (1<<1)          /* transmitter ready */
 214 #define   ES_RXRDY              (1<<0)          /* receiver ready */
 215 #define ES_REG_UART_CONTROL 0x09        /* W/O: UART control register */
 216 #define   ES_RXINTEN            (1<<7)          /* RX interrupt enable */
 217 #define   ES_TXINTENO(o)        (((o)&0x03)<<5) /* TX interrupt enable */
 218 #define   ES_TXINTENM           (0x03<<5)       /* mask for above */
 219 #define   ES_TXINTENI(i)        (((i)>>5)&0x03)
 220 #define   ES_CNTRL(o)           (((o)&0x03)<<0) /* control */
 221 #define   ES_CNTRLM             (0x03<<0)       /* mask for above */
 222 #define ES_REG_UART_RES 0x0a    /* R/W: UART reserver register */
 223 #define   ES_TEST_MODE          (1<<0)          /* test mode enabled */
 224 #define ES_REG_MEM_PAGE 0x0c    /* R/W: Memory page register */
 225 #define   ES_MEM_PAGEO(o)       (((o)&0x0f)<<0) /* memory page select - out */
 226 #define   ES_MEM_PAGEM          (0x0f<<0)       /* mask for above */
 227 #define   ES_MEM_PAGEI(i)       (((i)>>0)&0x0f) /* memory page select - in */
 228 #define ES_REG_1370_CODEC 0x10  /* W/O: Codec write register address */
 229 #define   ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
 230 #define ES_REG_1371_CODEC 0x14  /* W/R: Codec Read/Write register address */
 231 #define   ES_1371_CODEC_RDY        (1<<31)      /* codec ready */
 232 #define   ES_1371_CODEC_WIP        (1<<30)      /* codec register access in progress */
 233 #define   ES_1371_CODEC_PIRD       (1<<23)      /* codec read/write select register */
 234 #define   ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
 235 #define   ES_1371_CODEC_READS(a)   ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
 236 #define   ES_1371_CODEC_READ(i)    (((i)>>0)&0xffff)
 237
 238 #define ES_REG_1371_SMPRATE 0x10        /* W/R: Codec rate converter interface register */
 239 #define   ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
 240 #define   ES_1371_SRC_RAM_ADDRM    (0x7f<<25)   /* mask for above */
 241 #define   ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
 242 #define   ES_1371_SRC_RAM_WE       (1<<24)      /* R/W: read/write control for sample rate converter */
 243 #define   ES_1371_SRC_RAM_BUSY     (1<<23)      /* R/O: sample rate memory is busy */
 244 #define   ES_1371_SRC_DISABLE      (1<<22)      /* sample rate converter disable */
 245 #define   ES_1371_DIS_P1           (1<<21)      /* playback channel 1 accumulator update disable */
 246 #define   ES_1371_DIS_P2           (1<<20)      /* playback channel 1 accumulator update disable */
 247 #define   ES_1371_DIS_R1           (1<<19)      /* capture channel accumulator update disable */
 248 #define   ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
 249 #define   ES_1371_SRC_RAM_DATAM    (0xffff<<0)  /* mask for above */
 250 #define   ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
 251
 252 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
 253 #define   ES_1371_JFAST         (1<<31)         /* fast joystick timing */
 254 #define   ES_1371_HIB           (1<<30)         /* host interrupt blocking enable */
 255 #define   ES_1371_VSB           (1<<29)         /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
 256 #define   ES_1371_VMPUO(o)      (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
 257 #define   ES_1371_VMPUM         (0x03<<27)      /* mask for above */
 258 #define   ES_1371_VMPUI(i)      (((i)>>27)&0x03)/* base register address */
 259 #define   ES_1371_VCDCO(o)      (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
 260 #define   ES_1371_VCDCM         (0x03<<25)      /* mask for above */
 261 #define   ES_1371_VCDCI(i)      (((i)>>25)&0x03)/* CODEC address */
 262 #define   ES_1371_FIRQ          (1<<24)         /* force an interrupt */
 263 #define   ES_1371_SDMACAP       (1<<23)         /* enable event capture for slave DMA controller */
 264 #define   ES_1371_SPICAP        (1<<22)         /* enable event capture for slave IRQ controller */
 265 #define   ES_1371_MDMACAP       (1<<21)         /* enable event capture for master DMA controller */
 266 #define   ES_1371_MPICAP        (1<<20)         /* enable event capture for master IRQ controller */
 267 #define   ES_1371_ADCAP         (1<<19)         /* enable event capture for ADLIB register; 0x388xH */
 268 #define   ES_1371_SVCAP         (1<<18)         /* enable event capture for SB registers */
 269 #define   ES_1371_CDCCAP        (1<<17)         /* enable event capture for CODEC registers */
 270 #define   ES_1371_BACAP         (1<<16)         /* enable event capture for SoundScape base address */
 271 #define   ES_1371_EXI(i)        (((i)>>8)&0x07) /* event number */
 272 #define   ES_1371_AI(i)         (((i)>>3)&0x1f) /* event significant I/O address */
 273 #define   ES_1371_WR            (1<<2)  /* event capture; 0 = read; 1 = write */
 274 #define   ES_1371_LEGINT        (1<<0)  /* interrupt for legacy events; 0 = interrupt did occur */
 275
 276 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
 277
 278 #define ES_REG_SERIAL   0x20    /* R/W: Serial interface control register */
 279 #define   ES_1371_DAC_TEST      (1<<22)         /* DAC test mode enable */
 280 #define   ES_P2_END_INCO(o)     (((o)&0x07)<<19)/* binary offset value to increment / loop end */
 281 #define   ES_P2_END_INCM        (0x07<<19)      /* mask for above */
 282 #define   ES_P2_END_INCI(i)     (((i)>>16)&0x07)/* binary offset value to increment / loop end */
 283 #define   ES_P2_ST_INCO(o)      (((o)&0x07)<<16)/* binary offset value to increment / start */
 284 #define   ES_P2_ST_INCM         (0x07<<16)      /* mask for above */
 285 #define   ES_P2_ST_INCI(i)      (((i)<<16)&0x07)/* binary offset value to increment / start */
 286 #define   ES_R1_LOOP_SEL        (1<<15)         /* ADC; 0 - loop mode; 1 = stop mode */
 287 #define   ES_P2_LOOP_SEL        (1<<14)         /* DAC2; 0 - loop mode; 1 = stop mode */
 288 #define   ES_P1_LOOP_SEL        (1<<13)         /* DAC1; 0 - loop mode; 1 = stop mode */
 289 #define   ES_P2_PAUSE           (1<<12)         /* DAC2; 0 - play mode; 1 = pause mode */
 290 #define   ES_P1_PAUSE           (1<<11)         /* DAC1; 0 - play mode; 1 = pause mode */
 291 #define   ES_R1_INT_EN          (1<<10)         /* ADC interrupt enable */
 292 #define   ES_P2_INT_EN          (1<<9)          /* DAC2 interrupt enable */
 293 #define   ES_P1_INT_EN          (1<<8)          /* DAC1 interrupt enable */
 294 #define   ES_P1_SCT_RLD         (1<<7)          /* force sample counter reload for DAC1 */
 295 #define   ES_P2_DAC_SEN         (1<<6)          /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
 296 #define   ES_R1_MODEO(o)        (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
 297 #define   ES_R1_MODEM           (0x03<<4)       /* mask for above */
 298 #define   ES_R1_MODEI(i)        (((i)>>4)&0x03)
 299 #define   ES_P2_MODEO(o)        (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
 300 #define   ES_P2_MODEM           (0x03<<2)       /* mask for above */
 301 #define   ES_P2_MODEI(i)        (((i)>>2)&0x03)
 302 #define   ES_P1_MODEO(o)        (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
 303 #define   ES_P1_MODEM           (0x03<<0)       /* mask for above */
 304 #define   ES_P1_MODEI(i)        (((i)>>0)&0x03)
 305
 306 #define ES_REG_DAC1_COUNT 0x24  /* R/W: DAC1 sample count register */
 307 #define ES_REG_DAC2_COUNT 0x28  /* R/W: DAC2 sample count register */
 308 #define ES_REG_ADC_COUNT  0x2c  /* R/W: ADC sample count register */
 309 #define   ES_REG_CURR_COUNT(i)  (((i)>>16)&0xffff)
 310 #define   ES_REG_COUNTO(o)      (((o)&0xffff)<<0)
 311 #define   ES_REG_COUNTM         (0xffff<<0)
 312 #define   ES_REG_COUNTI(i)      (((i)>>0)&0xffff)
 313
 314 #define ES_REG_DAC1_FRAME 0x30  /* R/W: PAGE 0x0c; DAC1 frame address */
 315 #define ES_REG_DAC1_SIZE  0x34  /* R/W: PAGE 0x0c; DAC1 frame size */
 316 #define ES_REG_DAC2_FRAME 0x38  /* R/W: PAGE 0x0c; DAC2 frame address */
 317 #define ES_REG_DAC2_SIZE  0x3c  /* R/W: PAGE 0x0c; DAC2 frame size */
 318 #define ES_REG_ADC_FRAME  0x30  /* R/W: PAGE 0x0d; ADC frame address */
 319 #define ES_REG_ADC_SIZE   0x34  /* R/W: PAGE 0x0d; ADC frame size */
 320 #define   ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
 321 #define   ES_REG_FCURR_COUNTM    (0xffff<<16)
 322 #define   ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
 323 #define   ES_REG_FSIZEO(o)       (((o)&0xffff)<<0)
 324 #define   ES_REG_FSIZEM          (0xffff<<0)
 325 #define   ES_REG_FSIZEI(i)       (((i)>>0)&0xffff)
 326 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
 327 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
 328
 329 #define ES_REG_UART_FIFO  0x30  /* R/W: PAGE 0x0e; UART FIFO register */
 330 #define   ES_REG_UF_VALID        (1<<8)
 331 #define   ES_REG_UF_BYTEO(o)     (((o)&0xff)<<0)
 332 #define   ES_REG_UF_BYTEM        (0xff<<0)
 333 #define   ES_REG_UF_BYTEI(i)     (((i)>>0)&0xff)
 334
 335
 336 /*
 337  *  Pages
 338  */
 339
 340 #define ES_PAGE_DAC     0x0c
 341 #define ES_PAGE_ADC     0x0d
 342 #define ES_PAGE_UART    0x0e
 343 #define ES_PAGE_UART1   0x0f
 344
 345 /*
 346  *  Sample rate converter addresses
 347  */
 348
 349 #define ES_SMPREG_DAC1          0x70
 350 #define ES_SMPREG_DAC2          0x74
 351 #define ES_SMPREG_ADC           0x78
 352 #define ES_SMPREG_VOL_ADC       0x6c
 353 #define ES_SMPREG_VOL_DAC1      0x7c
 354 #define ES_SMPREG_VOL_DAC2      0x7e
 355 #define ES_SMPREG_TRUNC_N       0x00
 356 #define ES_SMPREG_INT_REGS      0x01
 357 #define ES_SMPREG_ACCUM_FRAC    0x02
 358 #define ES_SMPREG_VFREQ_FRAC    0x03
 359
 360 /*
 361  *  Some contants
 362  */
 363
 364 #define ES_1370_SRCLOCK    1411200
 365 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
 366
 367 /*
 368  *  Open modes
 369  */
 370
 371 #define ES_MODE_PLAY1   0x0001
 372 #define ES_MODE_PLAY2   0x0002
 373 #define ES_MODE_CAPTURE 0x0004
 374
 375 #define ES_MODE_OUTPUT  0x0001  /* for MIDI */
 376 #define ES_MODE_INPUT   0x0002  /* for MIDI */
 377
 378 /*
 379
 380  */
 381
 382 struct ensoniq {
 383         spinlock_t reg_lock;
 384         struct mutex src_mutex;
 385
 386         int irq;
 387
 388         unsigned long playback1size;
 389         unsigned long playback2size;
 390         unsigned long capture3size;
 391
 392         unsigned long port;
 393         unsigned int mode;
 394         unsigned int uartm;     /* UART mode */
 395
 396         unsigned int ctrl;      /* control register */
 397         unsigned int sctrl;     /* serial control register */
 398         unsigned int cssr;      /* control status register */
 399         unsigned int uartc;     /* uart control register */
 400         unsigned int rev;       /* chip revision */
 401
 402         union {
 403 #ifdef CHIP1371
 404                 struct {
 405                         struct snd_ac97 *ac97;
 406                 } es1371;
 407 #else
 408                 struct {
 409                         int pclkdiv_lock;
 410                         struct snd_ak4531 *ak4531;
 411                 } es1370;
 412 #endif
 413         } u;
 414
 415         struct pci_dev *pci;
 416         unsigned short subsystem_vendor_id;
 417         unsigned short subsystem_device_id;
 418         struct snd_card *card;
 419         struct snd_pcm *pcm1;   /* DAC1/ADC PCM */
 420         struct snd_pcm *pcm2;   /* DAC2 PCM */
 421         struct snd_pcm_substream *playback1_substream;
 422         struct snd_pcm_substream *playback2_substream;
 423         struct snd_pcm_substream *capture_substream;
 424         unsigned int p1_dma_size;
 425         unsigned int p2_dma_size;
 426         unsigned int c_dma_size;
 427         unsigned int p1_period_size;
 428         unsigned int p2_period_size;
 429         unsigned int c_period_size;
 430         struct snd_rawmidi *rmidi;
 431         struct snd_rawmidi_substream *midi_input;
 432         struct snd_rawmidi_substream *midi_output;
 433
 434         unsigned int spdif;
 435         unsigned int spdif_default;
 436         unsigned int spdif_stream;
 437
 438 #ifdef CHIP1370
 439         struct snd_dma_buffer dma_bug;
 440 #endif
 441
 442 #ifdef SUPPORT_JOYSTICK
 443         struct gameport *gameport;
 444 #endif
 445 };
 446
 447 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 448
 449 static struct pci_device_id snd_audiopci_ids[] __devinitdata = {
 450 #ifdef CHIP1370
 451         { 0x1274, 0x5000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1370 */
 452 #endif
 453 #ifdef CHIP1371
 454         { 0x1274, 0x1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1371 */
 455         { 0x1274, 0x5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* ES1373 - CT5880 */
 456         { 0x1102, 0x8938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },   /* Ectiva EV1938 */
 457 #endif
 458         { 0, }
 459 };
 460
 461 MODULE_DEVICE_TABLE(pci, snd_audiopci_ids);
 462
 463 /*
 464  *  constants
 465  */
 466
 467 #define POLL_COUNT      0xa000
 468
 469 #ifdef CHIP1370
 470 static unsigned int snd_es1370_fixed_rates[] =
 471         {5512, 11025, 22050, 44100};
 472 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates = {
 473         .count = 4,
 474         .list = snd_es1370_fixed_rates,
 475         .mask = 0,
 476 };
 477 static struct snd_ratnum es1370_clock = {
 478         .num = ES_1370_SRCLOCK,
 479         .den_min = 29,
 480         .den_max = 353,
 481         .den_step = 1,
 482 };
 483 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock = {
 484         .nrats = 1,
 485         .rats = &es1370_clock,
 486 };
 487 #else
 488 static struct snd_ratden es1371_dac_clock = {
 489         .num_min = 3000 * (1 << 15),
 490         .num_max = 48000 * (1 << 15),
 491         .num_step = 3000,
 492         .den = 1 << 15,
 493 };
 494 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock = {
 495         .nrats = 1,
 496         .rats = &es1371_dac_clock,
 497 };
 498 static struct snd_ratnum es1371_adc_clock = {
 499         .num = 48000 << 15,
 500         .den_min = 32768,
 501         .den_max = 393216,
 502         .den_step = 1,
 503 };
 504 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock = {
 505         .nrats = 1,
 506         .rats = &es1371_adc_clock,
 507 };
 508 #endif
 509 static const unsigned int snd_ensoniq_sample_shift[] =
 510         {0, 1, 1, 2};
 511
 512 /*
 513  *  common I/O routines
 514  */
 515
 516 #ifdef CHIP1371
 517
 518 static unsigned int snd_es1371_wait_src_ready(struct ensoniq * ensoniq)
 519 {
 520         unsigned int t, r = 0;
 521
 522         for (t = 0; t < POLL_COUNT; t++) {
 523                 r = inl(ES_REG(ensoniq, 1371_SMPRATE));
 524                 if ((r & ES_1371_SRC_RAM_BUSY) == 0)
 525                         return r;
 526                 cond_resched();
 527         }
 528         snd_printk(KERN_ERR "wait source ready timeout 0x%lx [0x%x]\n",
 529                    ES_REG(ensoniq, 1371_SMPRATE), r);
 530         return 0;
 531 }
 532
 533 static unsigned int snd_es1371_src_read(struct ensoniq * ensoniq, unsigned short reg)
 534 {
 535         unsigned int temp, i, orig, r;
 536
 537         /* wait for ready */
 538         temp = orig = snd_es1371_wait_src_ready(ensoniq);
 539
 540         /* expose the SRC state bits */
 541         r = temp & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 542                     ES_1371_DIS_P2 | ES_1371_DIS_R1);
 543         r |= ES_1371_SRC_RAM_ADDRO(reg) | 0x10000;
 544         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 545
 546         /* now, wait for busy and the correct time to read */
 547         temp = snd_es1371_wait_src_ready(ensoniq);
 548
 549         if ((temp & 0x00870000) != 0x00010000) {
 550                 /* wait for the right state */
 551                 for (i = 0; i < POLL_COUNT; i++) {
 552                         temp = inl(ES_REG(ensoniq, 1371_SMPRATE));
 553                         if ((temp & 0x00870000) == 0x00010000)
 554                                 break;
 555                 }
 556         }
 557
 558         /* hide the state bits */
 559         r = orig & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 560                    ES_1371_DIS_P2 | ES_1371_DIS_R1);
 561         r |= ES_1371_SRC_RAM_ADDRO(reg);
 562         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 563
 564         return temp;
 565 }
 566
 567 static void snd_es1371_src_write(struct ensoniq * ensoniq,
 568                                  unsigned short reg, unsigned short data)
 569 {
 570         unsigned int r;
 571
 572         r = snd_es1371_wait_src_ready(ensoniq) &
 573             (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 574              ES_1371_DIS_P2 | ES_1371_DIS_R1);
 575         r |= ES_1371_SRC_RAM_ADDRO(reg) | ES_1371_SRC_RAM_DATAO(data);
 576         outl(r | ES_1371_SRC_RAM_WE, ES_REG(ensoniq, 1371_SMPRATE));
 577 }
 578
 579 #endif /* CHIP1371 */
 580
 581 #ifdef CHIP1370
 582
 583 static void snd_es1370_codec_write(struct snd_ak4531 *ak4531,
 584                                    unsigned short reg, unsigned short val)
 585 {
 586         struct ensoniq *ensoniq = ak4531->private_data;
 587         unsigned long end_time = jiffies + HZ / 10;
 588
 589 #if 0
 590         printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
 591                reg, val, ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 592 #endif
 593         do {
 594                 if (!(inl(ES_REG(ensoniq, STATUS)) & ES_1370_CSTAT)) {
 595                         outw(ES_1370_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1370_CODEC));
 596                         return;
 597                 }
 598                 schedule_timeout_uninterruptible(1);
 599         } while (time_after(end_time, jiffies));
 600         snd_printk(KERN_ERR "codec write timeout, status = 0x%x\n",
 601                    inl(ES_REG(ensoniq, STATUS)));
 602 }
 603
 604 #endif /* CHIP1370 */
 605
 606 #ifdef CHIP1371
 607
 608 static void snd_es1371_codec_write(struct snd_ac97 *ac97,
 609                                    unsigned short reg, unsigned short val)
 610 {
 611         struct ensoniq *ensoniq = ac97->private_data;
 612         unsigned int t, x;
 613
 614         mutex_lock(&ensoniq->src_mutex);
 615         for (t = 0; t < POLL_COUNT; t++) {
 616                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 617                         /* save the current state for latter */
 618                         x = snd_es1371_wait_src_ready(ensoniq);
 619                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 620                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 621                              ES_REG(ensoniq, 1371_SMPRATE));
 622                         /* wait for not busy (state 0) first to avoid
 623                            transition states */
 624                         for (t = 0; t < POLL_COUNT; t++) {
 625                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 626                                     0x00000000)
 627                                         break;
 628                         }
 629                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 630                         for (t = 0; t < POLL_COUNT; t++) {
 631                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 632                                     0x00010000)
 633                                         break;
 634                         }
 635                         outl(ES_1371_CODEC_WRITE(reg, val), ES_REG(ensoniq, 1371_CODEC));
 636                         /* restore SRC reg */
 637                         snd_es1371_wait_src_ready(ensoniq);
 638                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 639                         mutex_unlock(&ensoniq->src_mutex);
 640                         return;
 641                 }
 642         }
 643         mutex_unlock(&ensoniq->src_mutex);
 644         snd_printk(KERN_ERR "codec write timeout at 0x%lx [0x%x]\n",
 645                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 646 }
 647
 648 static unsigned short snd_es1371_codec_read(struct snd_ac97 *ac97,
 649                                             unsigned short reg)
 650 {
 651         struct ensoniq *ensoniq = ac97->private_data;
 652         unsigned int t, x, fail = 0;
 653
 654       __again:
 655         mutex_lock(&ensoniq->src_mutex);
 656         for (t = 0; t < POLL_COUNT; t++) {
 657                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP)) {
 658                         /* save the current state for latter */
 659                         x = snd_es1371_wait_src_ready(ensoniq);
 660                         outl((x & (ES_1371_SRC_DISABLE | ES_1371_DIS_P1 |
 661                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) | 0x00010000,
 662                              ES_REG(ensoniq, 1371_SMPRATE));
 663                         /* wait for not busy (state 0) first to avoid
 664                            transition states */
 665                         for (t = 0; t < POLL_COUNT; t++) {
 666                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 667                                     0x00000000)
 668                                         break;
 669                         }
 670                         /* wait for a SAFE time to write addr/data and then do it, dammit */
 671                         for (t = 0; t < POLL_COUNT; t++) {
 672                                 if ((inl(ES_REG(ensoniq, 1371_SMPRATE)) & 0x00870000) ==
 673                                     0x00010000)
 674                                         break;
 675                         }
 676                         outl(ES_1371_CODEC_READS(reg), ES_REG(ensoniq, 1371_CODEC));
 677                         /* restore SRC reg */
 678                         snd_es1371_wait_src_ready(ensoniq);
 679                         outl(x, ES_REG(ensoniq, 1371_SMPRATE));
 680                         /* wait for WIP again */
 681                         for (t = 0; t < POLL_COUNT; t++) {
 682                                 if (!(inl(ES_REG(ensoniq, 1371_CODEC)) & ES_1371_CODEC_WIP))
 683                                         break;
 684                         }
 685                         /* now wait for the stinkin' data (RDY) */
 686                         for (t = 0; t < POLL_COUNT; t++) {
 687                                 if ((x = inl(ES_REG(ensoniq, 1371_CODEC))) & ES_1371_CODEC_RDY) {
 688                                         mutex_unlock(&ensoniq->src_mutex);
 689                                         return ES_1371_CODEC_READ(x);
 690                                 }
 691                         }
 692                         mutex_unlock(&ensoniq->src_mutex);
 693                         if (++fail > 10) {
 694                                 snd_printk(KERN_ERR "codec read timeout (final) "
 695                                            "at 0x%lx, reg = 0x%x [0x%x]\n",
 696                                            ES_REG(ensoniq, 1371_CODEC), reg,
 697                                            inl(ES_REG(ensoniq, 1371_CODEC)));
 698                                 return 0;
 699                         }
 700                         goto __again;
 701                 }
 702         }
 703         mutex_unlock(&ensoniq->src_mutex);
 704         snd_printk(KERN_ERR "es1371: codec read timeout at 0x%lx [0x%x]\n",
 705                    ES_REG(ensoniq, 1371_CODEC), inl(ES_REG(ensoniq, 1371_CODEC)));
 706         return 0;
 707 }
 708
 709 static void snd_es1371_codec_wait(struct snd_ac97 *ac97)
 710 {
 711         msleep(750);
 712         snd_es1371_codec_read(ac97, AC97_RESET);
 713         snd_es1371_codec_read(ac97, AC97_VENDOR_ID1);
 714         snd_es1371_codec_read(ac97, AC97_VENDOR_ID2);
 715         msleep(50);
 716 }
 717
 718 static void snd_es1371_adc_rate(struct ensoniq * ensoniq, unsigned int rate)
 719 {
 720         unsigned int n, truncm, freq, result;
 721
 722         mutex_lock(&ensoniq->src_mutex);
 723         n = rate / 3000;
 724         if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
 725                 n--;
 726         truncm = (21 * n - 1) | 1;
 727         freq = ((48000UL << 15) / rate) * n;
 728         result = (48000UL << 15) / (freq / n);
 729         if (rate >= 24000) {
 730                 if (truncm > 239)
 731                         truncm = 239;
 732                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 733                                 (((239 - truncm) >> 1) << 9) | (n << 4));
 734         } else {
 735                 if (truncm > 119)
 736                         truncm = 119;
 737                 snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_TRUNC_N,
 738                                 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
 739         }
 740         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_INT_REGS,
 741                              (snd_es1371_src_read(ensoniq, ES_SMPREG_ADC +
 742                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 743                              ((freq >> 5) & 0xfc00));
 744         snd_es1371_src_write(ensoniq, ES_SMPREG_ADC + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 745         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, n << 8);
 746         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, n << 8);
 747         mutex_unlock(&ensoniq->src_mutex);
 748 }
 749
 750 static void snd_es1371_dac1_rate(struct ensoniq * ensoniq, unsigned int rate)
 751 {
 752         unsigned int freq, r;
 753
 754         mutex_lock(&ensoniq->src_mutex);
 755         freq = ((rate << 15) + 1500) / 3000;
 756         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 757                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1)) |
 758                 ES_1371_DIS_P1;
 759         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 760         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS,
 761                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC1 +
 762                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 763                              ((freq >> 5) & 0xfc00));
 764         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_VFREQ_FRAC, freq & 0x7fff);
 765         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 766                                                    ES_1371_DIS_P2 | ES_1371_DIS_R1));
 767         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 768         mutex_unlock(&ensoniq->src_mutex);
 769 }
 770
 771 static void snd_es1371_dac2_rate(struct ensoniq * ensoniq, unsigned int rate)
 772 {
 773         unsigned int freq, r;
 774
 775         mutex_lock(&ensoniq->src_mutex);
 776         freq = ((rate << 15) + 1500) / 3000;
 777         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 778                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1)) |
 779                 ES_1371_DIS_P2;
 780         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 781         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS,
 782                              (snd_es1371_src_read(ensoniq, ES_SMPREG_DAC2 +
 783                                                   ES_SMPREG_INT_REGS) & 0x00ff) |
 784                              ((freq >> 5) & 0xfc00));
 785         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_VFREQ_FRAC,
 786                              freq & 0x7fff);
 787         r = (snd_es1371_wait_src_ready(ensoniq) & (ES_1371_SRC_DISABLE |
 788                                                    ES_1371_DIS_P1 | ES_1371_DIS_R1));
 789         outl(r, ES_REG(ensoniq, 1371_SMPRATE));
 790         mutex_unlock(&ensoniq->src_mutex);
 791 }
 792
 793 #endif /* CHIP1371 */
 794
 795 static int snd_ensoniq_trigger(struct snd_pcm_substream *substream, int cmd)
 796 {
 797         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 798         switch (cmd) {
 799         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 800         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 801         {
 802                 unsigned int what = 0;
 803                 struct list_head *pos;
 804                 struct snd_pcm_substream *s;
 805                 snd_pcm_group_for_each(pos, substream) {
 806                         s = snd_pcm_group_substream_entry(pos);
 807                         if (s == ensoniq->playback1_substream) {
 808                                 what |= ES_P1_PAUSE;
 809                                 snd_pcm_trigger_done(s, substream);
 810                         } else if (s == ensoniq->playback2_substream) {
 811                                 what |= ES_P2_PAUSE;
 812                                 snd_pcm_trigger_done(s, substream);
 813                         } else if (s == ensoniq->capture_substream)
 814                                 return -EINVAL;
 815                 }
 816                 spin_lock(&ensoniq->reg_lock);
 817                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 818                         ensoniq->sctrl |= what;
 819                 else
 820                         ensoniq->sctrl &= ~what;
 821                 outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 822                 spin_unlock(&ensoniq->reg_lock);
 823                 break;
 824         }
 825         case SNDRV_PCM_TRIGGER_START:
 826         case SNDRV_PCM_TRIGGER_STOP:
 827         {
 828                 unsigned int what = 0;
 829                 struct list_head *pos;
 830                 struct snd_pcm_substream *s;
 831                 snd_pcm_group_for_each(pos, substream) {
 832                         s = snd_pcm_group_substream_entry(pos);
 833                         if (s == ensoniq->playback1_substream) {
 834                                 what |= ES_DAC1_EN;
 835                                 snd_pcm_trigger_done(s, substream);
 836                         } else if (s == ensoniq->playback2_substream) {
 837                                 what |= ES_DAC2_EN;
 838                                 snd_pcm_trigger_done(s, substream);
 839                         } else if (s == ensoniq->capture_substream) {
 840                                 what |= ES_ADC_EN;
 841                                 snd_pcm_trigger_done(s, substream);
 842                         }
 843                 }
 844                 spin_lock(&ensoniq->reg_lock);
 845                 if (cmd == SNDRV_PCM_TRIGGER_START)
 846                         ensoniq->ctrl |= what;
 847                 else
 848                         ensoniq->ctrl &= ~what;
 849                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 850                 spin_unlock(&ensoniq->reg_lock);
 851                 break;
 852         }
 853         default:
 854                 return -EINVAL;
 855         }
 856         return 0;
 857 }
 858
 859 /*
 860  *  PCM part
 861  */
 862
 863 static int snd_ensoniq_hw_params(struct snd_pcm_substream *substream,
 864                                  struct snd_pcm_hw_params *hw_params)
 865 {
 866         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 867 }
 868
 869 static int snd_ensoniq_hw_free(struct snd_pcm_substream *substream)
 870 {
 871         return snd_pcm_lib_free_pages(substream);
 872 }
 873
 874 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream *substream)
 875 {
 876         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 877         struct snd_pcm_runtime *runtime = substream->runtime;
 878         unsigned int mode = 0;
 879
 880         ensoniq->p1_dma_size = snd_pcm_lib_buffer_bytes(substream);
 881         ensoniq->p1_period_size = snd_pcm_lib_period_bytes(substream);
 882         if (snd_pcm_format_width(runtime->format) == 16)
 883                 mode |= 0x02;
 884         if (runtime->channels > 1)
 885                 mode |= 0x01;
 886         spin_lock_irq(&ensoniq->reg_lock);
 887         ensoniq->ctrl &= ~ES_DAC1_EN;
 888 #ifdef CHIP1371
 889         /* 48k doesn't need SRC (it breaks AC3-passthru) */
 890         if (runtime->rate == 48000)
 891                 ensoniq->ctrl |= ES_1373_BYPASS_P1;
 892         else
 893                 ensoniq->ctrl &= ~ES_1373_BYPASS_P1;
 894 #endif
 895         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 896         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 897         outl(runtime->dma_addr, ES_REG(ensoniq, DAC1_FRAME));
 898         outl((ensoniq->p1_dma_size >> 2) - 1, ES_REG(ensoniq, DAC1_SIZE));
 899         ensoniq->sctrl &= ~(ES_P1_LOOP_SEL | ES_P1_PAUSE | ES_P1_SCT_RLD | ES_P1_MODEM);
 900         ensoniq->sctrl |= ES_P1_INT_EN | ES_P1_MODEO(mode);
 901         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 902         outl((ensoniq->p1_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 903              ES_REG(ensoniq, DAC1_COUNT));
 904 #ifdef CHIP1370
 905         ensoniq->ctrl &= ~ES_1370_WTSRSELM;
 906         switch (runtime->rate) {
 907         case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break;
 908         case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break;
 909         case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break;
 910         case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break;
 911         default: snd_BUG();
 912         }
 913 #endif
 914         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 915         spin_unlock_irq(&ensoniq->reg_lock);
 916 #ifndef CHIP1370
 917         snd_es1371_dac1_rate(ensoniq, runtime->rate);
 918 #endif
 919         return 0;
 920 }
 921
 922 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream *substream)
 923 {
 924         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 925         struct snd_pcm_runtime *runtime = substream->runtime;
 926         unsigned int mode = 0;
 927
 928         ensoniq->p2_dma_size = snd_pcm_lib_buffer_bytes(substream);
 929         ensoniq->p2_period_size = snd_pcm_lib_period_bytes(substream);
 930         if (snd_pcm_format_width(runtime->format) == 16)
 931                 mode |= 0x02;
 932         if (runtime->channels > 1)
 933                 mode |= 0x01;
 934         spin_lock_irq(&ensoniq->reg_lock);
 935         ensoniq->ctrl &= ~ES_DAC2_EN;
 936         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 937         outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
 938         outl(runtime->dma_addr, ES_REG(ensoniq, DAC2_FRAME));
 939         outl((ensoniq->p2_dma_size >> 2) - 1, ES_REG(ensoniq, DAC2_SIZE));
 940         ensoniq->sctrl &= ~(ES_P2_LOOP_SEL | ES_P2_PAUSE | ES_P2_DAC_SEN |
 941                             ES_P2_END_INCM | ES_P2_ST_INCM | ES_P2_MODEM);
 942         ensoniq->sctrl |= ES_P2_INT_EN | ES_P2_MODEO(mode) |
 943                           ES_P2_END_INCO(mode & 2 ? 2 : 1) | ES_P2_ST_INCO(0);
 944         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 945         outl((ensoniq->p2_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 946              ES_REG(ensoniq, DAC2_COUNT));
 947 #ifdef CHIP1370
 948         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_CAPTURE)) {
 949                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 950                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 951                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_PLAY2;
 952         }
 953 #endif
 954         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 955         spin_unlock_irq(&ensoniq->reg_lock);
 956 #ifndef CHIP1370
 957         snd_es1371_dac2_rate(ensoniq, runtime->rate);
 958 #endif
 959         return 0;
 960 }
 961
 962 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream *substream)
 963 {
 964         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
 965         struct snd_pcm_runtime *runtime = substream->runtime;
 966         unsigned int mode = 0;
 967
 968         ensoniq->c_dma_size = snd_pcm_lib_buffer_bytes(substream);
 969         ensoniq->c_period_size = snd_pcm_lib_period_bytes(substream);
 970         if (snd_pcm_format_width(runtime->format) == 16)
 971                 mode |= 0x02;
 972         if (runtime->channels > 1)
 973                 mode |= 0x01;
 974         spin_lock_irq(&ensoniq->reg_lock);
 975         ensoniq->ctrl &= ~ES_ADC_EN;
 976         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 977         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
 978         outl(runtime->dma_addr, ES_REG(ensoniq, ADC_FRAME));
 979         outl((ensoniq->c_dma_size >> 2) - 1, ES_REG(ensoniq, ADC_SIZE));
 980         ensoniq->sctrl &= ~(ES_R1_LOOP_SEL | ES_R1_MODEM);
 981         ensoniq->sctrl |= ES_R1_INT_EN | ES_R1_MODEO(mode);
 982         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
 983         outl((ensoniq->c_period_size >> snd_ensoniq_sample_shift[mode]) - 1,
 984              ES_REG(ensoniq, ADC_COUNT));
 985 #ifdef CHIP1370
 986         if (!(ensoniq->u.es1370.pclkdiv_lock & ES_MODE_PLAY2)) {
 987                 ensoniq->ctrl &= ~ES_1370_PCLKDIVM;
 988                 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate));
 989                 ensoniq->u.es1370.pclkdiv_lock |= ES_MODE_CAPTURE;
 990         }
 991 #endif
 992         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
 993         spin_unlock_irq(&ensoniq->reg_lock);
 994 #ifndef CHIP1370
 995         snd_es1371_adc_rate(ensoniq, runtime->rate);
 996 #endif
 997         return 0;
 998 }
 999
1000 static snd_pcm_uframes_t snd_ensoniq_playback1_pointer(struct snd_pcm_substream *substream)
1001 {
1002         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1003         size_t ptr;
1004
1005         spin_lock(&ensoniq->reg_lock);
1006         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC1_EN) {
1007                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1008                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC1_SIZE)));
1009                 ptr = bytes_to_frames(substream->runtime, ptr);
1010         } else {
1011                 ptr = 0;
1012         }
1013         spin_unlock(&ensoniq->reg_lock);
1014         return ptr;
1015 }
1016
1017 static snd_pcm_uframes_t snd_ensoniq_playback2_pointer(struct snd_pcm_substream *substream)
1018 {
1019         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1020         size_t ptr;
1021
1022         spin_lock(&ensoniq->reg_lock);
1023         if (inl(ES_REG(ensoniq, CONTROL)) & ES_DAC2_EN) {
1024                 outl(ES_MEM_PAGEO(ES_PAGE_DAC), ES_REG(ensoniq, MEM_PAGE));
1025                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, DAC2_SIZE)));
1026                 ptr = bytes_to_frames(substream->runtime, ptr);
1027         } else {
1028                 ptr = 0;
1029         }
1030         spin_unlock(&ensoniq->reg_lock);
1031         return ptr;
1032 }
1033
1034 static snd_pcm_uframes_t snd_ensoniq_capture_pointer(struct snd_pcm_substream *substream)
1035 {
1036         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1037         size_t ptr;
1038
1039         spin_lock(&ensoniq->reg_lock);
1040         if (inl(ES_REG(ensoniq, CONTROL)) & ES_ADC_EN) {
1041                 outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1042                 ptr = ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq, ADC_SIZE)));
1043                 ptr = bytes_to_frames(substream->runtime, ptr);
1044         } else {
1045                 ptr = 0;
1046         }
1047         spin_unlock(&ensoniq->reg_lock);
1048         return ptr;
1049 }
1050
1051 static struct snd_pcm_hardware snd_ensoniq_playback1 =
1052 {
1053         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1054                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1055                                  SNDRV_PCM_INFO_MMAP_VALID |
1056                                  SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
1057         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1058         .rates =
1059 #ifndef CHIP1370
1060                                 SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1061 #else
1062                                 (SNDRV_PCM_RATE_KNOT |  /* 5512Hz rate */
1063                                  SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 |
1064                                  SNDRV_PCM_RATE_44100),
1065 #endif
1066         .rate_min =             4000,
1067         .rate_max =             48000,
1068         .channels_min =         1,
1069         .channels_max =         2,
1070         .buffer_bytes_max =     (128*1024),
1071         .period_bytes_min =     64,
1072         .period_bytes_max =     (128*1024),
1073         .periods_min =          1,
1074         .periods_max =          1024,
1075         .fifo_size =            0,
1076 };
1077
1078 static struct snd_pcm_hardware snd_ensoniq_playback2 =
1079 {
1080         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1081                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1082                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_PAUSE |
1083                                  SNDRV_PCM_INFO_SYNC_START),
1084         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1085         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1086         .rate_min =             4000,
1087         .rate_max =             48000,
1088         .channels_min =         1,
1089         .channels_max =         2,
1090         .buffer_bytes_max =     (128*1024),
1091         .period_bytes_min =     64,
1092         .period_bytes_max =     (128*1024),
1093         .periods_min =          1,
1094         .periods_max =          1024,
1095         .fifo_size =            0,
1096 };
1097
1098 static struct snd_pcm_hardware snd_ensoniq_capture =
1099 {
1100         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1101                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1102                                  SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START),
1103         .formats =              SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1104         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1105         .rate_min =             4000,
1106         .rate_max =             48000,
1107         .channels_min =         1,
1108         .channels_max =         2,
1109         .buffer_bytes_max =     (128*1024),
1110         .period_bytes_min =     64,
1111         .period_bytes_max =     (128*1024),
1112         .periods_min =          1,
1113         .periods_max =          1024,
1114         .fifo_size =            0,
1115 };
1116
1117 static int snd_ensoniq_playback1_open(struct snd_pcm_substream *substream)
1118 {
1119         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1120         struct snd_pcm_runtime *runtime = substream->runtime;
1121
1122         ensoniq->mode |= ES_MODE_PLAY1;
1123         ensoniq->playback1_substream = substream;
1124         runtime->hw = snd_ensoniq_playback1;
1125         snd_pcm_set_sync(substream);
1126         spin_lock_irq(&ensoniq->reg_lock);
1127         if (ensoniq->spdif && ensoniq->playback2_substream == NULL)
1128                 ensoniq->spdif_stream = ensoniq->spdif_default;
1129         spin_unlock_irq(&ensoniq->reg_lock);
1130 #ifdef CHIP1370
1131         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1132                                    &snd_es1370_hw_constraints_rates);
1133 #else
1134         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1135                                       &snd_es1371_hw_constraints_dac_clock);
1136 #endif
1137         return 0;
1138 }
1139
1140 static int snd_ensoniq_playback2_open(struct snd_pcm_substream *substream)
1141 {
1142         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1143         struct snd_pcm_runtime *runtime = substream->runtime;
1144
1145         ensoniq->mode |= ES_MODE_PLAY2;
1146         ensoniq->playback2_substream = substream;
1147         runtime->hw = snd_ensoniq_playback2;
1148         snd_pcm_set_sync(substream);
1149         spin_lock_irq(&ensoniq->reg_lock);
1150         if (ensoniq->spdif && ensoniq->playback1_substream == NULL)
1151                 ensoniq->spdif_stream = ensoniq->spdif_default;
1152         spin_unlock_irq(&ensoniq->reg_lock);
1153 #ifdef CHIP1370
1154         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1155                                       &snd_es1370_hw_constraints_clock);
1156 #else
1157         snd_pcm_hw_constraint_ratdens(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1158                                       &snd_es1371_hw_constraints_dac_clock);
1159 #endif
1160         return 0;
1161 }
1162
1163 static int snd_ensoniq_capture_open(struct snd_pcm_substream *substream)
1164 {
1165         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1166         struct snd_pcm_runtime *runtime = substream->runtime;
1167
1168         ensoniq->mode |= ES_MODE_CAPTURE;
1169         ensoniq->capture_substream = substream;
1170         runtime->hw = snd_ensoniq_capture;
1171         snd_pcm_set_sync(substream);
1172 #ifdef CHIP1370
1173         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1174                                       &snd_es1370_hw_constraints_clock);
1175 #else
1176         snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
1177                                       &snd_es1371_hw_constraints_adc_clock);
1178 #endif
1179         return 0;
1180 }
1181
1182 static int snd_ensoniq_playback1_close(struct snd_pcm_substream *substream)
1183 {
1184         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1185
1186         ensoniq->playback1_substream = NULL;
1187         ensoniq->mode &= ~ES_MODE_PLAY1;
1188         return 0;
1189 }
1190
1191 static int snd_ensoniq_playback2_close(struct snd_pcm_substream *substream)
1192 {
1193         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1194
1195         ensoniq->playback2_substream = NULL;
1196         spin_lock_irq(&ensoniq->reg_lock);
1197 #ifdef CHIP1370
1198         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_PLAY2;
1199 #endif
1200         ensoniq->mode &= ~ES_MODE_PLAY2;
1201         spin_unlock_irq(&ensoniq->reg_lock);
1202         return 0;
1203 }
1204
1205 static int snd_ensoniq_capture_close(struct snd_pcm_substream *substream)
1206 {
1207         struct ensoniq *ensoniq = snd_pcm_substream_chip(substream);
1208
1209         ensoniq->capture_substream = NULL;
1210         spin_lock_irq(&ensoniq->reg_lock);
1211 #ifdef CHIP1370
1212         ensoniq->u.es1370.pclkdiv_lock &= ~ES_MODE_CAPTURE;
1213 #endif
1214         ensoniq->mode &= ~ES_MODE_CAPTURE;
1215         spin_unlock_irq(&ensoniq->reg_lock);
1216         return 0;
1217 }
1218
1219 static struct snd_pcm_ops snd_ensoniq_playback1_ops = {
1220         .open =         snd_ensoniq_playback1_open,
1221         .close =        snd_ensoniq_playback1_close,
1222         .ioctl =        snd_pcm_lib_ioctl,
1223         .hw_params =    snd_ensoniq_hw_params,
1224         .hw_free =      snd_ensoniq_hw_free,
1225         .prepare =      snd_ensoniq_playback1_prepare,
1226         .trigger =      snd_ensoniq_trigger,
1227         .pointer =      snd_ensoniq_playback1_pointer,
1228 };
1229
1230 static struct snd_pcm_ops snd_ensoniq_playback2_ops = {
1231         .open =         snd_ensoniq_playback2_open,
1232         .close =        snd_ensoniq_playback2_close,
1233         .ioctl =        snd_pcm_lib_ioctl,
1234         .hw_params =    snd_ensoniq_hw_params,
1235         .hw_free =      snd_ensoniq_hw_free,
1236         .prepare =      snd_ensoniq_playback2_prepare,
1237         .trigger =      snd_ensoniq_trigger,
1238         .pointer =      snd_ensoniq_playback2_pointer,
1239 };
1240
1241 static struct snd_pcm_ops snd_ensoniq_capture_ops = {
1242         .open =         snd_ensoniq_capture_open,
1243         .close =        snd_ensoniq_capture_close,
1244         .ioctl =        snd_pcm_lib_ioctl,
1245         .hw_params =    snd_ensoniq_hw_params,
1246         .hw_free =      snd_ensoniq_hw_free,
1247         .prepare =      snd_ensoniq_capture_prepare,
1248         .trigger =      snd_ensoniq_trigger,
1249         .pointer =      snd_ensoniq_capture_pointer,
1250 };
1251
1252 static int __devinit snd_ensoniq_pcm(struct ensoniq * ensoniq, int device,
1253                                      struct snd_pcm ** rpcm)
1254 {
1255         struct snd_pcm *pcm;
1256         int err;
1257
1258         if (rpcm)
1259                 *rpcm = NULL;
1260 #ifdef CHIP1370
1261         err = snd_pcm_new(ensoniq->card, "ES1370/1", device, 1, 1, &pcm);
1262 #else
1263         err = snd_pcm_new(ensoniq->card, "ES1371/1", device, 1, 1, &pcm);
1264 #endif
1265         if (err < 0)
1266                 return err;
1267
1268 #ifdef CHIP1370
1269         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1270 #else
1271         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1272 #endif
1273         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ensoniq_capture_ops);
1274
1275         pcm->private_data = ensoniq;
1276         pcm->info_flags = 0;
1277 #ifdef CHIP1370
1278         strcpy(pcm->name, "ES1370 DAC2/ADC");
1279 #else
1280         strcpy(pcm->name, "ES1371 DAC2/ADC");
1281 #endif
1282         ensoniq->pcm1 = pcm;
1283
1284         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1285                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1286
1287         if (rpcm)
1288                 *rpcm = pcm;
1289         return 0;
1290 }
1291
1292 static int __devinit snd_ensoniq_pcm2(struct ensoniq * ensoniq, int device,
1293                                       struct snd_pcm ** rpcm)
1294 {
1295         struct snd_pcm *pcm;
1296         int err;
1297
1298         if (rpcm)
1299                 *rpcm = NULL;
1300 #ifdef CHIP1370
1301         err = snd_pcm_new(ensoniq->card, "ES1370/2", device, 1, 0, &pcm);
1302 #else
1303         err = snd_pcm_new(ensoniq->card, "ES1371/2", device, 1, 0, &pcm);
1304 #endif
1305         if (err < 0)
1306                 return err;
1307
1308 #ifdef CHIP1370
1309         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback1_ops);
1310 #else
1311         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ensoniq_playback2_ops);
1312 #endif
1313         pcm->private_data = ensoniq;
1314         pcm->info_flags = 0;
1315 #ifdef CHIP1370
1316         strcpy(pcm->name, "ES1370 DAC1");
1317 #else
1318         strcpy(pcm->name, "ES1371 DAC1");
1319 #endif
1320         ensoniq->pcm2 = pcm;
1321
1322         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1323                                               snd_dma_pci_data(ensoniq->pci), 64*1024, 128*1024);
1324
1325         if (rpcm)
1326                 *rpcm = pcm;
1327         return 0;
1328 }
1329
1330 /*
1331  *  Mixer section
1332  */
1333
1334 /*
1335  * ENS1371 mixer (including SPDIF interface)
1336  */
1337 #ifdef CHIP1371
1338 static int snd_ens1373_spdif_info(struct snd_kcontrol *kcontrol,
1339                                   struct snd_ctl_elem_info *uinfo)
1340 {
1341         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1342         uinfo->count = 1;
1343         return 0;
1344 }
1345
1346 static int snd_ens1373_spdif_default_get(struct snd_kcontrol *kcontrol,
1347                                          struct snd_ctl_elem_value *ucontrol)
1348 {
1349         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1350         spin_lock_irq(&ensoniq->reg_lock);
1351         ucontrol->value.iec958.status[0] = (ensoniq->spdif_default >> 0) & 0xff;
1352         ucontrol->value.iec958.status[1] = (ensoniq->spdif_default >> 8) & 0xff;
1353         ucontrol->value.iec958.status[2] = (ensoniq->spdif_default >> 16) & 0xff;
1354         ucontrol->value.iec958.status[3] = (ensoniq->spdif_default >> 24) & 0xff;
1355         spin_unlock_irq(&ensoniq->reg_lock);
1356         return 0;
1357 }
1358
1359 static int snd_ens1373_spdif_default_put(struct snd_kcontrol *kcontrol,
1360                                          struct snd_ctl_elem_value *ucontrol)
1361 {
1362         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1363         unsigned int val;
1364         int change;
1365
1366         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1367               ((u32)ucontrol->value.iec958.status[1] << 8) |
1368               ((u32)ucontrol->value.iec958.status[2] << 16) |
1369               ((u32)ucontrol->value.iec958.status[3] << 24);
1370         spin_lock_irq(&ensoniq->reg_lock);
1371         change = ensoniq->spdif_default != val;
1372         ensoniq->spdif_default = val;
1373         if (change && ensoniq->playback1_substream == NULL &&
1374             ensoniq->playback2_substream == NULL)
1375                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1376         spin_unlock_irq(&ensoniq->reg_lock);
1377         return change;
1378 }
1379
1380 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol *kcontrol,
1381                                       struct snd_ctl_elem_value *ucontrol)
1382 {
1383         ucontrol->value.iec958.status[0] = 0xff;
1384         ucontrol->value.iec958.status[1] = 0xff;
1385         ucontrol->value.iec958.status[2] = 0xff;
1386         ucontrol->value.iec958.status[3] = 0xff;
1387         return 0;
1388 }
1389
1390 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol *kcontrol,
1391                                         struct snd_ctl_elem_value *ucontrol)
1392 {
1393         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1394         spin_lock_irq(&ensoniq->reg_lock);
1395         ucontrol->value.iec958.status[0] = (ensoniq->spdif_stream >> 0) & 0xff;
1396         ucontrol->value.iec958.status[1] = (ensoniq->spdif_stream >> 8) & 0xff;
1397         ucontrol->value.iec958.status[2] = (ensoniq->spdif_stream >> 16) & 0xff;
1398         ucontrol->value.iec958.status[3] = (ensoniq->spdif_stream >> 24) & 0xff;
1399         spin_unlock_irq(&ensoniq->reg_lock);
1400         return 0;
1401 }
1402
1403 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol *kcontrol,
1404                                         struct snd_ctl_elem_value *ucontrol)
1405 {
1406         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1407         unsigned int val;
1408         int change;
1409
1410         val = ((u32)ucontrol->value.iec958.status[0] << 0) |
1411               ((u32)ucontrol->value.iec958.status[1] << 8) |
1412               ((u32)ucontrol->value.iec958.status[2] << 16) |
1413               ((u32)ucontrol->value.iec958.status[3] << 24);
1414         spin_lock_irq(&ensoniq->reg_lock);
1415         change = ensoniq->spdif_stream != val;
1416         ensoniq->spdif_stream = val;
1417         if (change && (ensoniq->playback1_substream != NULL ||
1418                        ensoniq->playback2_substream != NULL))
1419                 outl(val, ES_REG(ensoniq, CHANNEL_STATUS));
1420         spin_unlock_irq(&ensoniq->reg_lock);
1421         return change;
1422 }
1423
1424 #define ES1371_SPDIF(xname) \
1425 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1426   .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1427
1428 static int snd_es1371_spdif_info(struct snd_kcontrol *kcontrol,
1429                                  struct snd_ctl_elem_info *uinfo)
1430 {
1431         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1432         uinfo->count = 1;
1433         uinfo->value.integer.min = 0;
1434         uinfo->value.integer.max = 1;
1435         return 0;
1436 }
1437
1438 static int snd_es1371_spdif_get(struct snd_kcontrol *kcontrol,
1439                                 struct snd_ctl_elem_value *ucontrol)
1440 {
1441         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1442
1443         spin_lock_irq(&ensoniq->reg_lock);
1444         ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0;
1445         spin_unlock_irq(&ensoniq->reg_lock);
1446         return 0;
1447 }
1448
1449 static int snd_es1371_spdif_put(struct snd_kcontrol *kcontrol,
1450                                 struct snd_ctl_elem_value *ucontrol)
1451 {
1452         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1453         unsigned int nval1, nval2;
1454         int change;
1455
1456         nval1 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_THRU : 0;
1457         nval2 = ucontrol->value.integer.value[0] ? ES_1373_SPDIF_EN : 0;
1458         spin_lock_irq(&ensoniq->reg_lock);
1459         change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1;
1460         ensoniq->ctrl &= ~ES_1373_SPDIF_THRU;
1461         ensoniq->ctrl |= nval1;
1462         ensoniq->cssr &= ~ES_1373_SPDIF_EN;
1463         ensoniq->cssr |= nval2;
1464         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1465         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1466         spin_unlock_irq(&ensoniq->reg_lock);
1467         return change;
1468 }
1469
1470
1471 /* spdif controls */
1472 static struct snd_kcontrol_new snd_es1371_mixer_spdif[] __devinitdata = {
1473         ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH)),
1474         {
1475                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1476                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
1477                 .info =         snd_ens1373_spdif_info,
1478                 .get =          snd_ens1373_spdif_default_get,
1479                 .put =          snd_ens1373_spdif_default_put,
1480         },
1481         {
1482                 .access =       SNDRV_CTL_ELEM_ACCESS_READ,
1483                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1484                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
1485                 .info =         snd_ens1373_spdif_info,
1486                 .get =          snd_ens1373_spdif_mask_get
1487         },
1488         {
1489                 .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
1490                 .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
1491                 .info =         snd_ens1373_spdif_info,
1492                 .get =          snd_ens1373_spdif_stream_get,
1493                 .put =          snd_ens1373_spdif_stream_put
1494         },
1495 };
1496
1497
1498 static int snd_es1373_rear_info(struct snd_kcontrol *kcontrol,
1499                                 struct snd_ctl_elem_info *uinfo)
1500 {
1501         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1502         uinfo->count = 1;
1503         uinfo->value.integer.min = 0;
1504         uinfo->value.integer.max = 1;
1505         return 0;
1506 }
1507
1508 static int snd_es1373_rear_get(struct snd_kcontrol *kcontrol,
1509                                struct snd_ctl_elem_value *ucontrol)
1510 {
1511         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1512         int val = 0;
1513
1514         spin_lock_irq(&ensoniq->reg_lock);
1515         if ((ensoniq->cssr & (ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|
1516                               ES_1373_REAR_BIT24)) == ES_1373_REAR_BIT26)
1517                 val = 1;
1518         ucontrol->value.integer.value[0] = val;
1519         spin_unlock_irq(&ensoniq->reg_lock);
1520         return 0;
1521 }
1522
1523 static int snd_es1373_rear_put(struct snd_kcontrol *kcontrol,
1524                                struct snd_ctl_elem_value *ucontrol)
1525 {
1526         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1527         unsigned int nval1;
1528         int change;
1529
1530         nval1 = ucontrol->value.integer.value[0] ?
1531                 ES_1373_REAR_BIT26 : (ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1532         spin_lock_irq(&ensoniq->reg_lock);
1533         change = (ensoniq->cssr & (ES_1373_REAR_BIT27|
1534                                    ES_1373_REAR_BIT26|ES_1373_REAR_BIT24)) != nval1;
1535         ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT26|ES_1373_REAR_BIT24);
1536         ensoniq->cssr |= nval1;
1537         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
1538         spin_unlock_irq(&ensoniq->reg_lock);
1539         return change;
1540 }
1541
1542 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata =
1543 {
1544         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1545         .name =         "AC97 2ch->4ch Copy Switch",
1546         .info =         snd_es1373_rear_info,
1547         .get =          snd_es1373_rear_get,
1548         .put =          snd_es1373_rear_put,
1549 };
1550
1551 static int snd_es1373_line_info(struct snd_kcontrol *kcontrol,
1552                                 struct snd_ctl_elem_info *uinfo)
1553 {
1554         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1555         uinfo->count = 1;
1556         uinfo->value.integer.min = 0;
1557         uinfo->value.integer.max = 1;
1558         return 0;
1559 }
1560
1561 static int snd_es1373_line_get(struct snd_kcontrol *kcontrol,
1562                                struct snd_ctl_elem_value *ucontrol)
1563 {
1564         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1565         int val = 0;
1566
1567         spin_lock_irq(&ensoniq->reg_lock);
1568         if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4)
1569                 val = 1;
1570         ucontrol->value.integer.value[0] = val;
1571         spin_unlock_irq(&ensoniq->reg_lock);
1572         return 0;
1573 }
1574
1575 static int snd_es1373_line_put(struct snd_kcontrol *kcontrol,
1576                                struct snd_ctl_elem_value *ucontrol)
1577 {
1578         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1579         int changed;
1580         unsigned int ctrl;
1581
1582         spin_lock_irq(&ensoniq->reg_lock);
1583         ctrl = ensoniq->ctrl;
1584         if (ucontrol->value.integer.value[0])
1585                 ensoniq->ctrl |= ES_1371_GPIO_OUT(4);   /* switch line-in -> rear out */
1586         else
1587                 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4);
1588         changed = (ctrl != ensoniq->ctrl);
1589         if (changed)
1590                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1591         spin_unlock_irq(&ensoniq->reg_lock);
1592         return changed;
1593 }
1594
1595 static struct snd_kcontrol_new snd_ens1373_line __devinitdata =
1596 {
1597         .iface =        SNDRV_CTL_ELEM_IFACE_MIXER,
1598         .name =         "Line In->Rear Out Switch",
1599         .info =         snd_es1373_line_info,
1600         .get =          snd_es1373_line_get,
1601         .put =          snd_es1373_line_put,
1602 };
1603
1604 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97 *ac97)
1605 {
1606         struct ensoniq *ensoniq = ac97->private_data;
1607         ensoniq->u.es1371.ac97 = NULL;
1608 }
1609
1610 static struct {
1611         unsigned short vid;             /* vendor ID */
1612         unsigned short did;             /* device ID */
1613         unsigned char rev;              /* revision */
1614 } es1371_spdif_present[] __devinitdata = {
1615         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1616         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1617         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1618         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1619         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1620         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1621 };
1622
1623 static int snd_ensoniq_1371_mixer(struct ensoniq * ensoniq, int has_spdif, int has_line)
1624 {
1625         struct snd_card *card = ensoniq->card;
1626         struct snd_ac97_bus *pbus;
1627         struct snd_ac97_template ac97;
1628         int err, idx;
1629         static struct snd_ac97_bus_ops ops = {
1630                 .write = snd_es1371_codec_write,
1631                 .read = snd_es1371_codec_read,
1632                 .wait = snd_es1371_codec_wait,
1633         };
1634
1635         if ((err = snd_ac97_bus(card, 0, &ops, NULL, &pbus)) < 0)
1636                 return err;
1637
1638         memset(&ac97, 0, sizeof(ac97));
1639         ac97.private_data = ensoniq;
1640         ac97.private_free = snd_ensoniq_mixer_free_ac97;
1641         ac97.scaps = AC97_SCAP_AUDIO;
1642         if ((err = snd_ac97_mixer(pbus, &ac97, &ensoniq->u.es1371.ac97)) < 0)
1643                 return err;
1644         for (idx = 0; es1371_spdif_present[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
1645                 if ((ensoniq->pci->vendor == es1371_spdif_present[idx].vid &&
1646                      ensoniq->pci->device == es1371_spdif_present[idx].did &&
1647                      ensoniq->rev == es1371_spdif_present[idx].rev) || has_spdif > 0) {
1648                         struct snd_kcontrol *kctl;
1649                         int i, index = 0;
1650
1651                         if (has_spdif < 0)
1652                                 break;
1653
1654                         ensoniq->spdif_default = ensoniq->spdif_stream =
1655                                 SNDRV_PCM_DEFAULT_CON_SPDIF;
1656                         outl(ensoniq->spdif_default, ES_REG(ensoniq, CHANNEL_STATUS));
1657
1658                         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SPDIF)
1659                                 index++;
1660
1661                         for (i = 0; i < (int)ARRAY_SIZE(snd_es1371_mixer_spdif); i++) {
1662                                 kctl = snd_ctl_new1(&snd_es1371_mixer_spdif[i], ensoniq);
1663                                 if (! kctl)
1664                                         return -ENOMEM;
1665                                 kctl->id.index = index;
1666                                 if ((err = snd_ctl_add(card, kctl)) < 0)
1667                                         return err;
1668                         }
1669                         break;
1670                 }
1671         if (ensoniq->u.es1371.ac97->ext_id & AC97_EI_SDAC) {
1672                 /* mirror rear to front speakers */
1673                 ensoniq->cssr &= ~(ES_1373_REAR_BIT27|ES_1373_REAR_BIT24);
1674                 ensoniq->cssr |= ES_1373_REAR_BIT26;
1675                 err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_rear, ensoniq));
1676                 if (err < 0)
1677                         return err;
1678         }
1679         if (((ensoniq->subsystem_vendor_id == 0x1274) &&
1680             (ensoniq->subsystem_device_id == 0x2000)) || /* GA-7DXR */
1681             ((ensoniq->subsystem_vendor_id == 0x1458) &&
1682             (ensoniq->subsystem_device_id == 0xa000)) || /* GA-8IEXP */
1683             has_line > 0) {
1684                  err = snd_ctl_add(card, snd_ctl_new1(&snd_ens1373_line, ensoniq));
1685                  if (err < 0)
1686                          return err;
1687         }
1688
1689         return 0;
1690 }
1691
1692 #endif /* CHIP1371 */
1693
1694 /* generic control callbacks for ens1370 */
1695 #ifdef CHIP1370
1696 #define ENSONIQ_CONTROL(xname, mask) \
1697 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1698   .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1699   .private_value = mask }
1700
1701 static int snd_ensoniq_control_info(struct snd_kcontrol *kcontrol,
1702                                     struct snd_ctl_elem_info *uinfo)
1703 {
1704         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1705         uinfo->count = 1;
1706         uinfo->value.integer.min = 0;
1707         uinfo->value.integer.max = 1;
1708         return 0;
1709 }
1710
1711 static int snd_ensoniq_control_get(struct snd_kcontrol *kcontrol,
1712                                    struct snd_ctl_elem_value *ucontrol)
1713 {
1714         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1715         int mask = kcontrol->private_value;
1716
1717         spin_lock_irq(&ensoniq->reg_lock);
1718         ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0;
1719         spin_unlock_irq(&ensoniq->reg_lock);
1720         return 0;
1721 }
1722
1723 static int snd_ensoniq_control_put(struct snd_kcontrol *kcontrol,
1724                                    struct snd_ctl_elem_value *ucontrol)
1725 {
1726         struct ensoniq *ensoniq = snd_kcontrol_chip(kcontrol);
1727         int mask = kcontrol->private_value;
1728         unsigned int nval;
1729         int change;
1730
1731         nval = ucontrol->value.integer.value[0] ? mask : 0;
1732         spin_lock_irq(&ensoniq->reg_lock);
1733         change = (ensoniq->ctrl & mask) != nval;
1734         ensoniq->ctrl &= ~mask;
1735         ensoniq->ctrl |= nval;
1736         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1737         spin_unlock_irq(&ensoniq->reg_lock);
1738         return change;
1739 }
1740
1741 /*
1742  * ENS1370 mixer
1743  */
1744
1745 static struct snd_kcontrol_new snd_es1370_controls[2] __devinitdata = {
1746 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0),
1747 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1)
1748 };
1749
1750 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1751
1752 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531 *ak4531)
1753 {
1754         struct ensoniq *ensoniq = ak4531->private_data;
1755         ensoniq->u.es1370.ak4531 = NULL;
1756 }
1757
1758 static int __devinit snd_ensoniq_1370_mixer(struct ensoniq * ensoniq)
1759 {
1760         struct snd_card *card = ensoniq->card;
1761         struct snd_ak4531 ak4531;
1762         unsigned int idx;
1763         int err;
1764
1765         /* try reset AK4531 */
1766         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
1767         inw(ES_REG(ensoniq, 1370_CODEC));
1768         udelay(100);
1769         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
1770         inw(ES_REG(ensoniq, 1370_CODEC));
1771         udelay(100);
1772
1773         memset(&ak4531, 0, sizeof(ak4531));
1774         ak4531.write = snd_es1370_codec_write;
1775         ak4531.private_data = ensoniq;
1776         ak4531.private_free = snd_ensoniq_mixer_free_ak4531;
1777         if ((err = snd_ak4531_mixer(card, &ak4531, &ensoniq->u.es1370.ak4531)) < 0)
1778                 return err;
1779         for (idx = 0; idx < ES1370_CONTROLS; idx++) {
1780                 err = snd_ctl_add(card, snd_ctl_new1(&snd_es1370_controls[idx], ensoniq));
1781                 if (err < 0)
1782                         return err;
1783         }
1784         return 0;
1785 }
1786
1787 #endif /* CHIP1370 */
1788
1789 #ifdef SUPPORT_JOYSTICK
1790
1791 #ifdef CHIP1371
1792 static int __devinit snd_ensoniq_get_joystick_port(int dev)
1793 {
1794         switch (joystick_port[dev]) {
1795         case 0: /* disabled */
1796         case 1: /* auto-detect */
1797         case 0x200:
1798         case 0x208:
1799         case 0x210:
1800         case 0x218:
1801                 return joystick_port[dev];
1802
1803         default:
1804                 printk(KERN_ERR "ens1371: invalid joystick port %#x", joystick_port[dev]);
1805                 return 0;
1806         }
1807 }
1808 #else
1809 static inline int snd_ensoniq_get_joystick_port(int dev)
1810 {
1811         return joystick[dev] ? 0x200 : 0;
1812 }
1813 #endif
1814
1815 static int __devinit snd_ensoniq_create_gameport(struct ensoniq *ensoniq, int dev)
1816 {
1817         struct gameport *gp;
1818         int io_port;
1819
1820         io_port = snd_ensoniq_get_joystick_port(dev);
1821
1822         switch (io_port) {
1823         case 0:
1824                 return -ENOSYS;
1825
1826         case 1: /* auto_detect */
1827                 for (io_port = 0x200; io_port <= 0x218; io_port += 8)
1828                         if (request_region(io_port, 8, "ens137x: gameport"))
1829                                 break;
1830                 if (io_port > 0x218) {
1831                         printk(KERN_WARNING "ens137x: no gameport ports available\n");
1832                         return -EBUSY;
1833                 }
1834                 break;
1835
1836         default:
1837                 if (!request_region(io_port, 8, "ens137x: gameport")) {
1838                         printk(KERN_WARNING "ens137x: gameport io port 0x%#x in use\n",
1839                                io_port);
1840                         return -EBUSY;
1841                 }
1842                 break;
1843         }
1844
1845         ensoniq->gameport = gp = gameport_allocate_port();
1846         if (!gp) {
1847                 printk(KERN_ERR "ens137x: cannot allocate memory for gameport\n");
1848                 release_region(io_port, 8);
1849                 return -ENOMEM;
1850         }
1851
1852         gameport_set_name(gp, "ES137x");
1853         gameport_set_phys(gp, "pci%s/gameport0", pci_name(ensoniq->pci));
1854         gameport_set_dev_parent(gp, &ensoniq->pci->dev);
1855         gp->io = io_port;
1856
1857         ensoniq->ctrl |= ES_JYSTK_EN;
1858 #ifdef CHIP1371
1859         ensoniq->ctrl &= ~ES_1371_JOY_ASELM;
1860         ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8);
1861 #endif
1862         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1863
1864         gameport_register_port(ensoniq->gameport);
1865
1866         return 0;
1867 }
1868
1869 static void snd_ensoniq_free_gameport(struct ensoniq *ensoniq)
1870 {
1871         if (ensoniq->gameport) {
1872                 int port = ensoniq->gameport->io;
1873
1874                 gameport_unregister_port(ensoniq->gameport);
1875                 ensoniq->gameport = NULL;
1876                 ensoniq->ctrl &= ~ES_JYSTK_EN;
1877                 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1878                 release_region(port, 8);
1879         }
1880 }
1881 #else
1882 static inline int snd_ensoniq_create_gameport(struct ensoniq *ensoniq, long port) { return -ENOSYS; }
1883 static inline void snd_ensoniq_free_gameport(struct ensoniq *ensoniq) { }
1884 #endif /* SUPPORT_JOYSTICK */
1885
1886 /*
1887
1888  */
1889
1890 static void snd_ensoniq_proc_read(struct snd_info_entry *entry,
1891                                   struct snd_info_buffer *buffer)
1892 {
1893         struct ensoniq *ensoniq = entry->private_data;
1894
1895 #ifdef CHIP1370
1896         snd_iprintf(buffer, "Ensoniq AudioPCI ES1370\n\n");
1897 #else
1898         snd_iprintf(buffer, "Ensoniq AudioPCI ES1371\n\n");
1899 #endif
1900         snd_iprintf(buffer, "Joystick enable  : %s\n",
1901                     ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off");
1902 #ifdef CHIP1370
1903         snd_iprintf(buffer, "MIC +5V bias     : %s\n",
1904                     ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off");
1905         snd_iprintf(buffer, "Line In to AOUT  : %s\n",
1906                     ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off");
1907 #else
1908         snd_iprintf(buffer, "Joystick port    : 0x%x\n",
1909                     (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200);
1910 #endif
1911 }
1912
1913 static void __devinit snd_ensoniq_proc_init(struct ensoniq * ensoniq)
1914 {
1915         struct snd_info_entry *entry;
1916
1917         if (! snd_card_proc_new(ensoniq->card, "audiopci", &entry))
1918                 snd_info_set_text_ops(entry, ensoniq, 1024, snd_ensoniq_proc_read);
1919 }
1920
1921 /*
1922
1923  */
1924
1925 static int snd_ensoniq_free(struct ensoniq *ensoniq)
1926 {
1927         snd_ensoniq_free_gameport(ensoniq);
1928         if (ensoniq->irq < 0)
1929                 goto __hw_end;
1930 #ifdef CHIP1370
1931         outl(ES_1370_SERR_DISABLE, ES_REG(ensoniq, CONTROL));   /* switch everything off */
1932         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1933 #else
1934         outl(0, ES_REG(ensoniq, CONTROL));      /* switch everything off */
1935         outl(0, ES_REG(ensoniq, SERIAL));       /* clear serial interface */
1936 #endif
1937         synchronize_irq(ensoniq->irq);
1938         pci_set_power_state(ensoniq->pci, 3);
1939       __hw_end:
1940 #ifdef CHIP1370
1941         if (ensoniq->dma_bug.area)
1942                 snd_dma_free_pages(&ensoniq->dma_bug);
1943 #endif
1944         if (ensoniq->irq >= 0)
1945                 free_irq(ensoniq->irq, ensoniq);
1946         pci_release_regions(ensoniq->pci);
1947         pci_disable_device(ensoniq->pci);
1948         kfree(ensoniq);
1949         return 0;
1950 }
1951
1952 static int snd_ensoniq_dev_free(struct snd_device *device)
1953 {
1954         struct ensoniq *ensoniq = device->device_data;
1955         return snd_ensoniq_free(ensoniq);
1956 }
1957
1958 #ifdef CHIP1371
1959 static struct {
1960         unsigned short svid;            /* subsystem vendor ID */
1961         unsigned short sdid;            /* subsystem device ID */
1962 } es1371_amplifier_hack[] = {
1963         { .svid = 0x107b, .sdid = 0x2150 },     /* Gateway Solo 2150 */
1964         { .svid = 0x13bd, .sdid = 0x100c },     /* EV1938 on Mebius PC-MJ100V */
1965         { .svid = 0x1102, .sdid = 0x5938 },     /* Targa Xtender300 */
1966         { .svid = 0x1102, .sdid = 0x8938 },     /* IPC Topnote G notebook */
1967         { .svid = PCI_ANY_ID, .sdid = PCI_ANY_ID }
1968 };
1969 static struct {
1970         unsigned short vid;             /* vendor ID */
1971         unsigned short did;             /* device ID */
1972         unsigned char rev;              /* revision */
1973 } es1371_ac97_reset_hack[] = {
1974         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_C },
1975         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_D },
1976         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_CT5880, .rev = CT5880REV_CT5880_E },
1977         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_CT5880_A },
1978         { .vid = PCI_VENDOR_ID_ENSONIQ, .did = PCI_DEVICE_ID_ENSONIQ_ES1371, .rev = ES1371REV_ES1373_8 },
1979         { .vid = PCI_ANY_ID, .did = PCI_ANY_ID }
1980 };
1981 #endif
1982
1983 static void snd_ensoniq_chip_init(struct ensoniq *ensoniq)
1984 {
1985 #ifdef CHIP1371
1986         int idx;
1987         struct pci_dev *pci = ensoniq->pci;
1988 #endif
1989         /* this code was part of snd_ensoniq_create before intruduction
1990           * of suspend/resume
1991           */
1992 #ifdef CHIP1370
1993         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
1994         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
1995         outl(ES_MEM_PAGEO(ES_PAGE_ADC), ES_REG(ensoniq, MEM_PAGE));
1996         outl(ensoniq->dma_bug.addr, ES_REG(ensoniq, PHANTOM_FRAME));
1997         outl(0, ES_REG(ensoniq, PHANTOM_COUNT));
1998 #else
1999         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2000         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2001         outl(0, ES_REG(ensoniq, 1371_LEGACY));
2002         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2003                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2004                     pci->device == es1371_ac97_reset_hack[idx].did &&
2005                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2006                         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2007                         /* need to delay around 20ms(bleech) to give
2008                         some CODECs enough time to wakeup */
2009                         msleep(20);
2010                         break;
2011                 }
2012         /* AC'97 warm reset to start the bitclk */
2013         outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL));
2014         inl(ES_REG(ensoniq, CONTROL));
2015         udelay(20);
2016         outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
2017         /* Init the sample rate converter */
2018         snd_es1371_wait_src_ready(ensoniq);
2019         outl(ES_1371_SRC_DISABLE, ES_REG(ensoniq, 1371_SMPRATE));
2020         for (idx = 0; idx < 0x80; idx++)
2021                 snd_es1371_src_write(ensoniq, idx, 0);
2022         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_TRUNC_N, 16 << 4);
2023         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC1 + ES_SMPREG_INT_REGS, 16 << 10);
2024         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_TRUNC_N, 16 << 4);
2025         snd_es1371_src_write(ensoniq, ES_SMPREG_DAC2 + ES_SMPREG_INT_REGS, 16 << 10);
2026         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC, 1 << 12);
2027         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_ADC + 1, 1 << 12);
2028         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1, 1 << 12);
2029         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC1 + 1, 1 << 12);
2030         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2, 1 << 12);
2031         snd_es1371_src_write(ensoniq, ES_SMPREG_VOL_DAC2 + 1, 1 << 12);
2032         snd_es1371_adc_rate(ensoniq, 22050);
2033         snd_es1371_dac1_rate(ensoniq, 22050);
2034         snd_es1371_dac2_rate(ensoniq, 22050);
2035         /* WARNING:
2036          * enabling the sample rate converter without properly programming
2037          * its parameters causes the chip to lock up (the SRC busy bit will
2038          * be stuck high, and I've found no way to rectify this other than
2039          * power cycle) - Thomas Sailer
2040          */
2041         snd_es1371_wait_src_ready(ensoniq);
2042         outl(0, ES_REG(ensoniq, 1371_SMPRATE));
2043         /* try reset codec directly */
2044         outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq, 1371_CODEC));
2045 #endif
2046         outb(ensoniq->uartc = 0x00, ES_REG(ensoniq, UART_CONTROL));
2047         outb(0x00, ES_REG(ensoniq, UART_RES));
2048         outl(ensoniq->cssr, ES_REG(ensoniq, STATUS));
2049         synchronize_irq(ensoniq->irq);
2050 }
2051
2052 #ifdef CONFIG_PM
2053 static int snd_ensoniq_suspend(struct pci_dev *pci, pm_message_t state)
2054 {
2055         struct snd_card *card = pci_get_drvdata(pci);
2056         struct ensoniq *ensoniq = card->private_data;
2057
2058         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2059
2060         snd_pcm_suspend_all(ensoniq->pcm1);
2061         snd_pcm_suspend_all(ensoniq->pcm2);
2062
2063 #ifdef CHIP1371
2064         snd_ac97_suspend(ensoniq->u.es1371.ac97);
2065 #else
2066         /* try to reset AK4531 */
2067         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x02), ES_REG(ensoniq, 1370_CODEC));
2068         inw(ES_REG(ensoniq, 1370_CODEC));
2069         udelay(100);
2070         outw(ES_1370_CODEC_WRITE(AK4531_RESET, 0x03), ES_REG(ensoniq, 1370_CODEC));
2071         inw(ES_REG(ensoniq, 1370_CODEC));
2072         udelay(100);
2073         snd_ak4531_suspend(ensoniq->u.es1370.ak4531);
2074 #endif
2075         pci_set_power_state(pci, PCI_D3hot);
2076         pci_disable_device(pci);
2077         pci_save_state(pci);
2078         return 0;
2079 }
2080
2081 static int snd_ensoniq_resume(struct pci_dev *pci)
2082 {
2083         struct snd_card *card = pci_get_drvdata(pci);
2084         struct ensoniq *ensoniq = card->private_data;
2085
2086         pci_restore_state(pci);
2087         pci_enable_device(pci);
2088         pci_set_power_state(pci, PCI_D0);
2089         pci_set_master(pci);
2090
2091         snd_ensoniq_chip_init(ensoniq);
2092
2093 #ifdef CHIP1371
2094         snd_ac97_resume(ensoniq->u.es1371.ac97);
2095 #else
2096         snd_ak4531_resume(ensoniq->u.es1370.ak4531);
2097 #endif
2098         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2099         return 0;
2100 }
2101 #endif /* CONFIG_PM */
2102
2103
2104 static int __devinit snd_ensoniq_create(struct snd_card *card,
2105                                      struct pci_dev *pci,
2106                                      struct ensoniq ** rensoniq)
2107 {
2108         struct ensoniq *ensoniq;
2109         unsigned short cmdw;
2110         unsigned char cmdb;
2111 #ifdef CHIP1371
2112         int idx;
2113 #endif
2114         int err;
2115         static struct snd_device_ops ops = {
2116                 .dev_free =     snd_ensoniq_dev_free,
2117         };
2118
2119         *rensoniq = NULL;
2120         if ((err = pci_enable_device(pci)) < 0)
2121                 return err;
2122         ensoniq = kzalloc(sizeof(*ensoniq), GFP_KERNEL);
2123         if (ensoniq == NULL) {
2124                 pci_disable_device(pci);
2125                 return -ENOMEM;
2126         }
2127         spin_lock_init(&ensoniq->reg_lock);
2128         mutex_init(&ensoniq->src_mutex);
2129         ensoniq->card = card;
2130         ensoniq->pci = pci;
2131         ensoniq->irq = -1;
2132         if ((err = pci_request_regions(pci, "Ensoniq AudioPCI")) < 0) {
2133                 kfree(ensoniq);
2134                 pci_disable_device(pci);
2135                 return err;
2136         }
2137         ensoniq->port = pci_resource_start(pci, 0);
2138         if (request_irq(pci->irq, snd_audiopci_interrupt, SA_INTERRUPT|SA_SHIRQ,
2139                         "Ensoniq AudioPCI", ensoniq)) {
2140                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2141                 snd_ensoniq_free(ensoniq);
2142                 return -EBUSY;
2143         }
2144         ensoniq->irq = pci->irq;
2145 #ifdef CHIP1370
2146         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
2147                                 16, &ensoniq->dma_bug) < 0) {
2148                 snd_printk(KERN_ERR "unable to allocate space for phantom area - dma_bug\n");
2149                 snd_ensoniq_free(ensoniq);
2150                 return -EBUSY;
2151         }
2152 #endif
2153         pci_set_master(pci);
2154         pci_read_config_byte(pci, PCI_REVISION_ID, &cmdb);
2155         ensoniq->rev = cmdb;
2156         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &cmdw);
2157         ensoniq->subsystem_vendor_id = cmdw;
2158         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &cmdw);
2159         ensoniq->subsystem_device_id = cmdw;
2160 #ifdef CHIP1370
2161 #if 0
2162         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE |
2163                 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2164 #else   /* get microphone working */
2165         ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2166 #endif
2167         ensoniq->sctrl = 0;
2168 #else
2169         ensoniq->ctrl = 0;
2170         ensoniq->sctrl = 0;
2171         ensoniq->cssr = 0;
2172         for (idx = 0; es1371_amplifier_hack[idx].svid != (unsigned short)PCI_ANY_ID; idx++)
2173                 if (ensoniq->subsystem_vendor_id == es1371_amplifier_hack[idx].svid &&
2174                     ensoniq->subsystem_device_id == es1371_amplifier_hack[idx].sdid) {
2175                         ensoniq->ctrl |= ES_1371_GPIO_OUT(1);   /* turn amplifier on */
2176                         break;
2177                 }
2178         for (idx = 0; es1371_ac97_reset_hack[idx].vid != (unsigned short)PCI_ANY_ID; idx++)
2179                 if (pci->vendor == es1371_ac97_reset_hack[idx].vid &&
2180                     pci->device == es1371_ac97_reset_hack[idx].did &&
2181                     ensoniq->rev == es1371_ac97_reset_hack[idx].rev) {
2182                         ensoniq->cssr |= ES_1371_ST_AC97_RST;
2183                         break;
2184                 }
2185 #endif
2186
2187         snd_ensoniq_chip_init(ensoniq);
2188
2189         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ensoniq, &ops)) < 0) {
2190                 snd_ensoniq_free(ensoniq);
2191                 return err;
2192         }
2193
2194         snd_ensoniq_proc_init(ensoniq);
2195
2196         snd_card_set_dev(card, &pci->dev);
2197
2198         *rensoniq = ensoniq;
2199         return 0;
2200 }
2201
2202 /*
2203  *  MIDI section
2204  */
2205
2206 static void snd_ensoniq_midi_interrupt(struct ensoniq * ensoniq)
2207 {
2208         struct snd_rawmidi *rmidi = ensoniq->rmidi;
2209         unsigned char status, mask, byte;
2210
2211         if (rmidi == NULL)
2212                 return;
2213         /* do Rx at first */
2214         spin_lock(&ensoniq->reg_lock);
2215         mask = ensoniq->uartm & ES_MODE_INPUT ? ES_RXRDY : 0;
2216         while (mask) {
2217                 status = inb(ES_REG(ensoniq, UART_STATUS));
2218                 if ((status & mask) == 0)
2219                         break;
2220                 byte = inb(ES_REG(ensoniq, UART_DATA));
2221                 snd_rawmidi_receive(ensoniq->midi_input, &byte, 1);
2222         }
2223         spin_unlock(&ensoniq->reg_lock);
2224
2225         /* do Tx at second */
2226         spin_lock(&ensoniq->reg_lock);
2227         mask = ensoniq->uartm & ES_MODE_OUTPUT ? ES_TXRDY : 0;
2228         while (mask) {
2229                 status = inb(ES_REG(ensoniq, UART_STATUS));
2230                 if ((status & mask) == 0)
2231                         break;
2232                 if (snd_rawmidi_transmit(ensoniq->midi_output, &byte, 1) != 1) {
2233                         ensoniq->uartc &= ~ES_TXINTENM;
2234                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2235                         mask &= ~ES_TXRDY;
2236                 } else {
2237                         outb(byte, ES_REG(ensoniq, UART_DATA));
2238                 }
2239         }
2240         spin_unlock(&ensoniq->reg_lock);
2241 }
2242
2243 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream *substream)
2244 {
2245         struct ensoniq *ensoniq = substream->rmidi->private_data;
2246
2247         spin_lock_irq(&ensoniq->reg_lock);
2248         ensoniq->uartm |= ES_MODE_INPUT;
2249         ensoniq->midi_input = substream;
2250         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2251                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2252                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2253                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2254         }
2255         spin_unlock_irq(&ensoniq->reg_lock);
2256         return 0;
2257 }
2258
2259 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream *substream)
2260 {
2261         struct ensoniq *ensoniq = substream->rmidi->private_data;
2262
2263         spin_lock_irq(&ensoniq->reg_lock);
2264         if (!(ensoniq->uartm & ES_MODE_OUTPUT)) {
2265                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2266                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2267         } else {
2268                 outb(ensoniq->uartc &= ~ES_RXINTEN, ES_REG(ensoniq, UART_CONTROL));
2269         }
2270         ensoniq->midi_input = NULL;
2271         ensoniq->uartm &= ~ES_MODE_INPUT;
2272         spin_unlock_irq(&ensoniq->reg_lock);
2273         return 0;
2274 }
2275
2276 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream *substream)
2277 {
2278         struct ensoniq *ensoniq = substream->rmidi->private_data;
2279
2280         spin_lock_irq(&ensoniq->reg_lock);
2281         ensoniq->uartm |= ES_MODE_OUTPUT;
2282         ensoniq->midi_output = substream;
2283         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2284                 outb(ES_CNTRL(3), ES_REG(ensoniq, UART_CONTROL));
2285                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2286                 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL));
2287         }
2288         spin_unlock_irq(&ensoniq->reg_lock);
2289         return 0;
2290 }
2291
2292 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream *substream)
2293 {
2294         struct ensoniq *ensoniq = substream->rmidi->private_data;
2295
2296         spin_lock_irq(&ensoniq->reg_lock);
2297         if (!(ensoniq->uartm & ES_MODE_INPUT)) {
2298                 outb(ensoniq->uartc = 0, ES_REG(ensoniq, UART_CONTROL));
2299                 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL));
2300         } else {
2301                 outb(ensoniq->uartc &= ~ES_TXINTENM, ES_REG(ensoniq, UART_CONTROL));
2302         }
2303         ensoniq->midi_output = NULL;
2304         ensoniq->uartm &= ~ES_MODE_OUTPUT;
2305         spin_unlock_irq(&ensoniq->reg_lock);
2306         return 0;
2307 }
2308
2309 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2310 {
2311         unsigned long flags;
2312         struct ensoniq *ensoniq = substream->rmidi->private_data;
2313         int idx;
2314
2315         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2316         if (up) {
2317                 if ((ensoniq->uartc & ES_RXINTEN) == 0) {
2318                         /* empty input FIFO */
2319                         for (idx = 0; idx < 32; idx++)
2320                                 inb(ES_REG(ensoniq, UART_DATA));
2321                         ensoniq->uartc |= ES_RXINTEN;
2322                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2323                 }
2324         } else {
2325                 if (ensoniq->uartc & ES_RXINTEN) {
2326                         ensoniq->uartc &= ~ES_RXINTEN;
2327                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2328                 }
2329         }
2330         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2331 }
2332
2333 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2334 {
2335         unsigned long flags;
2336         struct ensoniq *ensoniq = substream->rmidi->private_data;
2337         unsigned char byte;
2338
2339         spin_lock_irqsave(&ensoniq->reg_lock, flags);
2340         if (up) {
2341                 if (ES_TXINTENI(ensoniq->uartc) == 0) {
2342                         ensoniq->uartc |= ES_TXINTENO(1);
2343                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2344                         while (ES_TXINTENI(ensoniq->uartc) == 1 &&
2345                                (inb(ES_REG(ensoniq, UART_STATUS)) & ES_TXRDY)) {
2346                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2347                                         ensoniq->uartc &= ~ES_TXINTENM;
2348                                 } else {
2349                                         outb(byte, ES_REG(ensoniq, UART_DATA));
2350                                 }
2351                         }
2352                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2353                 }
2354         } else {
2355                 if (ES_TXINTENI(ensoniq->uartc) == 1) {
2356                         ensoniq->uartc &= ~ES_TXINTENM;
2357                         outb(ensoniq->uartc, ES_REG(ensoniq, UART_CONTROL));
2358                 }
2359         }
2360         spin_unlock_irqrestore(&ensoniq->reg_lock, flags);
2361 }
2362
2363 static struct snd_rawmidi_ops snd_ensoniq_midi_output =
2364 {
2365         .open =         snd_ensoniq_midi_output_open,
2366         .close =        snd_ensoniq_midi_output_close,
2367         .trigger =      snd_ensoniq_midi_output_trigger,
2368 };
2369
2370 static struct snd_rawmidi_ops snd_ensoniq_midi_input =
2371 {
2372         .open =         snd_ensoniq_midi_input_open,
2373         .close =        snd_ensoniq_midi_input_close,
2374         .trigger =      snd_ensoniq_midi_input_trigger,
2375 };
2376
2377 static int __devinit snd_ensoniq_midi(struct ensoniq * ensoniq, int device,
2378                                       struct snd_rawmidi **rrawmidi)
2379 {
2380         struct snd_rawmidi *rmidi;
2381         int err;
2382
2383         if (rrawmidi)
2384                 *rrawmidi = NULL;
2385         if ((err = snd_rawmidi_new(ensoniq->card, "ES1370/1", device, 1, 1, &rmidi)) < 0)
2386                 return err;
2387 #ifdef CHIP1370
2388         strcpy(rmidi->name, "ES1370");
2389 #else
2390         strcpy(rmidi->name, "ES1371");
2391 #endif
2392         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_ensoniq_midi_output);
2393         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_ensoniq_midi_input);
2394         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT |
2395                 SNDRV_RAWMIDI_INFO_DUPLEX;
2396         rmidi->private_data = ensoniq;
2397         ensoniq->rmidi = rmidi;
2398         if (rrawmidi)
2399                 *rrawmidi = rmidi;
2400         return 0;
2401 }
2402
2403 /*
2404  *  Interrupt handler
2405  */
2406
2407 static irqreturn_t snd_audiopci_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2408 {
2409         struct ensoniq *ensoniq = dev_id;
2410         unsigned int status, sctrl;
2411
2412         if (ensoniq == NULL)
2413                 return IRQ_NONE;
2414
2415         status = inl(ES_REG(ensoniq, STATUS));
2416         if (!(status & ES_INTR))
2417                 return IRQ_NONE;
2418
2419         spin_lock(&ensoniq->reg_lock);
2420         sctrl = ensoniq->sctrl;
2421         if (status & ES_DAC1)
2422                 sctrl &= ~ES_P1_INT_EN;
2423         if (status & ES_DAC2)
2424                 sctrl &= ~ES_P2_INT_EN;
2425         if (status & ES_ADC)
2426                 sctrl &= ~ES_R1_INT_EN;
2427         outl(sctrl, ES_REG(ensoniq, SERIAL));
2428         outl(ensoniq->sctrl, ES_REG(ensoniq, SERIAL));
2429         spin_unlock(&ensoniq->reg_lock);
2430
2431         if (status & ES_UART)
2432                 snd_ensoniq_midi_interrupt(ensoniq);
2433         if ((status & ES_DAC2) && ensoniq->playback2_substream)
2434                 snd_pcm_period_elapsed(ensoniq->playback2_substream);
2435         if ((status & ES_ADC) && ensoniq->capture_substream)
2436                 snd_pcm_period_elapsed(ensoniq->capture_substream);
2437         if ((status & ES_DAC1) && ensoniq->playback1_substream)
2438                 snd_pcm_period_elapsed(ensoniq->playback1_substream);
2439         return IRQ_HANDLED;
2440 }
2441
2442 static int __devinit snd_audiopci_probe(struct pci_dev *pci,
2443                                         const struct pci_device_id *pci_id)
2444 {
2445         static int dev;
2446         struct snd_card *card;
2447         struct ensoniq *ensoniq;
2448         int err, pcm_devs[2];
2449
2450         if (dev >= SNDRV_CARDS)
2451                 return -ENODEV;
2452         if (!enable[dev]) {
2453                 dev++;
2454                 return -ENOENT;
2455         }
2456
2457         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2458         if (card == NULL)
2459                 return -ENOMEM;
2460
2461         if ((err = snd_ensoniq_create(card, pci, &ensoniq)) < 0) {
2462                 snd_card_free(card);
2463                 return err;
2464         }
2465         card->private_data = ensoniq;
2466
2467         pcm_devs[0] = 0; pcm_devs[1] = 1;
2468 #ifdef CHIP1370
2469         if ((err = snd_ensoniq_1370_mixer(ensoniq)) < 0) {
2470                 snd_card_free(card);
2471                 return err;
2472         }
2473 #endif
2474 #ifdef CHIP1371
2475         if ((err = snd_ensoniq_1371_mixer(ensoniq, spdif[dev], lineio[dev])) < 0) {
2476                 snd_card_free(card);
2477                 return err;
2478         }
2479 #endif
2480         if ((err = snd_ensoniq_pcm(ensoniq, 0, NULL)) < 0) {
2481                 snd_card_free(card);
2482                 return err;
2483         }
2484         if ((err = snd_ensoniq_pcm2(ensoniq, 1, NULL)) < 0) {
2485                 snd_card_free(card);
2486                 return err;
2487         }
2488         if ((err = snd_ensoniq_midi(ensoniq, 0, NULL)) < 0) {
2489                 snd_card_free(card);
2490                 return err;
2491         }
2492
2493         snd_ensoniq_create_gameport(ensoniq, dev);
2494
2495         strcpy(card->driver, DRIVER_NAME);
2496
2497         strcpy(card->shortname, "Ensoniq AudioPCI");
2498         sprintf(card->longname, "%s %s at 0x%lx, irq %i",
2499                 card->shortname,
2500                 card->driver,
2501                 ensoniq->port,
2502                 ensoniq->irq);
2503
2504         if ((err = snd_card_register(card)) < 0) {
2505                 snd_card_free(card);
2506                 return err;
2507         }
2508
2509         pci_set_drvdata(pci, card);
2510         dev++;
2511         return 0;
2512 }
2513
2514 static void __devexit snd_audiopci_remove(struct pci_dev *pci)
2515 {
2516         snd_card_free(pci_get_drvdata(pci));
2517         pci_set_drvdata(pci, NULL);
2518 }
2519
2520 static struct pci_driver driver = {
2521         .name = DRIVER_NAME,
2522         .id_table = snd_audiopci_ids,
2523         .probe = snd_audiopci_probe,
2524         .remove = __devexit_p(snd_audiopci_remove),
2525 #ifdef CONFIG_PM
2526         .suspend = snd_ensoniq_suspend,
2527         .resume = snd_ensoniq_resume,
2528 #endif
2529 };
2530
2531 static int __init alsa_card_ens137x_init(void)
2532 {
2533         return pci_register_driver(&driver);
2534 }
2535
2536 static void __exit alsa_card_ens137x_exit(void)
2537 {
2538         pci_unregister_driver(&driver);
2539 }
2540
2541 module_init(alsa_card_ens137x_init)
2542 module_exit(alsa_card_ens137x_exit)