3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <sound/driver.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
53 static int index = SNDRV_DEFAULT_IDX1;
54 static char *id = SNDRV_DEFAULT_STR1;
56 static int position_fix;
57 static int probe_mask = -1;
58 static int single_cmd;
59 static int enable_msi;
61 module_param(index, int, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param(id, charp, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param(model, charp, 0444);
66 MODULE_PARM_DESC(model, "Use the given board model.");
67 module_param(position_fix, int, 0444);
68 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
69 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
70 module_param(probe_mask, int, 0444);
71 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
72 module_param(single_cmd, bool, 0444);
73 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
74 "(for debugging only).");
75 module_param(enable_msi, int, 0);
76 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
78 #ifdef CONFIG_SND_HDA_POWER_SAVE
79 /* power_save option is defined in hda_codec.c */
81 /* reset the HD-audio controller in power save mode.
82 * this may give more power-saving, but will take longer time to
85 static int power_save_controller = 1;
86 module_param(power_save_controller, bool, 0644);
87 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
90 /* just for backward compatibility */
92 module_param(enable, bool, 0444);
94 MODULE_LICENSE("GPL");
95 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
117 MODULE_DESCRIPTION("Intel HDA driver");
119 #define SFX "hda-intel: "
125 #define ICH6_REG_GCAP 0x00
126 #define ICH6_REG_VMIN 0x02
127 #define ICH6_REG_VMAJ 0x03
128 #define ICH6_REG_OUTPAY 0x04
129 #define ICH6_REG_INPAY 0x06
130 #define ICH6_REG_GCTL 0x08
131 #define ICH6_REG_WAKEEN 0x0c
132 #define ICH6_REG_STATESTS 0x0e
133 #define ICH6_REG_GSTS 0x10
134 #define ICH6_REG_INTCTL 0x20
135 #define ICH6_REG_INTSTS 0x24
136 #define ICH6_REG_WALCLK 0x30
137 #define ICH6_REG_SYNC 0x34
138 #define ICH6_REG_CORBLBASE 0x40
139 #define ICH6_REG_CORBUBASE 0x44
140 #define ICH6_REG_CORBWP 0x48
141 #define ICH6_REG_CORBRP 0x4A
142 #define ICH6_REG_CORBCTL 0x4c
143 #define ICH6_REG_CORBSTS 0x4d
144 #define ICH6_REG_CORBSIZE 0x4e
146 #define ICH6_REG_RIRBLBASE 0x50
147 #define ICH6_REG_RIRBUBASE 0x54
148 #define ICH6_REG_RIRBWP 0x58
149 #define ICH6_REG_RINTCNT 0x5a
150 #define ICH6_REG_RIRBCTL 0x5c
151 #define ICH6_REG_RIRBSTS 0x5d
152 #define ICH6_REG_RIRBSIZE 0x5e
154 #define ICH6_REG_IC 0x60
155 #define ICH6_REG_IR 0x64
156 #define ICH6_REG_IRS 0x68
157 #define ICH6_IRS_VALID (1<<1)
158 #define ICH6_IRS_BUSY (1<<0)
160 #define ICH6_REG_DPLBASE 0x70
161 #define ICH6_REG_DPUBASE 0x74
162 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
167 /* stream register offsets from stream base */
168 #define ICH6_REG_SD_CTL 0x00
169 #define ICH6_REG_SD_STS 0x03
170 #define ICH6_REG_SD_LPIB 0x04
171 #define ICH6_REG_SD_CBL 0x08
172 #define ICH6_REG_SD_LVI 0x0c
173 #define ICH6_REG_SD_FIFOW 0x0e
174 #define ICH6_REG_SD_FIFOSIZE 0x10
175 #define ICH6_REG_SD_FORMAT 0x12
176 #define ICH6_REG_SD_BDLPL 0x18
177 #define ICH6_REG_SD_BDLPU 0x1c
180 #define ICH6_PCIREG_TCSEL 0x44
186 /* max number of SDs */
187 /* ICH, ATI and VIA have 4 playback and 4 capture */
188 #define ICH6_CAPTURE_INDEX 0
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_PLAYBACK_INDEX 4
191 #define ICH6_NUM_PLAYBACK 4
193 /* ULI has 6 playback and 5 capture */
194 #define ULI_CAPTURE_INDEX 0
195 #define ULI_NUM_CAPTURE 5
196 #define ULI_PLAYBACK_INDEX 5
197 #define ULI_NUM_PLAYBACK 6
199 /* ATI HDMI has 1 playback and 0 capture */
200 #define ATIHDMI_CAPTURE_INDEX 0
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_PLAYBACK_INDEX 0
203 #define ATIHDMI_NUM_PLAYBACK 1
205 /* this number is statically defined for simplicity */
206 #define MAX_AZX_DEV 16
208 /* max number of fragments - we may use more if allocating more pages for BDL */
209 #define BDL_SIZE PAGE_ALIGN(8192)
210 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
211 /* max buffer size - no h/w limit, you can increase as you like */
212 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
213 /* max number of PCM devics per card */
214 #define AZX_MAX_AUDIO_PCMS 6
215 #define AZX_MAX_MODEM_PCMS 2
216 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
218 /* RIRB int mask: overrun[2], response[0] */
219 #define RIRB_INT_RESPONSE 0x01
220 #define RIRB_INT_OVERRUN 0x04
221 #define RIRB_INT_MASK 0x05
223 /* STATESTS int mask: SD2,SD1,SD0 */
224 #define AZX_MAX_CODECS 3
225 #define STATESTS_INT_MASK 0x07
228 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
229 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
230 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
231 #define SD_CTL_STREAM_TAG_SHIFT 20
233 /* SD_CTL and SD_STS */
234 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
235 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
236 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
237 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
241 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
243 /* INTCTL and INTSTS */
244 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
245 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
246 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
248 /* GCTL unsolicited response enable bit */
249 #define ICH6_GCTL_UREN (1<<8)
252 #define ICH6_GCTL_RESET (1<<0)
254 /* CORB/RIRB control, read/write pointer */
255 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
256 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
257 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
258 /* below are so far hardcoded - should read registers in future */
259 #define ICH6_MAX_CORB_ENTRIES 256
260 #define ICH6_MAX_RIRB_ENTRIES 256
262 /* position fix mode */
270 /* Defines for ATI HD Audio support in SB450 south bridge */
271 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
272 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
274 /* Defines for Nvidia HDA support */
275 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
276 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
282 u32 *bdl; /* virtual address of the BDL */
283 dma_addr_t bdl_addr; /* physical address of the BDL */
284 u32 *posbuf; /* position buffer pointer */
286 unsigned int bufsize; /* size of the play buffer in bytes */
287 unsigned int fragsize; /* size of each period in bytes */
288 unsigned int frags; /* number for period in the play buffer */
289 unsigned int fifo_size; /* FIFO size */
291 void __iomem *sd_addr; /* stream descriptor pointer */
293 u32 sd_int_sta_mask; /* stream int status mask */
296 struct snd_pcm_substream *substream; /* assigned substream,
299 unsigned int format_val; /* format value to be set in the
300 * controller and the codec
302 unsigned char stream_tag; /* assigned stream */
303 unsigned char index; /* stream index */
304 /* for sanity check of position buffer */
305 unsigned int period_intr;
307 unsigned int opened :1;
308 unsigned int running :1;
313 u32 *buf; /* CORB/RIRB buffer
314 * Each CORB entry is 4byte, RIRB is 8byte
316 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
318 unsigned short rp, wp; /* read/write pointers */
319 int cmds; /* number of pending requests */
320 u32 res; /* last read value */
324 struct snd_card *card;
327 /* chip type specific */
329 int playback_streams;
330 int playback_index_offset;
332 int capture_index_offset;
337 void __iomem *remap_addr;
342 struct mutex open_mutex;
344 /* streams (x num_streams) */
345 struct azx_dev *azx_dev;
348 unsigned int pcm_devs;
349 struct snd_pcm *pcm[AZX_MAX_PCMS];
352 unsigned short codec_mask;
359 /* BDL, CORB/RIRB and position buffers */
360 struct snd_dma_buffer bdl;
361 struct snd_dma_buffer rb;
362 struct snd_dma_buffer posbuf;
366 unsigned int running :1;
367 unsigned int initialized :1;
368 unsigned int single_cmd :1;
369 unsigned int polling_mode :1;
373 unsigned int last_cmd; /* last issued command (to sync) */
387 static char *driver_short_names[] __devinitdata = {
388 [AZX_DRIVER_ICH] = "HDA Intel",
389 [AZX_DRIVER_ATI] = "HDA ATI SB",
390 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
391 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
392 [AZX_DRIVER_SIS] = "HDA SIS966",
393 [AZX_DRIVER_ULI] = "HDA ULI M5461",
394 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
398 * macros for easy use
400 #define azx_writel(chip,reg,value) \
401 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
402 #define azx_readl(chip,reg) \
403 readl((chip)->remap_addr + ICH6_REG_##reg)
404 #define azx_writew(chip,reg,value) \
405 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
406 #define azx_readw(chip,reg) \
407 readw((chip)->remap_addr + ICH6_REG_##reg)
408 #define azx_writeb(chip,reg,value) \
409 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
410 #define azx_readb(chip,reg) \
411 readb((chip)->remap_addr + ICH6_REG_##reg)
413 #define azx_sd_writel(dev,reg,value) \
414 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
415 #define azx_sd_readl(dev,reg) \
416 readl((dev)->sd_addr + ICH6_REG_##reg)
417 #define azx_sd_writew(dev,reg,value) \
418 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
419 #define azx_sd_readw(dev,reg) \
420 readw((dev)->sd_addr + ICH6_REG_##reg)
421 #define azx_sd_writeb(dev,reg,value) \
422 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
423 #define azx_sd_readb(dev,reg) \
424 readb((dev)->sd_addr + ICH6_REG_##reg)
426 /* for pcm support */
427 #define get_azx_dev(substream) (substream->runtime->private_data)
429 /* Get the upper 32bit of the given dma_addr_t
430 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
432 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
434 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
437 * Interface for HD codec
441 * CORB / RIRB interface
443 static int azx_alloc_cmd_io(struct azx *chip)
447 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
448 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
449 snd_dma_pci_data(chip->pci),
450 PAGE_SIZE, &chip->rb);
452 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
458 static void azx_init_cmd_io(struct azx *chip)
461 chip->corb.addr = chip->rb.addr;
462 chip->corb.buf = (u32 *)chip->rb.area;
463 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
464 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
466 /* set the corb size to 256 entries (ULI requires explicitly) */
467 azx_writeb(chip, CORBSIZE, 0x02);
468 /* set the corb write pointer to 0 */
469 azx_writew(chip, CORBWP, 0);
470 /* reset the corb hw read pointer */
471 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
472 /* enable corb dma */
473 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
476 chip->rirb.addr = chip->rb.addr + 2048;
477 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
478 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
479 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
481 /* set the rirb size to 256 entries (ULI requires explicitly) */
482 azx_writeb(chip, RIRBSIZE, 0x02);
483 /* reset the rirb hw write pointer */
484 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
485 /* set N=1, get RIRB response interrupt for new entry */
486 azx_writew(chip, RINTCNT, 1);
487 /* enable rirb dma and response irq */
488 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
489 chip->rirb.rp = chip->rirb.cmds = 0;
492 static void azx_free_cmd_io(struct azx *chip)
494 /* disable ringbuffer DMAs */
495 azx_writeb(chip, RIRBCTL, 0);
496 azx_writeb(chip, CORBCTL, 0);
500 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
502 struct azx *chip = codec->bus->private_data;
505 /* add command to corb */
506 wp = azx_readb(chip, CORBWP);
508 wp %= ICH6_MAX_CORB_ENTRIES;
510 spin_lock_irq(&chip->reg_lock);
512 chip->corb.buf[wp] = cpu_to_le32(val);
513 azx_writel(chip, CORBWP, wp);
514 spin_unlock_irq(&chip->reg_lock);
519 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
521 /* retrieve RIRB entry - called from interrupt handler */
522 static void azx_update_rirb(struct azx *chip)
527 wp = azx_readb(chip, RIRBWP);
528 if (wp == chip->rirb.wp)
532 while (chip->rirb.rp != wp) {
534 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
536 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
537 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
538 res = le32_to_cpu(chip->rirb.buf[rp]);
539 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
540 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
541 else if (chip->rirb.cmds) {
543 chip->rirb.res = res;
548 /* receive a response */
549 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
551 struct azx *chip = codec->bus->private_data;
552 unsigned long timeout;
555 timeout = jiffies + msecs_to_jiffies(1000);
557 if (chip->polling_mode) {
558 spin_lock_irq(&chip->reg_lock);
559 azx_update_rirb(chip);
560 spin_unlock_irq(&chip->reg_lock);
562 if (!chip->rirb.cmds)
563 return chip->rirb.res; /* the last value */
566 } while (time_after_eq(timeout, jiffies));
569 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
570 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
571 free_irq(chip->irq, chip);
573 pci_disable_msi(chip->pci);
575 if (azx_acquire_irq(chip, 1) < 0)
580 if (!chip->polling_mode) {
581 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
582 "switching to polling mode: last cmd=0x%08x\n",
584 chip->polling_mode = 1;
588 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
589 "switching to single_cmd mode: last cmd=0x%08x\n",
591 chip->rirb.rp = azx_readb(chip, RIRBWP);
593 /* switch to single_cmd mode */
594 chip->single_cmd = 1;
595 azx_free_cmd_io(chip);
600 * Use the single immediate command instead of CORB/RIRB for simplicity
602 * Note: according to Intel, this is not preferred use. The command was
603 * intended for the BIOS only, and may get confused with unsolicited
604 * responses. So, we shouldn't use it for normal operation from the
606 * I left the codes, however, for debugging/testing purposes.
610 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
612 struct azx *chip = codec->bus->private_data;
616 /* check ICB busy bit */
617 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
618 /* Clear IRV valid bit */
619 azx_writew(chip, IRS, azx_readw(chip, IRS) |
621 azx_writel(chip, IC, val);
622 azx_writew(chip, IRS, azx_readw(chip, IRS) |
628 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
629 azx_readw(chip, IRS), val);
633 /* receive a response */
634 static unsigned int azx_single_get_response(struct hda_codec *codec)
636 struct azx *chip = codec->bus->private_data;
640 /* check IRV busy bit */
641 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
642 return azx_readl(chip, IR);
645 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
646 azx_readw(chip, IRS));
647 return (unsigned int)-1;
651 * The below are the main callbacks from hda_codec.
653 * They are just the skeleton to call sub-callbacks according to the
654 * current setting of chip->single_cmd.
658 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
659 int direct, unsigned int verb,
662 struct azx *chip = codec->bus->private_data;
665 val = (u32)(codec->addr & 0x0f) << 28;
666 val |= (u32)direct << 27;
667 val |= (u32)nid << 20;
670 chip->last_cmd = val;
672 if (chip->single_cmd)
673 return azx_single_send_cmd(codec, val);
675 return azx_corb_send_cmd(codec, val);
679 static unsigned int azx_get_response(struct hda_codec *codec)
681 struct azx *chip = codec->bus->private_data;
682 if (chip->single_cmd)
683 return azx_single_get_response(codec);
685 return azx_rirb_get_response(codec);
688 #ifdef CONFIG_SND_HDA_POWER_SAVE
689 static void azx_power_notify(struct hda_codec *codec);
692 /* reset codec link */
693 static int azx_reset(struct azx *chip)
698 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
700 /* reset controller */
701 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
704 while (azx_readb(chip, GCTL) && --count)
707 /* delay for >= 100us for codec PLL to settle per spec
708 * Rev 0.9 section 5.5.1
712 /* Bring controller out of reset */
713 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
716 while (!azx_readb(chip, GCTL) && --count)
719 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
722 /* check to see if controller is ready */
723 if (!azx_readb(chip, GCTL)) {
724 snd_printd("azx_reset: controller not ready!\n");
728 /* Accept unsolicited responses */
729 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
732 if (!chip->codec_mask) {
733 chip->codec_mask = azx_readw(chip, STATESTS);
734 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
745 /* enable interrupts */
746 static void azx_int_enable(struct azx *chip)
748 /* enable controller CIE and GIE */
749 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
750 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
753 /* disable interrupts */
754 static void azx_int_disable(struct azx *chip)
758 /* disable interrupts in stream descriptor */
759 for (i = 0; i < chip->num_streams; i++) {
760 struct azx_dev *azx_dev = &chip->azx_dev[i];
761 azx_sd_writeb(azx_dev, SD_CTL,
762 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
765 /* disable SIE for all streams */
766 azx_writeb(chip, INTCTL, 0);
768 /* disable controller CIE and GIE */
769 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
770 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
773 /* clear interrupts */
774 static void azx_int_clear(struct azx *chip)
778 /* clear stream status */
779 for (i = 0; i < chip->num_streams; i++) {
780 struct azx_dev *azx_dev = &chip->azx_dev[i];
781 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
785 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
787 /* clear rirb status */
788 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
790 /* clear int status */
791 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
795 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
798 azx_writeb(chip, INTCTL,
799 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
800 /* set DMA start and interrupt mask */
801 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
802 SD_CTL_DMA_START | SD_INT_MASK);
806 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
809 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
810 ~(SD_CTL_DMA_START | SD_INT_MASK));
811 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
813 azx_writeb(chip, INTCTL,
814 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
819 * reset and start the controller registers
821 static void azx_init_chip(struct azx *chip)
823 if (chip->initialized)
826 /* reset controller */
829 /* initialize interrupts */
831 azx_int_enable(chip);
833 /* initialize the codec command I/O */
834 if (!chip->single_cmd)
835 azx_init_cmd_io(chip);
837 /* program the position buffer */
838 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
839 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
841 chip->initialized = 1;
845 * initialize the PCI registers
847 /* update bits in a PCI register byte */
848 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
849 unsigned char mask, unsigned char val)
853 pci_read_config_byte(pci, reg, &data);
855 data |= (val & mask);
856 pci_write_config_byte(pci, reg, data);
859 static void azx_init_pci(struct azx *chip)
861 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
862 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
863 * Ensuring these bits are 0 clears playback static on some HD Audio
866 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
868 switch (chip->driver_type) {
870 /* For ATI SB450 azalia HD audio, we need to enable snoop */
871 update_pci_byte(chip->pci,
872 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
873 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
875 case AZX_DRIVER_NVIDIA:
876 /* For NVIDIA HDA, enable snoop */
877 update_pci_byte(chip->pci,
878 NVIDIA_HDA_TRANSREG_ADDR,
879 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
888 static irqreturn_t azx_interrupt(int irq, void *dev_id)
890 struct azx *chip = dev_id;
891 struct azx_dev *azx_dev;
895 spin_lock(&chip->reg_lock);
897 status = azx_readl(chip, INTSTS);
899 spin_unlock(&chip->reg_lock);
903 for (i = 0; i < chip->num_streams; i++) {
904 azx_dev = &chip->azx_dev[i];
905 if (status & azx_dev->sd_int_sta_mask) {
906 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
907 if (azx_dev->substream && azx_dev->running) {
908 azx_dev->period_intr++;
909 spin_unlock(&chip->reg_lock);
910 snd_pcm_period_elapsed(azx_dev->substream);
911 spin_lock(&chip->reg_lock);
917 status = azx_readb(chip, RIRBSTS);
918 if (status & RIRB_INT_MASK) {
919 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
920 azx_update_rirb(chip);
921 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
925 /* clear state status int */
926 if (azx_readb(chip, STATESTS) & 0x04)
927 azx_writeb(chip, STATESTS, 0x04);
929 spin_unlock(&chip->reg_lock);
938 static void azx_setup_periods(struct azx_dev *azx_dev)
940 u32 *bdl = azx_dev->bdl;
941 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
944 /* reset BDL address */
945 azx_sd_writel(azx_dev, SD_BDLPL, 0);
946 azx_sd_writel(azx_dev, SD_BDLPU, 0);
948 /* program the initial BDL entries */
949 for (idx = 0; idx < azx_dev->frags; idx++) {
950 unsigned int off = idx << 2; /* 4 dword step */
951 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
952 /* program the address field of the BDL entry */
953 bdl[off] = cpu_to_le32((u32)addr);
954 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
956 /* program the size field of the BDL entry */
957 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
959 /* program the IOC to enable interrupt when buffer completes */
960 bdl[off+3] = cpu_to_le32(0x01);
965 * set up the SD for streaming
967 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
972 /* make sure the run bit is zero for SD */
973 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
976 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
977 SD_CTL_STREAM_RESET);
980 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
983 val &= ~SD_CTL_STREAM_RESET;
984 azx_sd_writeb(azx_dev, SD_CTL, val);
988 /* waiting for hardware to report that the stream is out of reset */
989 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
993 /* program the stream_tag */
994 azx_sd_writel(azx_dev, SD_CTL,
995 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
996 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
998 /* program the length of samples in cyclic buffer */
999 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1001 /* program the stream format */
1002 /* this value needs to be the same as the one programmed */
1003 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1005 /* program the stream LVI (last valid index) of the BDL */
1006 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1008 /* program the BDL address */
1009 /* lower BDL address */
1010 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1011 /* upper BDL address */
1012 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1014 /* enable the position buffer */
1015 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1016 azx_writel(chip, DPLBASE,
1017 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1019 /* set the interrupt enable bits in the descriptor control register */
1020 azx_sd_writel(azx_dev, SD_CTL,
1021 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1028 * Codec initialization
1031 static unsigned int azx_max_codecs[] __devinitdata = {
1032 [AZX_DRIVER_ICH] = 3,
1033 [AZX_DRIVER_ATI] = 4,
1034 [AZX_DRIVER_ATIHDMI] = 4,
1035 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1036 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1037 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1038 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1041 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1043 struct hda_bus_template bus_temp;
1044 int c, codecs, audio_codecs, err;
1046 memset(&bus_temp, 0, sizeof(bus_temp));
1047 bus_temp.private_data = chip;
1048 bus_temp.modelname = model;
1049 bus_temp.pci = chip->pci;
1050 bus_temp.ops.command = azx_send_cmd;
1051 bus_temp.ops.get_response = azx_get_response;
1052 #ifdef CONFIG_SND_HDA_POWER_SAVE
1053 bus_temp.ops.pm_notify = azx_power_notify;
1056 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1060 codecs = audio_codecs = 0;
1061 for (c = 0; c < AZX_MAX_CODECS; c++) {
1062 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1063 struct hda_codec *codec;
1064 err = snd_hda_codec_new(chip->bus, c, &codec);
1072 if (!audio_codecs) {
1073 /* probe additional slots if no codec is found */
1074 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1075 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1076 err = snd_hda_codec_new(chip->bus, c, NULL);
1084 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1096 /* assign a stream for the PCM */
1097 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1100 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1101 dev = chip->playback_index_offset;
1102 nums = chip->playback_streams;
1104 dev = chip->capture_index_offset;
1105 nums = chip->capture_streams;
1107 for (i = 0; i < nums; i++, dev++)
1108 if (!chip->azx_dev[dev].opened) {
1109 chip->azx_dev[dev].opened = 1;
1110 return &chip->azx_dev[dev];
1115 /* release the assigned stream */
1116 static inline void azx_release_device(struct azx_dev *azx_dev)
1118 azx_dev->opened = 0;
1121 static struct snd_pcm_hardware azx_pcm_hw = {
1122 .info = (SNDRV_PCM_INFO_MMAP |
1123 SNDRV_PCM_INFO_INTERLEAVED |
1124 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1125 SNDRV_PCM_INFO_MMAP_VALID |
1126 /* No full-resume yet implemented */
1127 /* SNDRV_PCM_INFO_RESUME |*/
1128 SNDRV_PCM_INFO_PAUSE),
1129 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1130 .rates = SNDRV_PCM_RATE_48000,
1135 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1136 .period_bytes_min = 128,
1137 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1139 .periods_max = AZX_MAX_FRAG,
1145 struct hda_codec *codec;
1146 struct hda_pcm_stream *hinfo[2];
1149 static int azx_pcm_open(struct snd_pcm_substream *substream)
1151 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1152 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1153 struct azx *chip = apcm->chip;
1154 struct azx_dev *azx_dev;
1155 struct snd_pcm_runtime *runtime = substream->runtime;
1156 unsigned long flags;
1159 mutex_lock(&chip->open_mutex);
1160 azx_dev = azx_assign_device(chip, substream->stream);
1161 if (azx_dev == NULL) {
1162 mutex_unlock(&chip->open_mutex);
1165 runtime->hw = azx_pcm_hw;
1166 runtime->hw.channels_min = hinfo->channels_min;
1167 runtime->hw.channels_max = hinfo->channels_max;
1168 runtime->hw.formats = hinfo->formats;
1169 runtime->hw.rates = hinfo->rates;
1170 snd_pcm_limit_hw_rates(runtime);
1171 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1172 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1174 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1176 snd_hda_power_up(apcm->codec);
1177 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1179 azx_release_device(azx_dev);
1180 snd_hda_power_down(apcm->codec);
1181 mutex_unlock(&chip->open_mutex);
1184 spin_lock_irqsave(&chip->reg_lock, flags);
1185 azx_dev->substream = substream;
1186 azx_dev->running = 0;
1187 spin_unlock_irqrestore(&chip->reg_lock, flags);
1189 runtime->private_data = azx_dev;
1190 mutex_unlock(&chip->open_mutex);
1194 static int azx_pcm_close(struct snd_pcm_substream *substream)
1196 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1197 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1198 struct azx *chip = apcm->chip;
1199 struct azx_dev *azx_dev = get_azx_dev(substream);
1200 unsigned long flags;
1202 mutex_lock(&chip->open_mutex);
1203 spin_lock_irqsave(&chip->reg_lock, flags);
1204 azx_dev->substream = NULL;
1205 azx_dev->running = 0;
1206 spin_unlock_irqrestore(&chip->reg_lock, flags);
1207 azx_release_device(azx_dev);
1208 hinfo->ops.close(hinfo, apcm->codec, substream);
1209 snd_hda_power_down(apcm->codec);
1210 mutex_unlock(&chip->open_mutex);
1214 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1215 struct snd_pcm_hw_params *hw_params)
1217 return snd_pcm_lib_malloc_pages(substream,
1218 params_buffer_bytes(hw_params));
1221 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1223 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1224 struct azx_dev *azx_dev = get_azx_dev(substream);
1225 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1227 /* reset BDL address */
1228 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1229 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1230 azx_sd_writel(azx_dev, SD_CTL, 0);
1232 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1234 return snd_pcm_lib_free_pages(substream);
1237 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1239 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1240 struct azx *chip = apcm->chip;
1241 struct azx_dev *azx_dev = get_azx_dev(substream);
1242 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1243 struct snd_pcm_runtime *runtime = substream->runtime;
1245 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1246 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1247 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1248 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1252 if (!azx_dev->format_val) {
1253 snd_printk(KERN_ERR SFX
1254 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1255 runtime->rate, runtime->channels, runtime->format);
1259 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1261 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1262 azx_setup_periods(azx_dev);
1263 azx_setup_controller(chip, azx_dev);
1264 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1265 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1267 azx_dev->fifo_size = 0;
1269 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1270 azx_dev->format_val, substream);
1273 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1275 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1276 struct azx_dev *azx_dev = get_azx_dev(substream);
1277 struct azx *chip = apcm->chip;
1280 spin_lock(&chip->reg_lock);
1282 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1283 case SNDRV_PCM_TRIGGER_RESUME:
1284 case SNDRV_PCM_TRIGGER_START:
1285 azx_stream_start(chip, azx_dev);
1286 azx_dev->running = 1;
1288 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1289 case SNDRV_PCM_TRIGGER_SUSPEND:
1290 case SNDRV_PCM_TRIGGER_STOP:
1291 azx_stream_stop(chip, azx_dev);
1292 azx_dev->running = 0;
1297 spin_unlock(&chip->reg_lock);
1298 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1299 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1300 cmd == SNDRV_PCM_TRIGGER_STOP) {
1302 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1309 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1311 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1312 struct azx *chip = apcm->chip;
1313 struct azx_dev *azx_dev = get_azx_dev(substream);
1316 if (chip->position_fix == POS_FIX_POSBUF ||
1317 chip->position_fix == POS_FIX_AUTO) {
1318 /* use the position buffer */
1319 pos = le32_to_cpu(*azx_dev->posbuf);
1320 if (chip->position_fix == POS_FIX_AUTO &&
1321 azx_dev->period_intr == 1 && !pos) {
1323 "hda-intel: Invalid position buffer, "
1324 "using LPIB read method instead.\n");
1325 chip->position_fix = POS_FIX_NONE;
1331 pos = azx_sd_readl(azx_dev, SD_LPIB);
1332 if (chip->position_fix == POS_FIX_FIFO)
1333 pos += azx_dev->fifo_size;
1335 if (pos >= azx_dev->bufsize)
1337 return bytes_to_frames(substream->runtime, pos);
1340 static struct snd_pcm_ops azx_pcm_ops = {
1341 .open = azx_pcm_open,
1342 .close = azx_pcm_close,
1343 .ioctl = snd_pcm_lib_ioctl,
1344 .hw_params = azx_pcm_hw_params,
1345 .hw_free = azx_pcm_hw_free,
1346 .prepare = azx_pcm_prepare,
1347 .trigger = azx_pcm_trigger,
1348 .pointer = azx_pcm_pointer,
1351 static void azx_pcm_free(struct snd_pcm *pcm)
1353 kfree(pcm->private_data);
1356 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1357 struct hda_pcm *cpcm, int pcm_dev)
1360 struct snd_pcm *pcm;
1361 struct azx_pcm *apcm;
1363 /* if no substreams are defined for both playback and capture,
1364 * it's just a placeholder. ignore it.
1366 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1369 snd_assert(cpcm->name, return -EINVAL);
1371 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1372 cpcm->stream[0].substreams,
1373 cpcm->stream[1].substreams,
1377 strcpy(pcm->name, cpcm->name);
1378 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1382 apcm->codec = codec;
1383 apcm->hinfo[0] = &cpcm->stream[0];
1384 apcm->hinfo[1] = &cpcm->stream[1];
1385 pcm->private_data = apcm;
1386 pcm->private_free = azx_pcm_free;
1387 if (cpcm->stream[0].substreams)
1388 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1389 if (cpcm->stream[1].substreams)
1390 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1391 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1392 snd_dma_pci_data(chip->pci),
1393 1024 * 64, 1024 * 1024);
1394 chip->pcm[pcm_dev] = pcm;
1395 if (chip->pcm_devs < pcm_dev + 1)
1396 chip->pcm_devs = pcm_dev + 1;
1401 static int __devinit azx_pcm_create(struct azx *chip)
1403 struct hda_codec *codec;
1407 err = snd_hda_build_pcms(chip->bus);
1411 /* create audio PCMs */
1413 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1414 for (c = 0; c < codec->num_pcms; c++) {
1415 if (codec->pcm_info[c].is_modem)
1416 continue; /* create later */
1417 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1418 snd_printk(KERN_ERR SFX
1419 "Too many audio PCMs\n");
1422 err = create_codec_pcm(chip, codec,
1423 &codec->pcm_info[c], pcm_dev);
1430 /* create modem PCMs */
1431 pcm_dev = AZX_MAX_AUDIO_PCMS;
1432 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1433 for (c = 0; c < codec->num_pcms; c++) {
1434 if (!codec->pcm_info[c].is_modem)
1435 continue; /* already created */
1436 if (pcm_dev >= AZX_MAX_PCMS) {
1437 snd_printk(KERN_ERR SFX
1438 "Too many modem PCMs\n");
1441 err = create_codec_pcm(chip, codec,
1442 &codec->pcm_info[c], pcm_dev);
1445 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1453 * mixer creation - all stuff is implemented in hda module
1455 static int __devinit azx_mixer_create(struct azx *chip)
1457 return snd_hda_build_controls(chip->bus);
1462 * initialize SD streams
1464 static int __devinit azx_init_stream(struct azx *chip)
1468 /* initialize each stream (aka device)
1469 * assign the starting bdl address to each stream (device)
1472 for (i = 0; i < chip->num_streams; i++) {
1473 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1474 struct azx_dev *azx_dev = &chip->azx_dev[i];
1475 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1476 azx_dev->bdl_addr = chip->bdl.addr + off;
1477 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1478 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1479 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1480 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1481 azx_dev->sd_int_sta_mask = 1 << i;
1482 /* stream tag: must be non-zero and unique */
1484 azx_dev->stream_tag = i + 1;
1490 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1492 if (request_irq(chip->pci->irq, azx_interrupt,
1493 chip->msi ? 0 : IRQF_SHARED,
1494 "HDA Intel", chip)) {
1495 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1496 "disabling device\n", chip->pci->irq);
1498 snd_card_disconnect(chip->card);
1501 chip->irq = chip->pci->irq;
1502 pci_intx(chip->pci, !chip->msi);
1507 static void azx_stop_chip(struct azx *chip)
1509 if (!chip->initialized)
1512 /* disable interrupts */
1513 azx_int_disable(chip);
1514 azx_int_clear(chip);
1516 /* disable CORB/RIRB */
1517 azx_free_cmd_io(chip);
1519 /* disable position buffer */
1520 azx_writel(chip, DPLBASE, 0);
1521 azx_writel(chip, DPUBASE, 0);
1523 chip->initialized = 0;
1526 #ifdef CONFIG_SND_HDA_POWER_SAVE
1527 /* power-up/down the controller */
1528 static void azx_power_notify(struct hda_codec *codec)
1530 struct azx *chip = codec->bus->private_data;
1531 struct hda_codec *c;
1534 list_for_each_entry(c, &codec->bus->codec_list, list) {
1541 azx_init_chip(chip);
1542 else if (chip->running && power_save_controller)
1543 azx_stop_chip(chip);
1545 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1551 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1553 struct snd_card *card = pci_get_drvdata(pci);
1554 struct azx *chip = card->private_data;
1557 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1558 for (i = 0; i < chip->pcm_devs; i++)
1559 snd_pcm_suspend_all(chip->pcm[i]);
1560 if (chip->initialized)
1561 snd_hda_suspend(chip->bus, state);
1562 azx_stop_chip(chip);
1563 if (chip->irq >= 0) {
1564 synchronize_irq(chip->irq);
1565 free_irq(chip->irq, chip);
1569 pci_disable_msi(chip->pci);
1570 pci_disable_device(pci);
1571 pci_save_state(pci);
1572 pci_set_power_state(pci, pci_choose_state(pci, state));
1576 static int azx_resume(struct pci_dev *pci)
1578 struct snd_card *card = pci_get_drvdata(pci);
1579 struct azx *chip = card->private_data;
1581 pci_set_power_state(pci, PCI_D0);
1582 pci_restore_state(pci);
1583 if (pci_enable_device(pci) < 0) {
1584 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1585 "disabling device\n");
1586 snd_card_disconnect(card);
1589 pci_set_master(pci);
1591 if (pci_enable_msi(pci) < 0)
1593 if (azx_acquire_irq(chip, 1) < 0)
1597 if (snd_hda_codecs_inuse(chip->bus))
1598 azx_init_chip(chip);
1600 snd_hda_resume(chip->bus);
1601 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1604 #endif /* CONFIG_PM */
1610 static int azx_free(struct azx *chip)
1612 if (chip->initialized) {
1614 for (i = 0; i < chip->num_streams; i++)
1615 azx_stream_stop(chip, &chip->azx_dev[i]);
1616 azx_stop_chip(chip);
1619 if (chip->irq >= 0) {
1620 synchronize_irq(chip->irq);
1621 free_irq(chip->irq, (void*)chip);
1624 pci_disable_msi(chip->pci);
1625 if (chip->remap_addr)
1626 iounmap(chip->remap_addr);
1629 snd_dma_free_pages(&chip->bdl);
1631 snd_dma_free_pages(&chip->rb);
1632 if (chip->posbuf.area)
1633 snd_dma_free_pages(&chip->posbuf);
1634 pci_release_regions(chip->pci);
1635 pci_disable_device(chip->pci);
1636 kfree(chip->azx_dev);
1642 static int azx_dev_free(struct snd_device *device)
1644 return azx_free(device->device_data);
1648 * white/black-listing for position_fix
1650 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1651 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1652 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1656 static int __devinit check_position_fix(struct azx *chip, int fix)
1658 const struct snd_pci_quirk *q;
1660 if (fix == POS_FIX_AUTO) {
1661 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1664 "hda_intel: position_fix set to %d "
1665 "for device %04x:%04x\n",
1666 q->value, q->subvendor, q->subdevice);
1674 * black-lists for probe_mask
1676 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1677 /* Thinkpad often breaks the controller communication when accessing
1678 * to the non-working (or non-existing) modem codec slot.
1680 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1681 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1682 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1686 static void __devinit check_probe_mask(struct azx *chip)
1688 const struct snd_pci_quirk *q;
1690 if (probe_mask == -1) {
1691 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1694 "hda_intel: probe_mask set to 0x%x "
1695 "for device %04x:%04x\n",
1696 q->value, q->subvendor, q->subdevice);
1697 probe_mask = q->value;
1706 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1712 static struct snd_device_ops ops = {
1713 .dev_free = azx_dev_free,
1718 err = pci_enable_device(pci);
1722 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1724 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1725 pci_disable_device(pci);
1729 spin_lock_init(&chip->reg_lock);
1730 mutex_init(&chip->open_mutex);
1734 chip->driver_type = driver_type;
1735 chip->msi = enable_msi;
1737 chip->position_fix = check_position_fix(chip, position_fix);
1738 check_probe_mask(chip);
1740 chip->single_cmd = single_cmd;
1742 #if BITS_PER_LONG != 64
1743 /* Fix up base address on ULI M5461 */
1744 if (chip->driver_type == AZX_DRIVER_ULI) {
1746 pci_read_config_word(pci, 0x40, &tmp3);
1747 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1748 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1752 err = pci_request_regions(pci, "ICH HD audio");
1755 pci_disable_device(pci);
1759 chip->addr = pci_resource_start(pci, 0);
1760 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1761 if (chip->remap_addr == NULL) {
1762 snd_printk(KERN_ERR SFX "ioremap error\n");
1768 if (pci_enable_msi(pci) < 0)
1771 if (azx_acquire_irq(chip, 0) < 0) {
1776 pci_set_master(pci);
1777 synchronize_irq(chip->irq);
1779 switch (chip->driver_type) {
1780 case AZX_DRIVER_ULI:
1781 chip->playback_streams = ULI_NUM_PLAYBACK;
1782 chip->capture_streams = ULI_NUM_CAPTURE;
1783 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1784 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1786 case AZX_DRIVER_ATIHDMI:
1787 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1788 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1789 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1790 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1793 chip->playback_streams = ICH6_NUM_PLAYBACK;
1794 chip->capture_streams = ICH6_NUM_CAPTURE;
1795 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1796 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1799 chip->num_streams = chip->playback_streams + chip->capture_streams;
1800 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1802 if (!chip->azx_dev) {
1803 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1807 /* allocate memory for the BDL for each stream */
1808 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1809 snd_dma_pci_data(chip->pci),
1810 BDL_SIZE, &chip->bdl);
1812 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1815 /* allocate memory for the position buffer */
1816 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1817 snd_dma_pci_data(chip->pci),
1818 chip->num_streams * 8, &chip->posbuf);
1820 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1823 /* allocate CORB/RIRB */
1824 if (!chip->single_cmd) {
1825 err = azx_alloc_cmd_io(chip);
1830 /* initialize streams */
1831 azx_init_stream(chip);
1833 /* initialize chip */
1835 azx_init_chip(chip);
1837 /* codec detection */
1838 if (!chip->codec_mask) {
1839 snd_printk(KERN_ERR SFX "no codecs found!\n");
1844 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1846 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1850 strcpy(card->driver, "HDA-Intel");
1851 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1852 sprintf(card->longname, "%s at 0x%lx irq %i",
1853 card->shortname, chip->addr, chip->irq);
1863 static void power_down_all_codecs(struct azx *chip)
1865 #ifdef CONFIG_SND_HDA_POWER_SAVE
1866 /* The codecs were powered up in snd_hda_codec_new().
1867 * Now all initialization done, so turn them down if possible
1869 struct hda_codec *codec;
1870 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1871 snd_hda_power_down(codec);
1876 static int __devinit azx_probe(struct pci_dev *pci,
1877 const struct pci_device_id *pci_id)
1879 struct snd_card *card;
1883 card = snd_card_new(index, id, THIS_MODULE, 0);
1885 snd_printk(KERN_ERR SFX "Error creating card!\n");
1889 err = azx_create(card, pci, pci_id->driver_data, &chip);
1891 snd_card_free(card);
1894 card->private_data = chip;
1896 /* create codec instances */
1897 err = azx_codec_create(chip, model);
1899 snd_card_free(card);
1903 /* create PCM streams */
1904 err = azx_pcm_create(chip);
1906 snd_card_free(card);
1910 /* create mixer controls */
1911 err = azx_mixer_create(chip);
1913 snd_card_free(card);
1917 snd_card_set_dev(card, &pci->dev);
1919 err = snd_card_register(card);
1921 snd_card_free(card);
1925 pci_set_drvdata(pci, card);
1927 power_down_all_codecs(chip);
1932 static void __devexit azx_remove(struct pci_dev *pci)
1934 snd_card_free(pci_get_drvdata(pci));
1935 pci_set_drvdata(pci, NULL);
1939 static struct pci_device_id azx_ids[] = {
1940 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1941 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1942 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1943 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1944 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1945 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1946 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1947 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1948 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1949 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1950 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1951 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1952 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
1953 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
1954 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
1955 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
1956 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
1957 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
1958 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1959 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1960 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1961 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1962 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1963 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1964 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1965 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1966 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1967 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1968 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1969 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1970 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1971 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1972 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1973 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1974 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1975 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
1976 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
1977 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
1978 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
1981 MODULE_DEVICE_TABLE(pci, azx_ids);
1983 /* pci_driver definition */
1984 static struct pci_driver driver = {
1985 .name = "HDA Intel",
1986 .id_table = azx_ids,
1988 .remove = __devexit_p(azx_remove),
1990 .suspend = azx_suspend,
1991 .resume = azx_resume,
1995 static int __init alsa_card_azx_init(void)
1997 return pci_register_driver(&driver);
2000 static void __exit alsa_card_azx_exit(void)
2002 pci_unregister_driver(&driver);
2005 module_init(alsa_card_azx_init)
2006 module_exit(alsa_card_azx_exit)