3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55 static char *model[SNDRV_CARDS];
56 static int position_fix[SNDRV_CARDS];
57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
58 static int single_cmd;
59 static int enable_msi;
61 module_param_array(index, int, NULL, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param_array(enable, bool, NULL, 0444);
66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
67 module_param_array(model, charp, NULL, 0444);
68 MODULE_PARM_DESC(model, "Use the given board model.");
69 module_param_array(position_fix, int, NULL, 0444);
70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask, int, NULL, 0444);
73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd, bool, 0444);
75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi, int, 0444);
78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
87 static int power_save_controller = 1;
88 module_param(power_save_controller, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
116 MODULE_DESCRIPTION("Intel HDA driver");
118 #define SFX "hda-intel: "
124 #define ICH6_REG_GCAP 0x00
125 #define ICH6_REG_VMIN 0x02
126 #define ICH6_REG_VMAJ 0x03
127 #define ICH6_REG_OUTPAY 0x04
128 #define ICH6_REG_INPAY 0x06
129 #define ICH6_REG_GCTL 0x08
130 #define ICH6_REG_WAKEEN 0x0c
131 #define ICH6_REG_STATESTS 0x0e
132 #define ICH6_REG_GSTS 0x10
133 #define ICH6_REG_INTCTL 0x20
134 #define ICH6_REG_INTSTS 0x24
135 #define ICH6_REG_WALCLK 0x30
136 #define ICH6_REG_SYNC 0x34
137 #define ICH6_REG_CORBLBASE 0x40
138 #define ICH6_REG_CORBUBASE 0x44
139 #define ICH6_REG_CORBWP 0x48
140 #define ICH6_REG_CORBRP 0x4A
141 #define ICH6_REG_CORBCTL 0x4c
142 #define ICH6_REG_CORBSTS 0x4d
143 #define ICH6_REG_CORBSIZE 0x4e
145 #define ICH6_REG_RIRBLBASE 0x50
146 #define ICH6_REG_RIRBUBASE 0x54
147 #define ICH6_REG_RIRBWP 0x58
148 #define ICH6_REG_RINTCNT 0x5a
149 #define ICH6_REG_RIRBCTL 0x5c
150 #define ICH6_REG_RIRBSTS 0x5d
151 #define ICH6_REG_RIRBSIZE 0x5e
153 #define ICH6_REG_IC 0x60
154 #define ICH6_REG_IR 0x64
155 #define ICH6_REG_IRS 0x68
156 #define ICH6_IRS_VALID (1<<1)
157 #define ICH6_IRS_BUSY (1<<0)
159 #define ICH6_REG_DPLBASE 0x70
160 #define ICH6_REG_DPUBASE 0x74
161 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
163 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
164 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
166 /* stream register offsets from stream base */
167 #define ICH6_REG_SD_CTL 0x00
168 #define ICH6_REG_SD_STS 0x03
169 #define ICH6_REG_SD_LPIB 0x04
170 #define ICH6_REG_SD_CBL 0x08
171 #define ICH6_REG_SD_LVI 0x0c
172 #define ICH6_REG_SD_FIFOW 0x0e
173 #define ICH6_REG_SD_FIFOSIZE 0x10
174 #define ICH6_REG_SD_FORMAT 0x12
175 #define ICH6_REG_SD_BDLPL 0x18
176 #define ICH6_REG_SD_BDLPU 0x1c
179 #define ICH6_PCIREG_TCSEL 0x44
185 /* max number of SDs */
186 /* ICH, ATI and VIA have 4 playback and 4 capture */
187 #define ICH6_CAPTURE_INDEX 0
188 #define ICH6_NUM_CAPTURE 4
189 #define ICH6_PLAYBACK_INDEX 4
190 #define ICH6_NUM_PLAYBACK 4
192 /* ULI has 6 playback and 5 capture */
193 #define ULI_CAPTURE_INDEX 0
194 #define ULI_NUM_CAPTURE 5
195 #define ULI_PLAYBACK_INDEX 5
196 #define ULI_NUM_PLAYBACK 6
198 /* ATI HDMI has 1 playback and 0 capture */
199 #define ATIHDMI_CAPTURE_INDEX 0
200 #define ATIHDMI_NUM_CAPTURE 0
201 #define ATIHDMI_PLAYBACK_INDEX 0
202 #define ATIHDMI_NUM_PLAYBACK 1
204 /* this number is statically defined for simplicity */
205 #define MAX_AZX_DEV 16
207 /* max number of fragments - we may use more if allocating more pages for BDL */
208 #define BDL_SIZE PAGE_ALIGN(8192)
209 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
210 /* max buffer size - no h/w limit, you can increase as you like */
211 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
212 /* max number of PCM devics per card */
213 #define AZX_MAX_AUDIO_PCMS 6
214 #define AZX_MAX_MODEM_PCMS 2
215 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
217 /* RIRB int mask: overrun[2], response[0] */
218 #define RIRB_INT_RESPONSE 0x01
219 #define RIRB_INT_OVERRUN 0x04
220 #define RIRB_INT_MASK 0x05
222 /* STATESTS int mask: SD2,SD1,SD0 */
223 #define AZX_MAX_CODECS 3
224 #define STATESTS_INT_MASK 0x07
227 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
228 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
229 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
230 #define SD_CTL_STREAM_TAG_SHIFT 20
232 /* SD_CTL and SD_STS */
233 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
234 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
235 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
236 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
240 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
242 /* INTCTL and INTSTS */
243 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
244 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
245 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
247 /* GCTL unsolicited response enable bit */
248 #define ICH6_GCTL_UREN (1<<8)
251 #define ICH6_GCTL_RESET (1<<0)
253 /* CORB/RIRB control, read/write pointer */
254 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
255 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
256 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
257 /* below are so far hardcoded - should read registers in future */
258 #define ICH6_MAX_CORB_ENTRIES 256
259 #define ICH6_MAX_RIRB_ENTRIES 256
261 /* position fix mode */
269 /* Defines for ATI HD Audio support in SB450 south bridge */
270 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
271 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
273 /* Defines for Nvidia HDA support */
274 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
275 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
281 u32 *bdl; /* virtual address of the BDL */
282 dma_addr_t bdl_addr; /* physical address of the BDL */
283 u32 *posbuf; /* position buffer pointer */
285 unsigned int bufsize; /* size of the play buffer in bytes */
286 unsigned int fragsize; /* size of each period in bytes */
287 unsigned int frags; /* number for period in the play buffer */
288 unsigned int fifo_size; /* FIFO size */
290 void __iomem *sd_addr; /* stream descriptor pointer */
292 u32 sd_int_sta_mask; /* stream int status mask */
295 struct snd_pcm_substream *substream; /* assigned substream,
298 unsigned int format_val; /* format value to be set in the
299 * controller and the codec
301 unsigned char stream_tag; /* assigned stream */
302 unsigned char index; /* stream index */
303 /* for sanity check of position buffer */
304 unsigned int period_intr;
306 unsigned int opened :1;
307 unsigned int running :1;
312 u32 *buf; /* CORB/RIRB buffer
313 * Each CORB entry is 4byte, RIRB is 8byte
315 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
317 unsigned short rp, wp; /* read/write pointers */
318 int cmds; /* number of pending requests */
319 u32 res; /* last read value */
323 struct snd_card *card;
326 /* chip type specific */
328 int playback_streams;
329 int playback_index_offset;
331 int capture_index_offset;
336 void __iomem *remap_addr;
341 struct mutex open_mutex;
343 /* streams (x num_streams) */
344 struct azx_dev *azx_dev;
347 unsigned int pcm_devs;
348 struct snd_pcm *pcm[AZX_MAX_PCMS];
351 unsigned short codec_mask;
358 /* BDL, CORB/RIRB and position buffers */
359 struct snd_dma_buffer bdl;
360 struct snd_dma_buffer rb;
361 struct snd_dma_buffer posbuf;
365 unsigned int running :1;
366 unsigned int initialized :1;
367 unsigned int single_cmd :1;
368 unsigned int polling_mode :1;
372 unsigned int last_cmd; /* last issued command (to sync) */
386 static char *driver_short_names[] __devinitdata = {
387 [AZX_DRIVER_ICH] = "HDA Intel",
388 [AZX_DRIVER_ATI] = "HDA ATI SB",
389 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
390 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
391 [AZX_DRIVER_SIS] = "HDA SIS966",
392 [AZX_DRIVER_ULI] = "HDA ULI M5461",
393 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
397 * macros for easy use
399 #define azx_writel(chip,reg,value) \
400 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
401 #define azx_readl(chip,reg) \
402 readl((chip)->remap_addr + ICH6_REG_##reg)
403 #define azx_writew(chip,reg,value) \
404 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
405 #define azx_readw(chip,reg) \
406 readw((chip)->remap_addr + ICH6_REG_##reg)
407 #define azx_writeb(chip,reg,value) \
408 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
409 #define azx_readb(chip,reg) \
410 readb((chip)->remap_addr + ICH6_REG_##reg)
412 #define azx_sd_writel(dev,reg,value) \
413 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
414 #define azx_sd_readl(dev,reg) \
415 readl((dev)->sd_addr + ICH6_REG_##reg)
416 #define azx_sd_writew(dev,reg,value) \
417 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
418 #define azx_sd_readw(dev,reg) \
419 readw((dev)->sd_addr + ICH6_REG_##reg)
420 #define azx_sd_writeb(dev,reg,value) \
421 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
422 #define azx_sd_readb(dev,reg) \
423 readb((dev)->sd_addr + ICH6_REG_##reg)
425 /* for pcm support */
426 #define get_azx_dev(substream) (substream->runtime->private_data)
428 /* Get the upper 32bit of the given dma_addr_t
429 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
431 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
433 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
436 * Interface for HD codec
440 * CORB / RIRB interface
442 static int azx_alloc_cmd_io(struct azx *chip)
446 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
447 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
448 snd_dma_pci_data(chip->pci),
449 PAGE_SIZE, &chip->rb);
451 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
457 static void azx_init_cmd_io(struct azx *chip)
460 chip->corb.addr = chip->rb.addr;
461 chip->corb.buf = (u32 *)chip->rb.area;
462 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
463 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
465 /* set the corb size to 256 entries (ULI requires explicitly) */
466 azx_writeb(chip, CORBSIZE, 0x02);
467 /* set the corb write pointer to 0 */
468 azx_writew(chip, CORBWP, 0);
469 /* reset the corb hw read pointer */
470 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
471 /* enable corb dma */
472 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
475 chip->rirb.addr = chip->rb.addr + 2048;
476 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
477 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
478 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
480 /* set the rirb size to 256 entries (ULI requires explicitly) */
481 azx_writeb(chip, RIRBSIZE, 0x02);
482 /* reset the rirb hw write pointer */
483 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
484 /* set N=1, get RIRB response interrupt for new entry */
485 azx_writew(chip, RINTCNT, 1);
486 /* enable rirb dma and response irq */
487 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
488 chip->rirb.rp = chip->rirb.cmds = 0;
491 static void azx_free_cmd_io(struct azx *chip)
493 /* disable ringbuffer DMAs */
494 azx_writeb(chip, RIRBCTL, 0);
495 azx_writeb(chip, CORBCTL, 0);
499 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
501 struct azx *chip = codec->bus->private_data;
504 /* add command to corb */
505 wp = azx_readb(chip, CORBWP);
507 wp %= ICH6_MAX_CORB_ENTRIES;
509 spin_lock_irq(&chip->reg_lock);
511 chip->corb.buf[wp] = cpu_to_le32(val);
512 azx_writel(chip, CORBWP, wp);
513 spin_unlock_irq(&chip->reg_lock);
518 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
520 /* retrieve RIRB entry - called from interrupt handler */
521 static void azx_update_rirb(struct azx *chip)
526 wp = azx_readb(chip, RIRBWP);
527 if (wp == chip->rirb.wp)
531 while (chip->rirb.rp != wp) {
533 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
535 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
536 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
537 res = le32_to_cpu(chip->rirb.buf[rp]);
538 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
539 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
540 else if (chip->rirb.cmds) {
542 chip->rirb.res = res;
547 /* receive a response */
548 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
550 struct azx *chip = codec->bus->private_data;
551 unsigned long timeout;
554 timeout = jiffies + msecs_to_jiffies(1000);
556 if (chip->polling_mode) {
557 spin_lock_irq(&chip->reg_lock);
558 azx_update_rirb(chip);
559 spin_unlock_irq(&chip->reg_lock);
561 if (!chip->rirb.cmds)
562 return chip->rirb.res; /* the last value */
563 if (time_after(jiffies, timeout))
565 if (codec->bus->needs_damn_long_delay)
566 msleep(2); /* temporary workaround */
574 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
575 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
576 free_irq(chip->irq, chip);
578 pci_disable_msi(chip->pci);
580 if (azx_acquire_irq(chip, 1) < 0)
585 if (!chip->polling_mode) {
586 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
587 "switching to polling mode: last cmd=0x%08x\n",
589 chip->polling_mode = 1;
593 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
594 "switching to single_cmd mode: last cmd=0x%08x\n",
596 chip->rirb.rp = azx_readb(chip, RIRBWP);
598 /* switch to single_cmd mode */
599 chip->single_cmd = 1;
600 azx_free_cmd_io(chip);
605 * Use the single immediate command instead of CORB/RIRB for simplicity
607 * Note: according to Intel, this is not preferred use. The command was
608 * intended for the BIOS only, and may get confused with unsolicited
609 * responses. So, we shouldn't use it for normal operation from the
611 * I left the codes, however, for debugging/testing purposes.
615 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
617 struct azx *chip = codec->bus->private_data;
621 /* check ICB busy bit */
622 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
623 /* Clear IRV valid bit */
624 azx_writew(chip, IRS, azx_readw(chip, IRS) |
626 azx_writel(chip, IC, val);
627 azx_writew(chip, IRS, azx_readw(chip, IRS) |
633 if (printk_ratelimit())
634 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
635 azx_readw(chip, IRS), val);
639 /* receive a response */
640 static unsigned int azx_single_get_response(struct hda_codec *codec)
642 struct azx *chip = codec->bus->private_data;
646 /* check IRV busy bit */
647 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
648 return azx_readl(chip, IR);
651 if (printk_ratelimit())
652 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
653 azx_readw(chip, IRS));
654 return (unsigned int)-1;
658 * The below are the main callbacks from hda_codec.
660 * They are just the skeleton to call sub-callbacks according to the
661 * current setting of chip->single_cmd.
665 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
666 int direct, unsigned int verb,
669 struct azx *chip = codec->bus->private_data;
672 val = (u32)(codec->addr & 0x0f) << 28;
673 val |= (u32)direct << 27;
674 val |= (u32)nid << 20;
677 chip->last_cmd = val;
679 if (chip->single_cmd)
680 return azx_single_send_cmd(codec, val);
682 return azx_corb_send_cmd(codec, val);
686 static unsigned int azx_get_response(struct hda_codec *codec)
688 struct azx *chip = codec->bus->private_data;
689 if (chip->single_cmd)
690 return azx_single_get_response(codec);
692 return azx_rirb_get_response(codec);
695 #ifdef CONFIG_SND_HDA_POWER_SAVE
696 static void azx_power_notify(struct hda_codec *codec);
699 /* reset codec link */
700 static int azx_reset(struct azx *chip)
705 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
707 /* reset controller */
708 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
711 while (azx_readb(chip, GCTL) && --count)
714 /* delay for >= 100us for codec PLL to settle per spec
715 * Rev 0.9 section 5.5.1
719 /* Bring controller out of reset */
720 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
723 while (!azx_readb(chip, GCTL) && --count)
726 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
729 /* check to see if controller is ready */
730 if (!azx_readb(chip, GCTL)) {
731 snd_printd("azx_reset: controller not ready!\n");
735 /* Accept unsolicited responses */
736 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
739 if (!chip->codec_mask) {
740 chip->codec_mask = azx_readw(chip, STATESTS);
741 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
752 /* enable interrupts */
753 static void azx_int_enable(struct azx *chip)
755 /* enable controller CIE and GIE */
756 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
757 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
760 /* disable interrupts */
761 static void azx_int_disable(struct azx *chip)
765 /* disable interrupts in stream descriptor */
766 for (i = 0; i < chip->num_streams; i++) {
767 struct azx_dev *azx_dev = &chip->azx_dev[i];
768 azx_sd_writeb(azx_dev, SD_CTL,
769 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
772 /* disable SIE for all streams */
773 azx_writeb(chip, INTCTL, 0);
775 /* disable controller CIE and GIE */
776 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
777 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
780 /* clear interrupts */
781 static void azx_int_clear(struct azx *chip)
785 /* clear stream status */
786 for (i = 0; i < chip->num_streams; i++) {
787 struct azx_dev *azx_dev = &chip->azx_dev[i];
788 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
792 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
794 /* clear rirb status */
795 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
797 /* clear int status */
798 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
802 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
805 azx_writeb(chip, INTCTL,
806 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
807 /* set DMA start and interrupt mask */
808 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
809 SD_CTL_DMA_START | SD_INT_MASK);
813 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
816 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
817 ~(SD_CTL_DMA_START | SD_INT_MASK));
818 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
820 azx_writeb(chip, INTCTL,
821 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
826 * reset and start the controller registers
828 static void azx_init_chip(struct azx *chip)
830 if (chip->initialized)
833 /* reset controller */
836 /* initialize interrupts */
838 azx_int_enable(chip);
840 /* initialize the codec command I/O */
841 if (!chip->single_cmd)
842 azx_init_cmd_io(chip);
844 /* program the position buffer */
845 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
846 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
848 chip->initialized = 1;
852 * initialize the PCI registers
854 /* update bits in a PCI register byte */
855 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
856 unsigned char mask, unsigned char val)
860 pci_read_config_byte(pci, reg, &data);
862 data |= (val & mask);
863 pci_write_config_byte(pci, reg, data);
866 static void azx_init_pci(struct azx *chip)
868 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
869 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
870 * Ensuring these bits are 0 clears playback static on some HD Audio
873 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
875 switch (chip->driver_type) {
877 /* For ATI SB450 azalia HD audio, we need to enable snoop */
878 update_pci_byte(chip->pci,
879 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
880 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
882 case AZX_DRIVER_NVIDIA:
883 /* For NVIDIA HDA, enable snoop */
884 update_pci_byte(chip->pci,
885 NVIDIA_HDA_TRANSREG_ADDR,
886 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
895 static irqreturn_t azx_interrupt(int irq, void *dev_id)
897 struct azx *chip = dev_id;
898 struct azx_dev *azx_dev;
902 spin_lock(&chip->reg_lock);
904 status = azx_readl(chip, INTSTS);
906 spin_unlock(&chip->reg_lock);
910 for (i = 0; i < chip->num_streams; i++) {
911 azx_dev = &chip->azx_dev[i];
912 if (status & azx_dev->sd_int_sta_mask) {
913 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
914 if (azx_dev->substream && azx_dev->running) {
915 azx_dev->period_intr++;
916 spin_unlock(&chip->reg_lock);
917 snd_pcm_period_elapsed(azx_dev->substream);
918 spin_lock(&chip->reg_lock);
924 status = azx_readb(chip, RIRBSTS);
925 if (status & RIRB_INT_MASK) {
926 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
927 azx_update_rirb(chip);
928 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
932 /* clear state status int */
933 if (azx_readb(chip, STATESTS) & 0x04)
934 azx_writeb(chip, STATESTS, 0x04);
936 spin_unlock(&chip->reg_lock);
945 static void azx_setup_periods(struct azx_dev *azx_dev)
947 u32 *bdl = azx_dev->bdl;
948 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
951 /* reset BDL address */
952 azx_sd_writel(azx_dev, SD_BDLPL, 0);
953 azx_sd_writel(azx_dev, SD_BDLPU, 0);
955 /* program the initial BDL entries */
956 for (idx = 0; idx < azx_dev->frags; idx++) {
957 unsigned int off = idx << 2; /* 4 dword step */
958 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
959 /* program the address field of the BDL entry */
960 bdl[off] = cpu_to_le32((u32)addr);
961 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
963 /* program the size field of the BDL entry */
964 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
966 /* program the IOC to enable interrupt when buffer completes */
967 bdl[off+3] = cpu_to_le32(0x01);
972 * set up the SD for streaming
974 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
979 /* make sure the run bit is zero for SD */
980 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
983 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
984 SD_CTL_STREAM_RESET);
987 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
990 val &= ~SD_CTL_STREAM_RESET;
991 azx_sd_writeb(azx_dev, SD_CTL, val);
995 /* waiting for hardware to report that the stream is out of reset */
996 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1000 /* program the stream_tag */
1001 azx_sd_writel(azx_dev, SD_CTL,
1002 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1003 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1005 /* program the length of samples in cyclic buffer */
1006 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1008 /* program the stream format */
1009 /* this value needs to be the same as the one programmed */
1010 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1012 /* program the stream LVI (last valid index) of the BDL */
1013 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1015 /* program the BDL address */
1016 /* lower BDL address */
1017 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1018 /* upper BDL address */
1019 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1021 /* enable the position buffer */
1022 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1023 azx_writel(chip, DPLBASE,
1024 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1026 /* set the interrupt enable bits in the descriptor control register */
1027 azx_sd_writel(azx_dev, SD_CTL,
1028 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1035 * Codec initialization
1038 static unsigned int azx_max_codecs[] __devinitdata = {
1039 [AZX_DRIVER_ICH] = 3,
1040 [AZX_DRIVER_ATI] = 4,
1041 [AZX_DRIVER_ATIHDMI] = 4,
1042 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1043 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1044 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1045 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1048 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1049 unsigned int codec_probe_mask)
1051 struct hda_bus_template bus_temp;
1052 int c, codecs, audio_codecs, err;
1054 memset(&bus_temp, 0, sizeof(bus_temp));
1055 bus_temp.private_data = chip;
1056 bus_temp.modelname = model;
1057 bus_temp.pci = chip->pci;
1058 bus_temp.ops.command = azx_send_cmd;
1059 bus_temp.ops.get_response = azx_get_response;
1060 #ifdef CONFIG_SND_HDA_POWER_SAVE
1061 bus_temp.ops.pm_notify = azx_power_notify;
1064 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1068 codecs = audio_codecs = 0;
1069 for (c = 0; c < AZX_MAX_CODECS; c++) {
1070 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1071 struct hda_codec *codec;
1072 err = snd_hda_codec_new(chip->bus, c, &codec);
1080 if (!audio_codecs) {
1081 /* probe additional slots if no codec is found */
1082 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1083 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1084 err = snd_hda_codec_new(chip->bus, c, NULL);
1092 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1104 /* assign a stream for the PCM */
1105 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1108 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1109 dev = chip->playback_index_offset;
1110 nums = chip->playback_streams;
1112 dev = chip->capture_index_offset;
1113 nums = chip->capture_streams;
1115 for (i = 0; i < nums; i++, dev++)
1116 if (!chip->azx_dev[dev].opened) {
1117 chip->azx_dev[dev].opened = 1;
1118 return &chip->azx_dev[dev];
1123 /* release the assigned stream */
1124 static inline void azx_release_device(struct azx_dev *azx_dev)
1126 azx_dev->opened = 0;
1129 static struct snd_pcm_hardware azx_pcm_hw = {
1130 .info = (SNDRV_PCM_INFO_MMAP |
1131 SNDRV_PCM_INFO_INTERLEAVED |
1132 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1133 SNDRV_PCM_INFO_MMAP_VALID |
1134 /* No full-resume yet implemented */
1135 /* SNDRV_PCM_INFO_RESUME |*/
1136 SNDRV_PCM_INFO_PAUSE),
1137 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1138 .rates = SNDRV_PCM_RATE_48000,
1143 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1144 .period_bytes_min = 128,
1145 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1147 .periods_max = AZX_MAX_FRAG,
1153 struct hda_codec *codec;
1154 struct hda_pcm_stream *hinfo[2];
1157 static int azx_pcm_open(struct snd_pcm_substream *substream)
1159 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1160 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1161 struct azx *chip = apcm->chip;
1162 struct azx_dev *azx_dev;
1163 struct snd_pcm_runtime *runtime = substream->runtime;
1164 unsigned long flags;
1167 mutex_lock(&chip->open_mutex);
1168 azx_dev = azx_assign_device(chip, substream->stream);
1169 if (azx_dev == NULL) {
1170 mutex_unlock(&chip->open_mutex);
1173 runtime->hw = azx_pcm_hw;
1174 runtime->hw.channels_min = hinfo->channels_min;
1175 runtime->hw.channels_max = hinfo->channels_max;
1176 runtime->hw.formats = hinfo->formats;
1177 runtime->hw.rates = hinfo->rates;
1178 snd_pcm_limit_hw_rates(runtime);
1179 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1180 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1182 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1184 snd_hda_power_up(apcm->codec);
1185 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1187 azx_release_device(azx_dev);
1188 snd_hda_power_down(apcm->codec);
1189 mutex_unlock(&chip->open_mutex);
1192 spin_lock_irqsave(&chip->reg_lock, flags);
1193 azx_dev->substream = substream;
1194 azx_dev->running = 0;
1195 spin_unlock_irqrestore(&chip->reg_lock, flags);
1197 runtime->private_data = azx_dev;
1198 mutex_unlock(&chip->open_mutex);
1202 static int azx_pcm_close(struct snd_pcm_substream *substream)
1204 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1205 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1206 struct azx *chip = apcm->chip;
1207 struct azx_dev *azx_dev = get_azx_dev(substream);
1208 unsigned long flags;
1210 mutex_lock(&chip->open_mutex);
1211 spin_lock_irqsave(&chip->reg_lock, flags);
1212 azx_dev->substream = NULL;
1213 azx_dev->running = 0;
1214 spin_unlock_irqrestore(&chip->reg_lock, flags);
1215 azx_release_device(azx_dev);
1216 hinfo->ops.close(hinfo, apcm->codec, substream);
1217 snd_hda_power_down(apcm->codec);
1218 mutex_unlock(&chip->open_mutex);
1222 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1223 struct snd_pcm_hw_params *hw_params)
1225 return snd_pcm_lib_malloc_pages(substream,
1226 params_buffer_bytes(hw_params));
1229 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1231 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1232 struct azx_dev *azx_dev = get_azx_dev(substream);
1233 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1235 /* reset BDL address */
1236 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1237 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1238 azx_sd_writel(azx_dev, SD_CTL, 0);
1240 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1242 return snd_pcm_lib_free_pages(substream);
1245 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1247 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1248 struct azx *chip = apcm->chip;
1249 struct azx_dev *azx_dev = get_azx_dev(substream);
1250 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1251 struct snd_pcm_runtime *runtime = substream->runtime;
1253 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1254 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1255 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1256 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1260 if (!azx_dev->format_val) {
1261 snd_printk(KERN_ERR SFX
1262 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1263 runtime->rate, runtime->channels, runtime->format);
1267 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1269 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1270 azx_setup_periods(azx_dev);
1271 azx_setup_controller(chip, azx_dev);
1272 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1273 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1275 azx_dev->fifo_size = 0;
1277 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1278 azx_dev->format_val, substream);
1281 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1283 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1284 struct azx_dev *azx_dev = get_azx_dev(substream);
1285 struct azx *chip = apcm->chip;
1288 spin_lock(&chip->reg_lock);
1290 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1291 case SNDRV_PCM_TRIGGER_RESUME:
1292 case SNDRV_PCM_TRIGGER_START:
1293 azx_stream_start(chip, azx_dev);
1294 azx_dev->running = 1;
1296 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1297 case SNDRV_PCM_TRIGGER_SUSPEND:
1298 case SNDRV_PCM_TRIGGER_STOP:
1299 azx_stream_stop(chip, azx_dev);
1300 azx_dev->running = 0;
1305 spin_unlock(&chip->reg_lock);
1306 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1307 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1308 cmd == SNDRV_PCM_TRIGGER_STOP) {
1310 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1317 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1319 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1320 struct azx *chip = apcm->chip;
1321 struct azx_dev *azx_dev = get_azx_dev(substream);
1324 if (chip->position_fix == POS_FIX_POSBUF ||
1325 chip->position_fix == POS_FIX_AUTO) {
1326 /* use the position buffer */
1327 pos = le32_to_cpu(*azx_dev->posbuf);
1328 if (chip->position_fix == POS_FIX_AUTO &&
1329 azx_dev->period_intr == 1 && !pos) {
1331 "hda-intel: Invalid position buffer, "
1332 "using LPIB read method instead.\n");
1333 chip->position_fix = POS_FIX_NONE;
1339 pos = azx_sd_readl(azx_dev, SD_LPIB);
1340 if (chip->position_fix == POS_FIX_FIFO)
1341 pos += azx_dev->fifo_size;
1343 if (pos >= azx_dev->bufsize)
1345 return bytes_to_frames(substream->runtime, pos);
1348 static struct snd_pcm_ops azx_pcm_ops = {
1349 .open = azx_pcm_open,
1350 .close = azx_pcm_close,
1351 .ioctl = snd_pcm_lib_ioctl,
1352 .hw_params = azx_pcm_hw_params,
1353 .hw_free = azx_pcm_hw_free,
1354 .prepare = azx_pcm_prepare,
1355 .trigger = azx_pcm_trigger,
1356 .pointer = azx_pcm_pointer,
1359 static void azx_pcm_free(struct snd_pcm *pcm)
1361 kfree(pcm->private_data);
1364 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1365 struct hda_pcm *cpcm, int pcm_dev)
1368 struct snd_pcm *pcm;
1369 struct azx_pcm *apcm;
1371 /* if no substreams are defined for both playback and capture,
1372 * it's just a placeholder. ignore it.
1374 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1377 snd_assert(cpcm->name, return -EINVAL);
1379 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1380 cpcm->stream[0].substreams,
1381 cpcm->stream[1].substreams,
1385 strcpy(pcm->name, cpcm->name);
1386 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1390 apcm->codec = codec;
1391 apcm->hinfo[0] = &cpcm->stream[0];
1392 apcm->hinfo[1] = &cpcm->stream[1];
1393 pcm->private_data = apcm;
1394 pcm->private_free = azx_pcm_free;
1395 if (cpcm->stream[0].substreams)
1396 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1397 if (cpcm->stream[1].substreams)
1398 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1399 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1400 snd_dma_pci_data(chip->pci),
1401 1024 * 64, 1024 * 1024);
1402 chip->pcm[pcm_dev] = pcm;
1403 if (chip->pcm_devs < pcm_dev + 1)
1404 chip->pcm_devs = pcm_dev + 1;
1409 static int __devinit azx_pcm_create(struct azx *chip)
1411 struct hda_codec *codec;
1415 err = snd_hda_build_pcms(chip->bus);
1419 /* create audio PCMs */
1421 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1422 for (c = 0; c < codec->num_pcms; c++) {
1423 if (codec->pcm_info[c].is_modem)
1424 continue; /* create later */
1425 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1426 snd_printk(KERN_ERR SFX
1427 "Too many audio PCMs\n");
1430 err = create_codec_pcm(chip, codec,
1431 &codec->pcm_info[c], pcm_dev);
1438 /* create modem PCMs */
1439 pcm_dev = AZX_MAX_AUDIO_PCMS;
1440 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1441 for (c = 0; c < codec->num_pcms; c++) {
1442 if (!codec->pcm_info[c].is_modem)
1443 continue; /* already created */
1444 if (pcm_dev >= AZX_MAX_PCMS) {
1445 snd_printk(KERN_ERR SFX
1446 "Too many modem PCMs\n");
1449 err = create_codec_pcm(chip, codec,
1450 &codec->pcm_info[c], pcm_dev);
1453 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1461 * mixer creation - all stuff is implemented in hda module
1463 static int __devinit azx_mixer_create(struct azx *chip)
1465 return snd_hda_build_controls(chip->bus);
1470 * initialize SD streams
1472 static int __devinit azx_init_stream(struct azx *chip)
1476 /* initialize each stream (aka device)
1477 * assign the starting bdl address to each stream (device)
1480 for (i = 0; i < chip->num_streams; i++) {
1481 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1482 struct azx_dev *azx_dev = &chip->azx_dev[i];
1483 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1484 azx_dev->bdl_addr = chip->bdl.addr + off;
1485 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1486 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1487 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1488 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1489 azx_dev->sd_int_sta_mask = 1 << i;
1490 /* stream tag: must be non-zero and unique */
1492 azx_dev->stream_tag = i + 1;
1498 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1500 if (request_irq(chip->pci->irq, azx_interrupt,
1501 chip->msi ? 0 : IRQF_SHARED,
1502 "HDA Intel", chip)) {
1503 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1504 "disabling device\n", chip->pci->irq);
1506 snd_card_disconnect(chip->card);
1509 chip->irq = chip->pci->irq;
1510 pci_intx(chip->pci, !chip->msi);
1515 static void azx_stop_chip(struct azx *chip)
1517 if (!chip->initialized)
1520 /* disable interrupts */
1521 azx_int_disable(chip);
1522 azx_int_clear(chip);
1524 /* disable CORB/RIRB */
1525 azx_free_cmd_io(chip);
1527 /* disable position buffer */
1528 azx_writel(chip, DPLBASE, 0);
1529 azx_writel(chip, DPUBASE, 0);
1531 chip->initialized = 0;
1534 #ifdef CONFIG_SND_HDA_POWER_SAVE
1535 /* power-up/down the controller */
1536 static void azx_power_notify(struct hda_codec *codec)
1538 struct azx *chip = codec->bus->private_data;
1539 struct hda_codec *c;
1542 list_for_each_entry(c, &codec->bus->codec_list, list) {
1549 azx_init_chip(chip);
1550 else if (chip->running && power_save_controller)
1551 azx_stop_chip(chip);
1553 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1559 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1561 struct snd_card *card = pci_get_drvdata(pci);
1562 struct azx *chip = card->private_data;
1565 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1566 for (i = 0; i < chip->pcm_devs; i++)
1567 snd_pcm_suspend_all(chip->pcm[i]);
1568 if (chip->initialized)
1569 snd_hda_suspend(chip->bus, state);
1570 azx_stop_chip(chip);
1571 if (chip->irq >= 0) {
1572 synchronize_irq(chip->irq);
1573 free_irq(chip->irq, chip);
1577 pci_disable_msi(chip->pci);
1578 pci_disable_device(pci);
1579 pci_save_state(pci);
1580 pci_set_power_state(pci, pci_choose_state(pci, state));
1584 static int azx_resume(struct pci_dev *pci)
1586 struct snd_card *card = pci_get_drvdata(pci);
1587 struct azx *chip = card->private_data;
1589 pci_set_power_state(pci, PCI_D0);
1590 pci_restore_state(pci);
1591 if (pci_enable_device(pci) < 0) {
1592 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1593 "disabling device\n");
1594 snd_card_disconnect(card);
1597 pci_set_master(pci);
1599 if (pci_enable_msi(pci) < 0)
1601 if (azx_acquire_irq(chip, 1) < 0)
1605 if (snd_hda_codecs_inuse(chip->bus))
1606 azx_init_chip(chip);
1608 snd_hda_resume(chip->bus);
1609 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1612 #endif /* CONFIG_PM */
1618 static int azx_free(struct azx *chip)
1620 if (chip->initialized) {
1622 for (i = 0; i < chip->num_streams; i++)
1623 azx_stream_stop(chip, &chip->azx_dev[i]);
1624 azx_stop_chip(chip);
1627 if (chip->irq >= 0) {
1628 synchronize_irq(chip->irq);
1629 free_irq(chip->irq, (void*)chip);
1632 pci_disable_msi(chip->pci);
1633 if (chip->remap_addr)
1634 iounmap(chip->remap_addr);
1637 snd_dma_free_pages(&chip->bdl);
1639 snd_dma_free_pages(&chip->rb);
1640 if (chip->posbuf.area)
1641 snd_dma_free_pages(&chip->posbuf);
1642 pci_release_regions(chip->pci);
1643 pci_disable_device(chip->pci);
1644 kfree(chip->azx_dev);
1650 static int azx_dev_free(struct snd_device *device)
1652 return azx_free(device->device_data);
1656 * white/black-listing for position_fix
1658 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1659 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1660 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1664 static int __devinit check_position_fix(struct azx *chip, int fix)
1666 const struct snd_pci_quirk *q;
1668 if (fix == POS_FIX_AUTO) {
1669 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1672 "hda_intel: position_fix set to %d "
1673 "for device %04x:%04x\n",
1674 q->value, q->subvendor, q->subdevice);
1682 * black-lists for probe_mask
1684 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1685 /* Thinkpad often breaks the controller communication when accessing
1686 * to the non-working (or non-existing) modem codec slot.
1688 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1689 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1690 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1694 static void __devinit check_probe_mask(struct azx *chip, int dev)
1696 const struct snd_pci_quirk *q;
1698 if (probe_mask[dev] == -1) {
1699 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1702 "hda_intel: probe_mask set to 0x%x "
1703 "for device %04x:%04x\n",
1704 q->value, q->subvendor, q->subdevice);
1705 probe_mask[dev] = q->value;
1714 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1715 int dev, int driver_type,
1720 unsigned short gcap;
1721 static struct snd_device_ops ops = {
1722 .dev_free = azx_dev_free,
1727 err = pci_enable_device(pci);
1731 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1733 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1734 pci_disable_device(pci);
1738 spin_lock_init(&chip->reg_lock);
1739 mutex_init(&chip->open_mutex);
1743 chip->driver_type = driver_type;
1744 chip->msi = enable_msi;
1746 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1747 check_probe_mask(chip, dev);
1749 chip->single_cmd = single_cmd;
1751 #if BITS_PER_LONG != 64
1752 /* Fix up base address on ULI M5461 */
1753 if (chip->driver_type == AZX_DRIVER_ULI) {
1755 pci_read_config_word(pci, 0x40, &tmp3);
1756 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1757 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1761 err = pci_request_regions(pci, "ICH HD audio");
1764 pci_disable_device(pci);
1768 chip->addr = pci_resource_start(pci, 0);
1769 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1770 if (chip->remap_addr == NULL) {
1771 snd_printk(KERN_ERR SFX "ioremap error\n");
1777 if (pci_enable_msi(pci) < 0)
1780 if (azx_acquire_irq(chip, 0) < 0) {
1785 pci_set_master(pci);
1786 synchronize_irq(chip->irq);
1788 gcap = azx_readw(chip, GCAP);
1789 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1792 /* read number of streams from GCAP register instead of using
1795 chip->playback_streams = (gcap & (0xF << 12)) >> 12;
1796 chip->capture_streams = (gcap & (0xF << 8)) >> 8;
1797 chip->playback_index_offset = (gcap & (0xF << 12)) >> 12;
1798 chip->capture_index_offset = 0;
1800 /* gcap didn't give any info, switching to old method */
1802 switch (chip->driver_type) {
1803 case AZX_DRIVER_ULI:
1804 chip->playback_streams = ULI_NUM_PLAYBACK;
1805 chip->capture_streams = ULI_NUM_CAPTURE;
1806 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1807 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1809 case AZX_DRIVER_ATIHDMI:
1810 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1811 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1812 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1813 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1816 chip->playback_streams = ICH6_NUM_PLAYBACK;
1817 chip->capture_streams = ICH6_NUM_CAPTURE;
1818 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1819 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1823 chip->num_streams = chip->playback_streams + chip->capture_streams;
1824 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1826 if (!chip->azx_dev) {
1827 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1831 /* allocate memory for the BDL for each stream */
1832 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1833 snd_dma_pci_data(chip->pci),
1834 BDL_SIZE, &chip->bdl);
1836 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1839 /* allocate memory for the position buffer */
1840 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1841 snd_dma_pci_data(chip->pci),
1842 chip->num_streams * 8, &chip->posbuf);
1844 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1847 /* allocate CORB/RIRB */
1848 if (!chip->single_cmd) {
1849 err = azx_alloc_cmd_io(chip);
1854 /* initialize streams */
1855 azx_init_stream(chip);
1857 /* initialize chip */
1859 azx_init_chip(chip);
1861 /* codec detection */
1862 if (!chip->codec_mask) {
1863 snd_printk(KERN_ERR SFX "no codecs found!\n");
1868 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1870 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1874 strcpy(card->driver, "HDA-Intel");
1875 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1876 sprintf(card->longname, "%s at 0x%lx irq %i",
1877 card->shortname, chip->addr, chip->irq);
1887 static void power_down_all_codecs(struct azx *chip)
1889 #ifdef CONFIG_SND_HDA_POWER_SAVE
1890 /* The codecs were powered up in snd_hda_codec_new().
1891 * Now all initialization done, so turn them down if possible
1893 struct hda_codec *codec;
1894 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1895 snd_hda_power_down(codec);
1900 static int __devinit azx_probe(struct pci_dev *pci,
1901 const struct pci_device_id *pci_id)
1904 struct snd_card *card;
1908 if (dev >= SNDRV_CARDS)
1915 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1917 snd_printk(KERN_ERR SFX "Error creating card!\n");
1921 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1923 snd_card_free(card);
1926 card->private_data = chip;
1928 /* create codec instances */
1929 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1931 snd_card_free(card);
1935 /* create PCM streams */
1936 err = azx_pcm_create(chip);
1938 snd_card_free(card);
1942 /* create mixer controls */
1943 err = azx_mixer_create(chip);
1945 snd_card_free(card);
1949 snd_card_set_dev(card, &pci->dev);
1951 err = snd_card_register(card);
1953 snd_card_free(card);
1957 pci_set_drvdata(pci, card);
1959 power_down_all_codecs(chip);
1965 static void __devexit azx_remove(struct pci_dev *pci)
1967 snd_card_free(pci_get_drvdata(pci));
1968 pci_set_drvdata(pci, NULL);
1972 static struct pci_device_id azx_ids[] = {
1973 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1974 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1975 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1976 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1977 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1978 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1979 { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
1980 { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
1981 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1982 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1983 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1984 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1985 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1986 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1987 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
1988 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
1989 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
1990 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
1991 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
1992 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
1993 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1994 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1995 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1996 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1997 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1998 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1999 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2000 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2001 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2002 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2003 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2004 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2005 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2006 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2007 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2008 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2009 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2010 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2011 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2012 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2013 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2016 MODULE_DEVICE_TABLE(pci, azx_ids);
2018 /* pci_driver definition */
2019 static struct pci_driver driver = {
2020 .name = "HDA Intel",
2021 .id_table = azx_ids,
2023 .remove = __devexit_p(azx_remove),
2025 .suspend = azx_suspend,
2026 .resume = azx_resume,
2030 static int __init alsa_card_azx_init(void)
2032 return pci_register_driver(&driver);
2035 static void __exit alsa_card_azx_exit(void)
2037 pci_unregister_driver(&driver);
2040 module_init(alsa_card_azx_init)
2041 module_exit(alsa_card_azx_exit)