3 * hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
5 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
8 * PeiSen Hou <pshou@realtek.com.tw>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 * Matt Jared matt.jared@intel.com
27 * Andy Kopp andy.kopp@intel.com
28 * Dan Kogan dan.d.kogan@intel.com
32 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
36 #include <sound/driver.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/module.h>
41 #include <linux/moduleparam.h>
42 #include <linux/init.h>
43 #include <linux/slab.h>
44 #include <linux/pci.h>
45 #include <sound/core.h>
46 #include <sound/initval.h>
47 #include "hda_codec.h"
50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
53 static char *model[SNDRV_CARDS];
54 static int position_fix[SNDRV_CARDS];
56 module_param_array(index, int, NULL, 0444);
57 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
58 module_param_array(id, charp, NULL, 0444);
59 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
60 module_param_array(enable, bool, NULL, 0444);
61 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
62 module_param_array(model, charp, NULL, 0444);
63 MODULE_PARM_DESC(model, "Use the given board model.");
64 module_param_array(position_fix, int, NULL, 0444);
65 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF).");
67 MODULE_LICENSE("GPL");
68 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
75 MODULE_DESCRIPTION("Intel HDA driver");
77 #define SFX "hda-intel: "
82 #define ICH6_REG_GCAP 0x00
83 #define ICH6_REG_VMIN 0x02
84 #define ICH6_REG_VMAJ 0x03
85 #define ICH6_REG_OUTPAY 0x04
86 #define ICH6_REG_INPAY 0x06
87 #define ICH6_REG_GCTL 0x08
88 #define ICH6_REG_WAKEEN 0x0c
89 #define ICH6_REG_STATESTS 0x0e
90 #define ICH6_REG_GSTS 0x10
91 #define ICH6_REG_INTCTL 0x20
92 #define ICH6_REG_INTSTS 0x24
93 #define ICH6_REG_WALCLK 0x30
94 #define ICH6_REG_SYNC 0x34
95 #define ICH6_REG_CORBLBASE 0x40
96 #define ICH6_REG_CORBUBASE 0x44
97 #define ICH6_REG_CORBWP 0x48
98 #define ICH6_REG_CORBRP 0x4A
99 #define ICH6_REG_CORBCTL 0x4c
100 #define ICH6_REG_CORBSTS 0x4d
101 #define ICH6_REG_CORBSIZE 0x4e
103 #define ICH6_REG_RIRBLBASE 0x50
104 #define ICH6_REG_RIRBUBASE 0x54
105 #define ICH6_REG_RIRBWP 0x58
106 #define ICH6_REG_RINTCNT 0x5a
107 #define ICH6_REG_RIRBCTL 0x5c
108 #define ICH6_REG_RIRBSTS 0x5d
109 #define ICH6_REG_RIRBSIZE 0x5e
111 #define ICH6_REG_IC 0x60
112 #define ICH6_REG_IR 0x64
113 #define ICH6_REG_IRS 0x68
114 #define ICH6_IRS_VALID (1<<1)
115 #define ICH6_IRS_BUSY (1<<0)
117 #define ICH6_REG_DPLBASE 0x70
118 #define ICH6_REG_DPUBASE 0x74
119 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
121 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
122 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
124 /* stream register offsets from stream base */
125 #define ICH6_REG_SD_CTL 0x00
126 #define ICH6_REG_SD_STS 0x03
127 #define ICH6_REG_SD_LPIB 0x04
128 #define ICH6_REG_SD_CBL 0x08
129 #define ICH6_REG_SD_LVI 0x0c
130 #define ICH6_REG_SD_FIFOW 0x0e
131 #define ICH6_REG_SD_FIFOSIZE 0x10
132 #define ICH6_REG_SD_FORMAT 0x12
133 #define ICH6_REG_SD_BDLPL 0x18
134 #define ICH6_REG_SD_BDLPU 0x1c
137 #define ICH6_PCIREG_TCSEL 0x44
143 /* max number of SDs */
144 #define MAX_ICH6_DEV 8
145 /* max number of fragments - we may use more if allocating more pages for BDL */
146 #define AZX_MAX_FRAG (PAGE_SIZE / (MAX_ICH6_DEV * 16))
147 /* max buffer size - no h/w limit, you can increase as you like */
148 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
149 /* max number of PCM devics per card */
150 #define AZX_MAX_PCMS 8
152 /* RIRB int mask: overrun[2], response[0] */
153 #define RIRB_INT_RESPONSE 0x01
154 #define RIRB_INT_OVERRUN 0x04
155 #define RIRB_INT_MASK 0x05
157 /* STATESTS int mask: SD2,SD1,SD0 */
158 #define STATESTS_INT_MASK 0x07
159 #define AZX_MAX_CODECS 4
162 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
163 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
164 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
165 #define SD_CTL_STREAM_TAG_SHIFT 20
167 /* SD_CTL and SD_STS */
168 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
169 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
170 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
171 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
174 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
176 /* INTCTL and INTSTS */
177 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
178 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
179 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
181 /* GCTL unsolicited response enable bit */
182 #define ICH6_GCTL_UREN (1<<8)
185 #define ICH6_GCTL_RESET (1<<0)
187 /* CORB/RIRB control, read/write pointer */
188 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
189 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
190 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
191 /* below are so far hardcoded - should read registers in future */
192 #define ICH6_MAX_CORB_ENTRIES 256
193 #define ICH6_MAX_RIRB_ENTRIES 256
195 /* position fix mode */
202 /* Defines for ATI HD Audio support in SB450 south bridge */
203 #define ATI_SB450_HDAUDIO_PCI_DEVICE_ID 0x437b
204 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
205 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
209 * Use CORB/RIRB for communication from/to codecs.
210 * This is the way recommended by Intel (see below).
212 #define USE_CORB_RIRB
217 typedef struct snd_azx azx_t;
218 typedef struct snd_azx_rb azx_rb_t;
219 typedef struct snd_azx_dev azx_dev_t;
222 u32 *bdl; /* virtual address of the BDL */
223 dma_addr_t bdl_addr; /* physical address of the BDL */
224 volatile u32 *posbuf; /* position buffer pointer */
226 unsigned int bufsize; /* size of the play buffer in bytes */
227 unsigned int fragsize; /* size of each period in bytes */
228 unsigned int frags; /* number for period in the play buffer */
229 unsigned int fifo_size; /* FIFO size */
231 void __iomem *sd_addr; /* stream descriptor pointer */
233 u32 sd_int_sta_mask; /* stream int status mask */
236 snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
237 unsigned int format_val; /* format value to be set in the controller and the codec */
238 unsigned char stream_tag; /* assigned stream */
239 unsigned char index; /* stream index */
241 unsigned int opened: 1;
242 unsigned int running: 1;
247 u32 *buf; /* CORB/RIRB buffer
248 * Each CORB entry is 4byte, RIRB is 8byte
250 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
252 unsigned short rp, wp; /* read/write pointers */
253 int cmds; /* number of pending requests */
254 u32 res; /* last read value */
263 void __iomem *remap_addr;
268 struct semaphore open_mutex;
271 azx_dev_t azx_dev[MAX_ICH6_DEV];
274 unsigned int pcm_devs;
275 snd_pcm_t *pcm[AZX_MAX_PCMS];
278 unsigned short codec_mask;
285 /* BDL, CORB/RIRB and position buffers */
286 struct snd_dma_buffer bdl;
287 struct snd_dma_buffer rb;
288 struct snd_dma_buffer posbuf;
292 unsigned int initialized: 1;
296 * macros for easy use
298 #define azx_writel(chip,reg,value) \
299 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
300 #define azx_readl(chip,reg) \
301 readl((chip)->remap_addr + ICH6_REG_##reg)
302 #define azx_writew(chip,reg,value) \
303 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
304 #define azx_readw(chip,reg) \
305 readw((chip)->remap_addr + ICH6_REG_##reg)
306 #define azx_writeb(chip,reg,value) \
307 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
308 #define azx_readb(chip,reg) \
309 readb((chip)->remap_addr + ICH6_REG_##reg)
311 #define azx_sd_writel(dev,reg,value) \
312 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
313 #define azx_sd_readl(dev,reg) \
314 readl((dev)->sd_addr + ICH6_REG_##reg)
315 #define azx_sd_writew(dev,reg,value) \
316 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
317 #define azx_sd_readw(dev,reg) \
318 readw((dev)->sd_addr + ICH6_REG_##reg)
319 #define azx_sd_writeb(dev,reg,value) \
320 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
321 #define azx_sd_readb(dev,reg) \
322 readb((dev)->sd_addr + ICH6_REG_##reg)
324 /* for pcm support */
325 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
327 /* Get the upper 32bit of the given dma_addr_t
328 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
330 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
334 * Interface for HD codec
339 * CORB / RIRB interface
341 static int azx_alloc_cmd_io(azx_t *chip)
345 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
346 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
347 PAGE_SIZE, &chip->rb);
349 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
355 static void azx_init_cmd_io(azx_t *chip)
358 chip->corb.addr = chip->rb.addr;
359 chip->corb.buf = (u32 *)chip->rb.area;
360 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
361 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
363 /* set the corb write pointer to 0 */
364 azx_writew(chip, CORBWP, 0);
365 /* reset the corb hw read pointer */
366 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
367 /* enable corb dma */
368 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
371 chip->rirb.addr = chip->rb.addr + 2048;
372 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
373 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
374 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
376 /* reset the rirb hw write pointer */
377 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
378 /* set N=1, get RIRB response interrupt for new entry */
379 azx_writew(chip, RINTCNT, 1);
380 /* enable rirb dma and response irq */
382 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
384 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
386 chip->rirb.rp = chip->rirb.cmds = 0;
389 static void azx_free_cmd_io(azx_t *chip)
391 /* disable ringbuffer DMAs */
392 azx_writeb(chip, RIRBCTL, 0);
393 azx_writeb(chip, CORBCTL, 0);
397 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
398 unsigned int verb, unsigned int para)
400 azx_t *chip = codec->bus->private_data;
404 val = (u32)(codec->addr & 0x0f) << 28;
405 val |= (u32)direct << 27;
406 val |= (u32)nid << 20;
410 /* add command to corb */
411 wp = azx_readb(chip, CORBWP);
413 wp %= ICH6_MAX_CORB_ENTRIES;
415 spin_lock_irq(&chip->reg_lock);
417 chip->corb.buf[wp] = cpu_to_le32(val);
418 azx_writel(chip, CORBWP, wp);
419 spin_unlock_irq(&chip->reg_lock);
424 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
426 /* retrieve RIRB entry - called from interrupt handler */
427 static void azx_update_rirb(azx_t *chip)
432 wp = azx_readb(chip, RIRBWP);
433 if (wp == chip->rirb.wp)
437 while (chip->rirb.rp != wp) {
439 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
441 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
442 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
443 res = le32_to_cpu(chip->rirb.buf[rp]);
444 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
445 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
446 else if (chip->rirb.cmds) {
448 chip->rirb.res = res;
453 /* receive a response */
454 static unsigned int azx_get_response(struct hda_codec *codec)
456 azx_t *chip = codec->bus->private_data;
459 while (chip->rirb.cmds) {
461 snd_printk(KERN_ERR "azx_get_response timeout\n");
462 chip->rirb.rp = azx_readb(chip, RIRBWP);
468 return chip->rirb.res; /* the last value */
473 * Use the single immediate command instead of CORB/RIRB for simplicity
475 * Note: according to Intel, this is not preferred use. The command was
476 * intended for the BIOS only, and may get confused with unsolicited
477 * responses. So, we shouldn't use it for normal operation from the
479 * I left the codes, however, for debugging/testing purposes.
482 #define azx_alloc_cmd_io(chip) 0
483 #define azx_init_cmd_io(chip)
484 #define azx_free_cmd_io(chip)
487 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
488 unsigned int verb, unsigned int para)
490 azx_t *chip = codec->bus->private_data;
494 val = (u32)(codec->addr & 0x0f) << 28;
495 val |= (u32)direct << 27;
496 val |= (u32)nid << 20;
501 /* check ICB busy bit */
502 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
503 /* Clear IRV valid bit */
504 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
505 azx_writel(chip, IC, val);
506 azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
511 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
515 /* receive a response */
516 static unsigned int azx_get_response(struct hda_codec *codec)
518 azx_t *chip = codec->bus->private_data;
522 /* check IRV busy bit */
523 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
524 return azx_readl(chip, IR);
527 snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
528 return (unsigned int)-1;
531 #define azx_update_rirb(chip)
533 #endif /* USE_CORB_RIRB */
535 /* reset codec link */
536 static int azx_reset(azx_t *chip)
540 /* reset controller */
541 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
544 while (azx_readb(chip, GCTL) && --count)
547 /* delay for >= 100us for codec PLL to settle per spec
548 * Rev 0.9 section 5.5.1
552 /* Bring controller out of reset */
553 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
556 while (! azx_readb(chip, GCTL) && --count)
559 /* Brent Chartrand said to wait >= 540us for codecs to intialize */
562 /* check to see if controller is ready */
563 if (! azx_readb(chip, GCTL)) {
564 snd_printd("azx_reset: controller not ready!\n");
568 /* Accept unsolicited responses */
569 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
572 if (! chip->codec_mask) {
573 chip->codec_mask = azx_readw(chip, STATESTS);
574 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
585 /* enable interrupts */
586 static void azx_int_enable(azx_t *chip)
588 /* enable controller CIE and GIE */
589 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
590 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
593 /* disable interrupts */
594 static void azx_int_disable(azx_t *chip)
598 /* disable interrupts in stream descriptor */
599 for (i = 0; i < MAX_ICH6_DEV; i++) {
600 azx_dev_t *azx_dev = &chip->azx_dev[i];
601 azx_sd_writeb(azx_dev, SD_CTL,
602 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
605 /* disable SIE for all streams */
606 azx_writeb(chip, INTCTL, 0);
608 /* disable controller CIE and GIE */
609 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
610 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
613 /* clear interrupts */
614 static void azx_int_clear(azx_t *chip)
618 /* clear stream status */
619 for (i = 0; i < MAX_ICH6_DEV; i++) {
620 azx_dev_t *azx_dev = &chip->azx_dev[i];
621 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
625 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
627 /* clear rirb status */
628 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
630 /* clear int status */
631 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
635 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
638 azx_writeb(chip, INTCTL,
639 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
640 /* set DMA start and interrupt mask */
641 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
642 SD_CTL_DMA_START | SD_INT_MASK);
646 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
649 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
650 ~(SD_CTL_DMA_START | SD_INT_MASK));
651 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
653 azx_writeb(chip, INTCTL,
654 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
659 * initialize the chip
661 static void azx_init_chip(azx_t *chip)
663 unsigned char tcsel_reg, ati_misc_cntl2;
665 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
666 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
667 * Ensuring these bits are 0 clears playback static on some HD Audio codecs
669 pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
670 pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
672 /* reset controller */
675 /* initialize interrupts */
677 azx_int_enable(chip);
679 /* initialize the codec command I/O */
680 azx_init_cmd_io(chip);
682 if (chip->position_fix == POS_FIX_POSBUF) {
683 /* program the position buffer */
684 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
685 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
688 /* For ATI SB450 azalia HD audio, we need to enable snoop */
689 if (chip->pci->vendor == PCI_VENDOR_ID_ATI &&
690 chip->pci->device == ATI_SB450_HDAUDIO_PCI_DEVICE_ID) {
691 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
693 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
694 (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
702 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
704 azx_t *chip = dev_id;
709 spin_lock(&chip->reg_lock);
711 status = azx_readl(chip, INTSTS);
713 spin_unlock(&chip->reg_lock);
717 for (i = 0; i < MAX_ICH6_DEV; i++) {
718 azx_dev = &chip->azx_dev[i];
719 if (status & azx_dev->sd_int_sta_mask) {
720 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
721 if (azx_dev->substream && azx_dev->running) {
722 spin_unlock(&chip->reg_lock);
723 snd_pcm_period_elapsed(azx_dev->substream);
724 spin_lock(&chip->reg_lock);
730 status = azx_readb(chip, RIRBSTS);
731 if (status & RIRB_INT_MASK) {
732 if (status & RIRB_INT_RESPONSE)
733 azx_update_rirb(chip);
734 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
738 /* clear state status int */
739 if (azx_readb(chip, STATESTS) & 0x04)
740 azx_writeb(chip, STATESTS, 0x04);
742 spin_unlock(&chip->reg_lock);
751 static void azx_setup_periods(azx_dev_t *azx_dev)
753 u32 *bdl = azx_dev->bdl;
754 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
757 /* reset BDL address */
758 azx_sd_writel(azx_dev, SD_BDLPL, 0);
759 azx_sd_writel(azx_dev, SD_BDLPU, 0);
761 /* program the initial BDL entries */
762 for (idx = 0; idx < azx_dev->frags; idx++) {
763 unsigned int off = idx << 2; /* 4 dword step */
764 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
765 /* program the address field of the BDL entry */
766 bdl[off] = cpu_to_le32((u32)addr);
767 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
769 /* program the size field of the BDL entry */
770 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
772 /* program the IOC to enable interrupt when buffer completes */
773 bdl[off+3] = cpu_to_le32(0x01);
778 * set up the SD for streaming
780 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
785 /* make sure the run bit is zero for SD */
786 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
788 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
791 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
794 val &= ~SD_CTL_STREAM_RESET;
795 azx_sd_writeb(azx_dev, SD_CTL, val);
799 /* waiting for hardware to report that the stream is out of reset */
800 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
804 /* program the stream_tag */
805 azx_sd_writel(azx_dev, SD_CTL,
806 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
807 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
809 /* program the length of samples in cyclic buffer */
810 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
812 /* program the stream format */
813 /* this value needs to be the same as the one programmed */
814 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
816 /* program the stream LVI (last valid index) of the BDL */
817 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
819 /* program the BDL address */
820 /* lower BDL address */
821 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
822 /* upper BDL address */
823 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
825 if (chip->position_fix == POS_FIX_POSBUF) {
826 /* enable the position buffer */
827 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
828 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
831 /* set the interrupt enable bits in the descriptor control register */
832 azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
839 * Codec initialization
842 static int __devinit azx_codec_create(azx_t *chip, const char *model)
844 struct hda_bus_template bus_temp;
847 memset(&bus_temp, 0, sizeof(bus_temp));
848 bus_temp.private_data = chip;
849 bus_temp.modelname = model;
850 bus_temp.pci = chip->pci;
851 bus_temp.ops.command = azx_send_cmd;
852 bus_temp.ops.get_response = azx_get_response;
854 if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
858 for (c = 0; c < AZX_MAX_CODECS; c++) {
859 if (chip->codec_mask & (1 << c)) {
860 err = snd_hda_codec_new(chip->bus, c, NULL);
867 snd_printk(KERN_ERR SFX "no codecs initialized\n");
879 /* assign a stream for the PCM */
880 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
883 dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
884 for (i = 0; i < 4; i++, dev++)
885 if (! chip->azx_dev[dev].opened) {
886 chip->azx_dev[dev].opened = 1;
887 return &chip->azx_dev[dev];
892 /* release the assigned stream */
893 static inline void azx_release_device(azx_dev_t *azx_dev)
898 static snd_pcm_hardware_t azx_pcm_hw = {
899 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
900 SNDRV_PCM_INFO_BLOCK_TRANSFER |
901 SNDRV_PCM_INFO_MMAP_VALID |
902 SNDRV_PCM_INFO_PAUSE |
903 SNDRV_PCM_INFO_RESUME),
904 .formats = SNDRV_PCM_FMTBIT_S16_LE,
905 .rates = SNDRV_PCM_RATE_48000,
910 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
911 .period_bytes_min = 128,
912 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
914 .periods_max = AZX_MAX_FRAG,
920 struct hda_codec *codec;
921 struct hda_pcm_stream *hinfo[2];
924 static int azx_pcm_open(snd_pcm_substream_t *substream)
926 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
927 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
928 azx_t *chip = apcm->chip;
930 snd_pcm_runtime_t *runtime = substream->runtime;
934 down(&chip->open_mutex);
935 azx_dev = azx_assign_device(chip, substream->stream);
936 if (azx_dev == NULL) {
937 up(&chip->open_mutex);
940 runtime->hw = azx_pcm_hw;
941 runtime->hw.channels_min = hinfo->channels_min;
942 runtime->hw.channels_max = hinfo->channels_max;
943 runtime->hw.formats = hinfo->formats;
944 runtime->hw.rates = hinfo->rates;
945 snd_pcm_limit_hw_rates(runtime);
946 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
947 if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
948 azx_release_device(azx_dev);
949 up(&chip->open_mutex);
952 spin_lock_irqsave(&chip->reg_lock, flags);
953 azx_dev->substream = substream;
954 azx_dev->running = 0;
955 spin_unlock_irqrestore(&chip->reg_lock, flags);
957 runtime->private_data = azx_dev;
958 up(&chip->open_mutex);
962 static int azx_pcm_close(snd_pcm_substream_t *substream)
964 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
965 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
966 azx_t *chip = apcm->chip;
967 azx_dev_t *azx_dev = get_azx_dev(substream);
970 down(&chip->open_mutex);
971 spin_lock_irqsave(&chip->reg_lock, flags);
972 azx_dev->substream = NULL;
973 azx_dev->running = 0;
974 spin_unlock_irqrestore(&chip->reg_lock, flags);
975 azx_release_device(azx_dev);
976 hinfo->ops.close(hinfo, apcm->codec, substream);
977 up(&chip->open_mutex);
981 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
983 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
986 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
988 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
989 azx_dev_t *azx_dev = get_azx_dev(substream);
990 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
992 /* reset BDL address */
993 azx_sd_writel(azx_dev, SD_BDLPL, 0);
994 azx_sd_writel(azx_dev, SD_BDLPU, 0);
995 azx_sd_writel(azx_dev, SD_CTL, 0);
997 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
999 return snd_pcm_lib_free_pages(substream);
1002 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
1004 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1005 azx_t *chip = apcm->chip;
1006 azx_dev_t *azx_dev = get_azx_dev(substream);
1007 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1008 snd_pcm_runtime_t *runtime = substream->runtime;
1010 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1011 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1012 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1013 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1017 if (! azx_dev->format_val) {
1018 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1019 runtime->rate, runtime->channels, runtime->format);
1023 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1024 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1025 azx_setup_periods(azx_dev);
1026 azx_setup_controller(chip, azx_dev);
1027 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1028 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1030 azx_dev->fifo_size = 0;
1032 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1033 azx_dev->format_val, substream);
1036 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1038 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1039 azx_dev_t *azx_dev = get_azx_dev(substream);
1040 azx_t *chip = apcm->chip;
1043 spin_lock(&chip->reg_lock);
1045 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1046 case SNDRV_PCM_TRIGGER_RESUME:
1047 case SNDRV_PCM_TRIGGER_START:
1048 azx_stream_start(chip, azx_dev);
1049 azx_dev->running = 1;
1051 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1052 case SNDRV_PCM_TRIGGER_STOP:
1053 azx_stream_stop(chip, azx_dev);
1054 azx_dev->running = 0;
1059 spin_unlock(&chip->reg_lock);
1060 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1061 cmd == SNDRV_PCM_TRIGGER_STOP) {
1063 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1069 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1072 azx_t *chip = apcm->chip;
1073 azx_dev_t *azx_dev = get_azx_dev(substream);
1076 if (chip->position_fix == POS_FIX_POSBUF) {
1077 /* use the position buffer */
1078 pos = *azx_dev->posbuf;
1081 pos = azx_sd_readl(azx_dev, SD_LPIB);
1082 if (chip->position_fix == POS_FIX_FIFO)
1083 pos += azx_dev->fifo_size;
1085 if (pos >= azx_dev->bufsize)
1087 return bytes_to_frames(substream->runtime, pos);
1090 static snd_pcm_ops_t azx_pcm_ops = {
1091 .open = azx_pcm_open,
1092 .close = azx_pcm_close,
1093 .ioctl = snd_pcm_lib_ioctl,
1094 .hw_params = azx_pcm_hw_params,
1095 .hw_free = azx_pcm_hw_free,
1096 .prepare = azx_pcm_prepare,
1097 .trigger = azx_pcm_trigger,
1098 .pointer = azx_pcm_pointer,
1101 static void azx_pcm_free(snd_pcm_t *pcm)
1103 kfree(pcm->private_data);
1106 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1107 struct hda_pcm *cpcm, int pcm_dev)
1111 struct azx_pcm *apcm;
1113 snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1114 snd_assert(cpcm->name, return -EINVAL);
1116 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1117 cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1121 strcpy(pcm->name, cpcm->name);
1122 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1126 apcm->codec = codec;
1127 apcm->hinfo[0] = &cpcm->stream[0];
1128 apcm->hinfo[1] = &cpcm->stream[1];
1129 pcm->private_data = apcm;
1130 pcm->private_free = azx_pcm_free;
1131 if (cpcm->stream[0].substreams)
1132 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1133 if (cpcm->stream[1].substreams)
1134 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1135 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1136 snd_dma_pci_data(chip->pci),
1137 1024 * 64, 1024 * 128);
1138 chip->pcm[pcm_dev] = pcm;
1143 static int __devinit azx_pcm_create(azx_t *chip)
1145 struct list_head *p;
1146 struct hda_codec *codec;
1150 if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1154 list_for_each(p, &chip->bus->codec_list) {
1155 codec = list_entry(p, struct hda_codec, list);
1156 for (c = 0; c < codec->num_pcms; c++) {
1157 if (pcm_dev >= AZX_MAX_PCMS) {
1158 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1161 err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1171 * mixer creation - all stuff is implemented in hda module
1173 static int __devinit azx_mixer_create(azx_t *chip)
1175 return snd_hda_build_controls(chip->bus);
1180 * initialize SD streams
1182 static int __devinit azx_init_stream(azx_t *chip)
1186 /* initialize each stream (aka device)
1187 * assign the starting bdl address to each stream (device) and initialize
1189 for (i = 0; i < MAX_ICH6_DEV; i++) {
1190 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1191 azx_dev_t *azx_dev = &chip->azx_dev[i];
1192 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1193 azx_dev->bdl_addr = chip->bdl.addr + off;
1194 if (chip->position_fix == POS_FIX_POSBUF)
1195 azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1196 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1197 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1198 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1199 azx_dev->sd_int_sta_mask = 1 << i;
1200 /* stream tag: must be non-zero and unique */
1202 azx_dev->stream_tag = i + 1;
1213 static int azx_suspend(snd_card_t *card, pm_message_t state)
1215 azx_t *chip = card->pm_private_data;
1218 for (i = 0; i < chip->pcm_devs; i++)
1220 snd_pcm_suspend_all(chip->pcm[i]);
1221 snd_hda_suspend(chip->bus, state);
1222 azx_free_cmd_io(chip);
1223 pci_disable_device(chip->pci);
1227 static int azx_resume(snd_card_t *card)
1229 azx_t *chip = card->pm_private_data;
1231 pci_enable_device(chip->pci);
1232 pci_set_master(chip->pci);
1233 azx_init_chip(chip);
1234 snd_hda_resume(chip->bus);
1237 #endif /* CONFIG_PM */
1243 static int azx_free(azx_t *chip)
1245 if (chip->initialized) {
1248 for (i = 0; i < MAX_ICH6_DEV; i++)
1249 azx_stream_stop(chip, &chip->azx_dev[i]);
1251 /* disable interrupts */
1252 azx_int_disable(chip);
1253 azx_int_clear(chip);
1255 /* disable CORB/RIRB */
1256 azx_free_cmd_io(chip);
1258 /* disable position buffer */
1259 azx_writel(chip, DPLBASE, 0);
1260 azx_writel(chip, DPUBASE, 0);
1262 /* wait a little for interrupts to finish */
1265 iounmap(chip->remap_addr);
1269 free_irq(chip->irq, (void*)chip);
1272 snd_dma_free_pages(&chip->bdl);
1274 snd_dma_free_pages(&chip->rb);
1275 if (chip->posbuf.area)
1276 snd_dma_free_pages(&chip->posbuf);
1277 pci_release_regions(chip->pci);
1278 pci_disable_device(chip->pci);
1284 static int azx_dev_free(snd_device_t *device)
1286 return azx_free(device->device_data);
1292 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
1293 int posfix, azx_t **rchip)
1297 static snd_device_ops_t ops = {
1298 .dev_free = azx_dev_free,
1303 if ((err = pci_enable_device(pci)) < 0)
1306 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1309 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1310 pci_disable_device(pci);
1314 spin_lock_init(&chip->reg_lock);
1315 init_MUTEX(&chip->open_mutex);
1320 chip->position_fix = posfix;
1322 if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1324 pci_disable_device(pci);
1328 chip->addr = pci_resource_start(pci,0);
1329 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1330 if (chip->remap_addr == NULL) {
1331 snd_printk(KERN_ERR SFX "ioremap error\n");
1336 if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1337 "HDA Intel", (void*)chip)) {
1338 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1342 chip->irq = pci->irq;
1344 pci_set_master(pci);
1345 synchronize_irq(chip->irq);
1347 /* allocate memory for the BDL for each stream */
1348 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1349 PAGE_SIZE, &chip->bdl)) < 0) {
1350 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1353 if (chip->position_fix == POS_FIX_POSBUF) {
1354 /* allocate memory for the position buffer */
1355 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1356 MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
1357 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1361 /* allocate CORB/RIRB */
1362 if ((err = azx_alloc_cmd_io(chip)) < 0)
1365 /* initialize streams */
1366 azx_init_stream(chip);
1368 /* initialize chip */
1369 azx_init_chip(chip);
1371 chip->initialized = 1;
1373 /* codec detection */
1374 if (! chip->codec_mask) {
1375 snd_printk(KERN_ERR SFX "no codecs found!\n");
1380 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1381 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1393 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1400 if (dev >= SNDRV_CARDS)
1402 if (! enable[dev]) {
1407 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1409 snd_printk(KERN_ERR SFX "Error creating card!\n");
1413 if ((err = azx_create(card, pci, position_fix[dev], &chip)) < 0) {
1414 snd_card_free(card);
1418 strcpy(card->driver, "HDA-Intel");
1419 strcpy(card->shortname, "HDA Intel");
1420 sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1422 /* create codec instances */
1423 if ((err = azx_codec_create(chip, model[dev])) < 0) {
1424 snd_card_free(card);
1428 /* create PCM streams */
1429 if ((err = azx_pcm_create(chip)) < 0) {
1430 snd_card_free(card);
1434 /* create mixer controls */
1435 if ((err = azx_mixer_create(chip)) < 0) {
1436 snd_card_free(card);
1440 snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1441 snd_card_set_dev(card, &pci->dev);
1443 if ((err = snd_card_register(card)) < 0) {
1444 snd_card_free(card);
1448 pci_set_drvdata(pci, card);
1454 static void __devexit azx_remove(struct pci_dev *pci)
1456 snd_card_free(pci_get_drvdata(pci));
1457 pci_set_drvdata(pci, NULL);
1461 static struct pci_device_id azx_ids[] = {
1462 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
1463 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
1464 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
1465 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ATI SB450 */
1466 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* VIA VT8251/VT8237A */
1467 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ALI 5461? */
1470 MODULE_DEVICE_TABLE(pci, azx_ids);
1472 /* pci_driver definition */
1473 static struct pci_driver driver = {
1474 .name = "HDA Intel",
1475 .id_table = azx_ids,
1477 .remove = __devexit_p(azx_remove),
1478 SND_PCI_PM_CALLBACKS
1481 static int __init alsa_card_azx_init(void)
1483 return pci_register_driver(&driver);
1486 static void __exit alsa_card_azx_exit(void)
1488 pci_unregister_driver(&driver);
1491 module_init(alsa_card_azx_init)
1492 module_exit(alsa_card_azx_exit)