3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <sound/driver.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <sound/core.h>
49 #include <sound/initval.h>
50 #include "hda_codec.h"
53 static int index = SNDRV_DEFAULT_IDX1;
54 static char *id = SNDRV_DEFAULT_STR1;
56 static int position_fix;
57 static int probe_mask = -1;
58 static int single_cmd;
59 static int enable_msi;
61 module_param(index, int, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param(id, charp, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param(model, charp, 0444);
66 MODULE_PARM_DESC(model, "Use the given board model.");
67 module_param(position_fix, int, 0444);
68 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
69 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
70 module_param(probe_mask, int, 0444);
71 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
72 module_param(single_cmd, bool, 0444);
73 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
74 "(for debugging only).");
75 module_param(enable_msi, int, 0);
76 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
78 /* power_save option is defined in hda_codec.c */
80 /* just for backward compatibility */
82 module_param(enable, bool, 0444);
84 MODULE_LICENSE("GPL");
85 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
101 MODULE_DESCRIPTION("Intel HDA driver");
103 #define SFX "hda-intel: "
110 * reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
114 #define HDA_POWER_SAVE_RESET_CONTROLLER
120 #define ICH6_REG_GCAP 0x00
121 #define ICH6_REG_VMIN 0x02
122 #define ICH6_REG_VMAJ 0x03
123 #define ICH6_REG_OUTPAY 0x04
124 #define ICH6_REG_INPAY 0x06
125 #define ICH6_REG_GCTL 0x08
126 #define ICH6_REG_WAKEEN 0x0c
127 #define ICH6_REG_STATESTS 0x0e
128 #define ICH6_REG_GSTS 0x10
129 #define ICH6_REG_INTCTL 0x20
130 #define ICH6_REG_INTSTS 0x24
131 #define ICH6_REG_WALCLK 0x30
132 #define ICH6_REG_SYNC 0x34
133 #define ICH6_REG_CORBLBASE 0x40
134 #define ICH6_REG_CORBUBASE 0x44
135 #define ICH6_REG_CORBWP 0x48
136 #define ICH6_REG_CORBRP 0x4A
137 #define ICH6_REG_CORBCTL 0x4c
138 #define ICH6_REG_CORBSTS 0x4d
139 #define ICH6_REG_CORBSIZE 0x4e
141 #define ICH6_REG_RIRBLBASE 0x50
142 #define ICH6_REG_RIRBUBASE 0x54
143 #define ICH6_REG_RIRBWP 0x58
144 #define ICH6_REG_RINTCNT 0x5a
145 #define ICH6_REG_RIRBCTL 0x5c
146 #define ICH6_REG_RIRBSTS 0x5d
147 #define ICH6_REG_RIRBSIZE 0x5e
149 #define ICH6_REG_IC 0x60
150 #define ICH6_REG_IR 0x64
151 #define ICH6_REG_IRS 0x68
152 #define ICH6_IRS_VALID (1<<1)
153 #define ICH6_IRS_BUSY (1<<0)
155 #define ICH6_REG_DPLBASE 0x70
156 #define ICH6_REG_DPUBASE 0x74
157 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
159 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
160 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
162 /* stream register offsets from stream base */
163 #define ICH6_REG_SD_CTL 0x00
164 #define ICH6_REG_SD_STS 0x03
165 #define ICH6_REG_SD_LPIB 0x04
166 #define ICH6_REG_SD_CBL 0x08
167 #define ICH6_REG_SD_LVI 0x0c
168 #define ICH6_REG_SD_FIFOW 0x0e
169 #define ICH6_REG_SD_FIFOSIZE 0x10
170 #define ICH6_REG_SD_FORMAT 0x12
171 #define ICH6_REG_SD_BDLPL 0x18
172 #define ICH6_REG_SD_BDLPU 0x1c
175 #define ICH6_PCIREG_TCSEL 0x44
181 /* max number of SDs */
182 /* ICH, ATI and VIA have 4 playback and 4 capture */
183 #define ICH6_CAPTURE_INDEX 0
184 #define ICH6_NUM_CAPTURE 4
185 #define ICH6_PLAYBACK_INDEX 4
186 #define ICH6_NUM_PLAYBACK 4
188 /* ULI has 6 playback and 5 capture */
189 #define ULI_CAPTURE_INDEX 0
190 #define ULI_NUM_CAPTURE 5
191 #define ULI_PLAYBACK_INDEX 5
192 #define ULI_NUM_PLAYBACK 6
194 /* ATI HDMI has 1 playback and 0 capture */
195 #define ATIHDMI_CAPTURE_INDEX 0
196 #define ATIHDMI_NUM_CAPTURE 0
197 #define ATIHDMI_PLAYBACK_INDEX 0
198 #define ATIHDMI_NUM_PLAYBACK 1
200 /* this number is statically defined for simplicity */
201 #define MAX_AZX_DEV 16
203 /* max number of fragments - we may use more if allocating more pages for BDL */
204 #define BDL_SIZE PAGE_ALIGN(8192)
205 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
206 /* max buffer size - no h/w limit, you can increase as you like */
207 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
208 /* max number of PCM devics per card */
209 #define AZX_MAX_AUDIO_PCMS 6
210 #define AZX_MAX_MODEM_PCMS 2
211 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
213 /* RIRB int mask: overrun[2], response[0] */
214 #define RIRB_INT_RESPONSE 0x01
215 #define RIRB_INT_OVERRUN 0x04
216 #define RIRB_INT_MASK 0x05
218 /* STATESTS int mask: SD2,SD1,SD0 */
219 #define AZX_MAX_CODECS 3
220 #define STATESTS_INT_MASK 0x07
223 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
224 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
225 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
226 #define SD_CTL_STREAM_TAG_SHIFT 20
228 /* SD_CTL and SD_STS */
229 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
230 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
231 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
232 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
236 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
238 /* INTCTL and INTSTS */
239 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
240 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
241 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
243 /* GCTL unsolicited response enable bit */
244 #define ICH6_GCTL_UREN (1<<8)
247 #define ICH6_GCTL_RESET (1<<0)
249 /* CORB/RIRB control, read/write pointer */
250 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
251 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
252 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
253 /* below are so far hardcoded - should read registers in future */
254 #define ICH6_MAX_CORB_ENTRIES 256
255 #define ICH6_MAX_RIRB_ENTRIES 256
257 /* position fix mode */
265 /* Defines for ATI HD Audio support in SB450 south bridge */
266 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
267 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
269 /* Defines for Nvidia HDA support */
270 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
271 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
277 u32 *bdl; /* virtual address of the BDL */
278 dma_addr_t bdl_addr; /* physical address of the BDL */
279 u32 *posbuf; /* position buffer pointer */
281 unsigned int bufsize; /* size of the play buffer in bytes */
282 unsigned int fragsize; /* size of each period in bytes */
283 unsigned int frags; /* number for period in the play buffer */
284 unsigned int fifo_size; /* FIFO size */
286 void __iomem *sd_addr; /* stream descriptor pointer */
288 u32 sd_int_sta_mask; /* stream int status mask */
291 struct snd_pcm_substream *substream; /* assigned substream,
294 unsigned int format_val; /* format value to be set in the
295 * controller and the codec
297 unsigned char stream_tag; /* assigned stream */
298 unsigned char index; /* stream index */
299 /* for sanity check of position buffer */
300 unsigned int period_intr;
302 unsigned int opened :1;
303 unsigned int running :1;
308 u32 *buf; /* CORB/RIRB buffer
309 * Each CORB entry is 4byte, RIRB is 8byte
311 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
313 unsigned short rp, wp; /* read/write pointers */
314 int cmds; /* number of pending requests */
315 u32 res; /* last read value */
319 struct snd_card *card;
322 /* chip type specific */
324 int playback_streams;
325 int playback_index_offset;
327 int capture_index_offset;
332 void __iomem *remap_addr;
337 struct mutex open_mutex;
339 /* streams (x num_streams) */
340 struct azx_dev *azx_dev;
343 unsigned int pcm_devs;
344 struct snd_pcm *pcm[AZX_MAX_PCMS];
347 unsigned short codec_mask;
354 /* BDL, CORB/RIRB and position buffers */
355 struct snd_dma_buffer bdl;
356 struct snd_dma_buffer rb;
357 struct snd_dma_buffer posbuf;
361 unsigned int running :1;
362 unsigned int initialized :1;
363 unsigned int single_cmd :1;
364 unsigned int polling_mode :1;
368 unsigned int last_cmd; /* last issued command (to sync) */
382 static char *driver_short_names[] __devinitdata = {
383 [AZX_DRIVER_ICH] = "HDA Intel",
384 [AZX_DRIVER_ATI] = "HDA ATI SB",
385 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
386 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
387 [AZX_DRIVER_SIS] = "HDA SIS966",
388 [AZX_DRIVER_ULI] = "HDA ULI M5461",
389 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
393 * macros for easy use
395 #define azx_writel(chip,reg,value) \
396 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
397 #define azx_readl(chip,reg) \
398 readl((chip)->remap_addr + ICH6_REG_##reg)
399 #define azx_writew(chip,reg,value) \
400 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
401 #define azx_readw(chip,reg) \
402 readw((chip)->remap_addr + ICH6_REG_##reg)
403 #define azx_writeb(chip,reg,value) \
404 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
405 #define azx_readb(chip,reg) \
406 readb((chip)->remap_addr + ICH6_REG_##reg)
408 #define azx_sd_writel(dev,reg,value) \
409 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
410 #define azx_sd_readl(dev,reg) \
411 readl((dev)->sd_addr + ICH6_REG_##reg)
412 #define azx_sd_writew(dev,reg,value) \
413 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
414 #define azx_sd_readw(dev,reg) \
415 readw((dev)->sd_addr + ICH6_REG_##reg)
416 #define azx_sd_writeb(dev,reg,value) \
417 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
418 #define azx_sd_readb(dev,reg) \
419 readb((dev)->sd_addr + ICH6_REG_##reg)
421 /* for pcm support */
422 #define get_azx_dev(substream) (substream->runtime->private_data)
424 /* Get the upper 32bit of the given dma_addr_t
425 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
427 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
429 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
432 * Interface for HD codec
436 * CORB / RIRB interface
438 static int azx_alloc_cmd_io(struct azx *chip)
442 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
443 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
444 snd_dma_pci_data(chip->pci),
445 PAGE_SIZE, &chip->rb);
447 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
453 static void azx_init_cmd_io(struct azx *chip)
456 chip->corb.addr = chip->rb.addr;
457 chip->corb.buf = (u32 *)chip->rb.area;
458 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
459 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
461 /* set the corb size to 256 entries (ULI requires explicitly) */
462 azx_writeb(chip, CORBSIZE, 0x02);
463 /* set the corb write pointer to 0 */
464 azx_writew(chip, CORBWP, 0);
465 /* reset the corb hw read pointer */
466 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
467 /* enable corb dma */
468 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
471 chip->rirb.addr = chip->rb.addr + 2048;
472 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
473 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
474 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
476 /* set the rirb size to 256 entries (ULI requires explicitly) */
477 azx_writeb(chip, RIRBSIZE, 0x02);
478 /* reset the rirb hw write pointer */
479 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
480 /* set N=1, get RIRB response interrupt for new entry */
481 azx_writew(chip, RINTCNT, 1);
482 /* enable rirb dma and response irq */
483 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
484 chip->rirb.rp = chip->rirb.cmds = 0;
487 static void azx_free_cmd_io(struct azx *chip)
489 /* disable ringbuffer DMAs */
490 azx_writeb(chip, RIRBCTL, 0);
491 azx_writeb(chip, CORBCTL, 0);
495 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
497 struct azx *chip = codec->bus->private_data;
500 /* add command to corb */
501 wp = azx_readb(chip, CORBWP);
503 wp %= ICH6_MAX_CORB_ENTRIES;
505 spin_lock_irq(&chip->reg_lock);
507 chip->corb.buf[wp] = cpu_to_le32(val);
508 azx_writel(chip, CORBWP, wp);
509 spin_unlock_irq(&chip->reg_lock);
514 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
516 /* retrieve RIRB entry - called from interrupt handler */
517 static void azx_update_rirb(struct azx *chip)
522 wp = azx_readb(chip, RIRBWP);
523 if (wp == chip->rirb.wp)
527 while (chip->rirb.rp != wp) {
529 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
531 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
532 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
533 res = le32_to_cpu(chip->rirb.buf[rp]);
534 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
535 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
536 else if (chip->rirb.cmds) {
538 chip->rirb.res = res;
543 /* receive a response */
544 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
546 struct azx *chip = codec->bus->private_data;
547 unsigned long timeout;
550 timeout = jiffies + msecs_to_jiffies(1000);
552 if (chip->polling_mode) {
553 spin_lock_irq(&chip->reg_lock);
554 azx_update_rirb(chip);
555 spin_unlock_irq(&chip->reg_lock);
557 if (!chip->rirb.cmds)
558 return chip->rirb.res; /* the last value */
560 } while (time_after_eq(timeout, jiffies));
563 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
564 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
565 free_irq(chip->irq, chip);
567 pci_disable_msi(chip->pci);
569 if (azx_acquire_irq(chip, 1) < 0)
574 if (!chip->polling_mode) {
575 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
576 "switching to polling mode: last cmd=0x%08x\n",
578 chip->polling_mode = 1;
582 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
583 "switching to single_cmd mode: last cmd=0x%08x\n",
585 chip->rirb.rp = azx_readb(chip, RIRBWP);
587 /* switch to single_cmd mode */
588 chip->single_cmd = 1;
589 azx_free_cmd_io(chip);
594 * Use the single immediate command instead of CORB/RIRB for simplicity
596 * Note: according to Intel, this is not preferred use. The command was
597 * intended for the BIOS only, and may get confused with unsolicited
598 * responses. So, we shouldn't use it for normal operation from the
600 * I left the codes, however, for debugging/testing purposes.
604 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
606 struct azx *chip = codec->bus->private_data;
610 /* check ICB busy bit */
611 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
612 /* Clear IRV valid bit */
613 azx_writew(chip, IRS, azx_readw(chip, IRS) |
615 azx_writel(chip, IC, val);
616 azx_writew(chip, IRS, azx_readw(chip, IRS) |
622 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
623 azx_readw(chip, IRS), val);
627 /* receive a response */
628 static unsigned int azx_single_get_response(struct hda_codec *codec)
630 struct azx *chip = codec->bus->private_data;
634 /* check IRV busy bit */
635 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
636 return azx_readl(chip, IR);
639 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
640 azx_readw(chip, IRS));
641 return (unsigned int)-1;
645 * The below are the main callbacks from hda_codec.
647 * They are just the skeleton to call sub-callbacks according to the
648 * current setting of chip->single_cmd.
652 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
653 int direct, unsigned int verb,
656 struct azx *chip = codec->bus->private_data;
659 val = (u32)(codec->addr & 0x0f) << 28;
660 val |= (u32)direct << 27;
661 val |= (u32)nid << 20;
664 chip->last_cmd = val;
666 if (chip->single_cmd)
667 return azx_single_send_cmd(codec, val);
669 return azx_corb_send_cmd(codec, val);
673 static unsigned int azx_get_response(struct hda_codec *codec)
675 struct azx *chip = codec->bus->private_data;
676 if (chip->single_cmd)
677 return azx_single_get_response(codec);
679 return azx_rirb_get_response(codec);
682 #ifdef CONFIG_SND_HDA_POWER_SAVE
683 static void azx_power_notify(struct hda_codec *codec);
686 /* reset codec link */
687 static int azx_reset(struct azx *chip)
691 /* reset controller */
692 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
695 while (azx_readb(chip, GCTL) && --count)
698 /* delay for >= 100us for codec PLL to settle per spec
699 * Rev 0.9 section 5.5.1
703 /* Bring controller out of reset */
704 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
707 while (!azx_readb(chip, GCTL) && --count)
710 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
713 /* check to see if controller is ready */
714 if (!azx_readb(chip, GCTL)) {
715 snd_printd("azx_reset: controller not ready!\n");
719 /* Accept unsolicited responses */
720 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
723 if (!chip->codec_mask) {
724 chip->codec_mask = azx_readw(chip, STATESTS);
725 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
736 /* enable interrupts */
737 static void azx_int_enable(struct azx *chip)
739 /* enable controller CIE and GIE */
740 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
741 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
744 /* disable interrupts */
745 static void azx_int_disable(struct azx *chip)
749 /* disable interrupts in stream descriptor */
750 for (i = 0; i < chip->num_streams; i++) {
751 struct azx_dev *azx_dev = &chip->azx_dev[i];
752 azx_sd_writeb(azx_dev, SD_CTL,
753 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
756 /* disable SIE for all streams */
757 azx_writeb(chip, INTCTL, 0);
759 /* disable controller CIE and GIE */
760 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
761 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
764 /* clear interrupts */
765 static void azx_int_clear(struct azx *chip)
769 /* clear stream status */
770 for (i = 0; i < chip->num_streams; i++) {
771 struct azx_dev *azx_dev = &chip->azx_dev[i];
772 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
776 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
778 /* clear rirb status */
779 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
781 /* clear int status */
782 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
786 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
789 azx_writeb(chip, INTCTL,
790 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
791 /* set DMA start and interrupt mask */
792 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
793 SD_CTL_DMA_START | SD_INT_MASK);
797 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
800 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
801 ~(SD_CTL_DMA_START | SD_INT_MASK));
802 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
804 azx_writeb(chip, INTCTL,
805 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
810 * reset and start the controller registers
812 static void azx_init_chip(struct azx *chip)
814 if (chip->initialized)
817 /* reset controller */
820 /* initialize interrupts */
822 azx_int_enable(chip);
824 /* initialize the codec command I/O */
825 if (!chip->single_cmd)
826 azx_init_cmd_io(chip);
828 /* program the position buffer */
829 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
830 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
832 chip->initialized = 1;
836 * initialize the PCI registers
838 /* update bits in a PCI register byte */
839 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
840 unsigned char mask, unsigned char val)
844 pci_read_config_byte(pci, reg, &data);
846 data |= (val & mask);
847 pci_write_config_byte(pci, reg, data);
850 static void azx_init_pci(struct azx *chip)
852 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
853 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
854 * Ensuring these bits are 0 clears playback static on some HD Audio
857 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
859 switch (chip->driver_type) {
861 /* For ATI SB450 azalia HD audio, we need to enable snoop */
862 update_pci_byte(chip->pci,
863 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
864 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
866 case AZX_DRIVER_NVIDIA:
867 /* For NVIDIA HDA, enable snoop */
868 update_pci_byte(chip->pci,
869 NVIDIA_HDA_TRANSREG_ADDR,
870 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
879 static irqreturn_t azx_interrupt(int irq, void *dev_id)
881 struct azx *chip = dev_id;
882 struct azx_dev *azx_dev;
886 spin_lock(&chip->reg_lock);
888 status = azx_readl(chip, INTSTS);
890 spin_unlock(&chip->reg_lock);
894 for (i = 0; i < chip->num_streams; i++) {
895 azx_dev = &chip->azx_dev[i];
896 if (status & azx_dev->sd_int_sta_mask) {
897 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
898 if (azx_dev->substream && azx_dev->running) {
899 azx_dev->period_intr++;
900 spin_unlock(&chip->reg_lock);
901 snd_pcm_period_elapsed(azx_dev->substream);
902 spin_lock(&chip->reg_lock);
908 status = azx_readb(chip, RIRBSTS);
909 if (status & RIRB_INT_MASK) {
910 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
911 azx_update_rirb(chip);
912 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
916 /* clear state status int */
917 if (azx_readb(chip, STATESTS) & 0x04)
918 azx_writeb(chip, STATESTS, 0x04);
920 spin_unlock(&chip->reg_lock);
929 static void azx_setup_periods(struct azx_dev *azx_dev)
931 u32 *bdl = azx_dev->bdl;
932 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
935 /* reset BDL address */
936 azx_sd_writel(azx_dev, SD_BDLPL, 0);
937 azx_sd_writel(azx_dev, SD_BDLPU, 0);
939 /* program the initial BDL entries */
940 for (idx = 0; idx < azx_dev->frags; idx++) {
941 unsigned int off = idx << 2; /* 4 dword step */
942 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
943 /* program the address field of the BDL entry */
944 bdl[off] = cpu_to_le32((u32)addr);
945 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
947 /* program the size field of the BDL entry */
948 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
950 /* program the IOC to enable interrupt when buffer completes */
951 bdl[off+3] = cpu_to_le32(0x01);
956 * set up the SD for streaming
958 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
963 /* make sure the run bit is zero for SD */
964 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
967 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
968 SD_CTL_STREAM_RESET);
971 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
974 val &= ~SD_CTL_STREAM_RESET;
975 azx_sd_writeb(azx_dev, SD_CTL, val);
979 /* waiting for hardware to report that the stream is out of reset */
980 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
984 /* program the stream_tag */
985 azx_sd_writel(azx_dev, SD_CTL,
986 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
987 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
989 /* program the length of samples in cyclic buffer */
990 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
992 /* program the stream format */
993 /* this value needs to be the same as the one programmed */
994 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
996 /* program the stream LVI (last valid index) of the BDL */
997 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
999 /* program the BDL address */
1000 /* lower BDL address */
1001 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1002 /* upper BDL address */
1003 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1005 /* enable the position buffer */
1006 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1007 azx_writel(chip, DPLBASE,
1008 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1010 /* set the interrupt enable bits in the descriptor control register */
1011 azx_sd_writel(azx_dev, SD_CTL,
1012 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1019 * Codec initialization
1022 static unsigned int azx_max_codecs[] __devinitdata = {
1023 [AZX_DRIVER_ICH] = 3,
1024 [AZX_DRIVER_ATI] = 4,
1025 [AZX_DRIVER_ATIHDMI] = 4,
1026 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1027 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1028 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1029 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1032 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1034 struct hda_bus_template bus_temp;
1035 int c, codecs, audio_codecs, err;
1037 memset(&bus_temp, 0, sizeof(bus_temp));
1038 bus_temp.private_data = chip;
1039 bus_temp.modelname = model;
1040 bus_temp.pci = chip->pci;
1041 bus_temp.ops.command = azx_send_cmd;
1042 bus_temp.ops.get_response = azx_get_response;
1043 #ifdef CONFIG_SND_HDA_POWER_SAVE
1044 bus_temp.ops.pm_notify = azx_power_notify;
1047 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1051 codecs = audio_codecs = 0;
1052 for (c = 0; c < AZX_MAX_CODECS; c++) {
1053 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1054 struct hda_codec *codec;
1055 err = snd_hda_codec_new(chip->bus, c, &codec);
1063 if (!audio_codecs) {
1064 /* probe additional slots if no codec is found */
1065 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1066 if ((chip->codec_mask & (1 << c)) & probe_mask) {
1067 err = snd_hda_codec_new(chip->bus, c, NULL);
1075 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1087 /* assign a stream for the PCM */
1088 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1091 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1092 dev = chip->playback_index_offset;
1093 nums = chip->playback_streams;
1095 dev = chip->capture_index_offset;
1096 nums = chip->capture_streams;
1098 for (i = 0; i < nums; i++, dev++)
1099 if (!chip->azx_dev[dev].opened) {
1100 chip->azx_dev[dev].opened = 1;
1101 return &chip->azx_dev[dev];
1106 /* release the assigned stream */
1107 static inline void azx_release_device(struct azx_dev *azx_dev)
1109 azx_dev->opened = 0;
1112 static struct snd_pcm_hardware azx_pcm_hw = {
1113 .info = (SNDRV_PCM_INFO_MMAP |
1114 SNDRV_PCM_INFO_INTERLEAVED |
1115 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1116 SNDRV_PCM_INFO_MMAP_VALID |
1117 /* No full-resume yet implemented */
1118 /* SNDRV_PCM_INFO_RESUME |*/
1119 SNDRV_PCM_INFO_PAUSE),
1120 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1121 .rates = SNDRV_PCM_RATE_48000,
1126 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1127 .period_bytes_min = 128,
1128 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1130 .periods_max = AZX_MAX_FRAG,
1136 struct hda_codec *codec;
1137 struct hda_pcm_stream *hinfo[2];
1140 static int azx_pcm_open(struct snd_pcm_substream *substream)
1142 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1143 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1144 struct azx *chip = apcm->chip;
1145 struct azx_dev *azx_dev;
1146 struct snd_pcm_runtime *runtime = substream->runtime;
1147 unsigned long flags;
1150 mutex_lock(&chip->open_mutex);
1151 azx_dev = azx_assign_device(chip, substream->stream);
1152 if (azx_dev == NULL) {
1153 mutex_unlock(&chip->open_mutex);
1156 runtime->hw = azx_pcm_hw;
1157 runtime->hw.channels_min = hinfo->channels_min;
1158 runtime->hw.channels_max = hinfo->channels_max;
1159 runtime->hw.formats = hinfo->formats;
1160 runtime->hw.rates = hinfo->rates;
1161 snd_pcm_limit_hw_rates(runtime);
1162 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1163 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1165 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1167 snd_hda_power_up(apcm->codec);
1168 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1170 azx_release_device(azx_dev);
1171 snd_hda_power_down(apcm->codec);
1172 mutex_unlock(&chip->open_mutex);
1175 spin_lock_irqsave(&chip->reg_lock, flags);
1176 azx_dev->substream = substream;
1177 azx_dev->running = 0;
1178 spin_unlock_irqrestore(&chip->reg_lock, flags);
1180 runtime->private_data = azx_dev;
1181 mutex_unlock(&chip->open_mutex);
1185 static int azx_pcm_close(struct snd_pcm_substream *substream)
1187 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1188 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1189 struct azx *chip = apcm->chip;
1190 struct azx_dev *azx_dev = get_azx_dev(substream);
1191 unsigned long flags;
1193 mutex_lock(&chip->open_mutex);
1194 spin_lock_irqsave(&chip->reg_lock, flags);
1195 azx_dev->substream = NULL;
1196 azx_dev->running = 0;
1197 spin_unlock_irqrestore(&chip->reg_lock, flags);
1198 azx_release_device(azx_dev);
1199 hinfo->ops.close(hinfo, apcm->codec, substream);
1200 snd_hda_power_down(apcm->codec);
1201 mutex_unlock(&chip->open_mutex);
1205 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1206 struct snd_pcm_hw_params *hw_params)
1208 return snd_pcm_lib_malloc_pages(substream,
1209 params_buffer_bytes(hw_params));
1212 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1214 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1215 struct azx_dev *azx_dev = get_azx_dev(substream);
1216 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1218 /* reset BDL address */
1219 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1220 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1221 azx_sd_writel(azx_dev, SD_CTL, 0);
1223 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1225 return snd_pcm_lib_free_pages(substream);
1228 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1230 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1231 struct azx *chip = apcm->chip;
1232 struct azx_dev *azx_dev = get_azx_dev(substream);
1233 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1234 struct snd_pcm_runtime *runtime = substream->runtime;
1236 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1237 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1238 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1239 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1243 if (!azx_dev->format_val) {
1244 snd_printk(KERN_ERR SFX
1245 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1246 runtime->rate, runtime->channels, runtime->format);
1250 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1252 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1253 azx_setup_periods(azx_dev);
1254 azx_setup_controller(chip, azx_dev);
1255 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1256 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1258 azx_dev->fifo_size = 0;
1260 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1261 azx_dev->format_val, substream);
1264 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1266 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1267 struct azx_dev *azx_dev = get_azx_dev(substream);
1268 struct azx *chip = apcm->chip;
1271 spin_lock(&chip->reg_lock);
1273 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1274 case SNDRV_PCM_TRIGGER_RESUME:
1275 case SNDRV_PCM_TRIGGER_START:
1276 azx_stream_start(chip, azx_dev);
1277 azx_dev->running = 1;
1279 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1280 case SNDRV_PCM_TRIGGER_SUSPEND:
1281 case SNDRV_PCM_TRIGGER_STOP:
1282 azx_stream_stop(chip, azx_dev);
1283 azx_dev->running = 0;
1288 spin_unlock(&chip->reg_lock);
1289 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1290 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1291 cmd == SNDRV_PCM_TRIGGER_STOP) {
1293 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1300 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1302 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1303 struct azx *chip = apcm->chip;
1304 struct azx_dev *azx_dev = get_azx_dev(substream);
1307 if (chip->position_fix == POS_FIX_POSBUF ||
1308 chip->position_fix == POS_FIX_AUTO) {
1309 /* use the position buffer */
1310 pos = le32_to_cpu(*azx_dev->posbuf);
1311 if (chip->position_fix == POS_FIX_AUTO &&
1312 azx_dev->period_intr == 1 && !pos) {
1314 "hda-intel: Invalid position buffer, "
1315 "using LPIB read method instead.\n");
1316 chip->position_fix = POS_FIX_NONE;
1322 pos = azx_sd_readl(azx_dev, SD_LPIB);
1323 if (chip->position_fix == POS_FIX_FIFO)
1324 pos += azx_dev->fifo_size;
1326 if (pos >= azx_dev->bufsize)
1328 return bytes_to_frames(substream->runtime, pos);
1331 static struct snd_pcm_ops azx_pcm_ops = {
1332 .open = azx_pcm_open,
1333 .close = azx_pcm_close,
1334 .ioctl = snd_pcm_lib_ioctl,
1335 .hw_params = azx_pcm_hw_params,
1336 .hw_free = azx_pcm_hw_free,
1337 .prepare = azx_pcm_prepare,
1338 .trigger = azx_pcm_trigger,
1339 .pointer = azx_pcm_pointer,
1342 static void azx_pcm_free(struct snd_pcm *pcm)
1344 kfree(pcm->private_data);
1347 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1348 struct hda_pcm *cpcm, int pcm_dev)
1351 struct snd_pcm *pcm;
1352 struct azx_pcm *apcm;
1354 /* if no substreams are defined for both playback and capture,
1355 * it's just a placeholder. ignore it.
1357 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1360 snd_assert(cpcm->name, return -EINVAL);
1362 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1363 cpcm->stream[0].substreams,
1364 cpcm->stream[1].substreams,
1368 strcpy(pcm->name, cpcm->name);
1369 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1373 apcm->codec = codec;
1374 apcm->hinfo[0] = &cpcm->stream[0];
1375 apcm->hinfo[1] = &cpcm->stream[1];
1376 pcm->private_data = apcm;
1377 pcm->private_free = azx_pcm_free;
1378 if (cpcm->stream[0].substreams)
1379 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1380 if (cpcm->stream[1].substreams)
1381 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1382 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1383 snd_dma_pci_data(chip->pci),
1384 1024 * 64, 1024 * 1024);
1385 chip->pcm[pcm_dev] = pcm;
1386 if (chip->pcm_devs < pcm_dev + 1)
1387 chip->pcm_devs = pcm_dev + 1;
1392 static int __devinit azx_pcm_create(struct azx *chip)
1394 struct list_head *p;
1395 struct hda_codec *codec;
1399 err = snd_hda_build_pcms(chip->bus);
1403 /* create audio PCMs */
1405 list_for_each(p, &chip->bus->codec_list) {
1406 codec = list_entry(p, struct hda_codec, list);
1407 for (c = 0; c < codec->num_pcms; c++) {
1408 if (codec->pcm_info[c].is_modem)
1409 continue; /* create later */
1410 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1411 snd_printk(KERN_ERR SFX
1412 "Too many audio PCMs\n");
1415 err = create_codec_pcm(chip, codec,
1416 &codec->pcm_info[c], pcm_dev);
1423 /* create modem PCMs */
1424 pcm_dev = AZX_MAX_AUDIO_PCMS;
1425 list_for_each(p, &chip->bus->codec_list) {
1426 codec = list_entry(p, struct hda_codec, list);
1427 for (c = 0; c < codec->num_pcms; c++) {
1428 if (!codec->pcm_info[c].is_modem)
1429 continue; /* already created */
1430 if (pcm_dev >= AZX_MAX_PCMS) {
1431 snd_printk(KERN_ERR SFX
1432 "Too many modem PCMs\n");
1435 err = create_codec_pcm(chip, codec,
1436 &codec->pcm_info[c], pcm_dev);
1439 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1447 * mixer creation - all stuff is implemented in hda module
1449 static int __devinit azx_mixer_create(struct azx *chip)
1451 return snd_hda_build_controls(chip->bus);
1456 * initialize SD streams
1458 static int __devinit azx_init_stream(struct azx *chip)
1462 /* initialize each stream (aka device)
1463 * assign the starting bdl address to each stream (device)
1466 for (i = 0; i < chip->num_streams; i++) {
1467 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1468 struct azx_dev *azx_dev = &chip->azx_dev[i];
1469 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1470 azx_dev->bdl_addr = chip->bdl.addr + off;
1471 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1472 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1473 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1474 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1475 azx_dev->sd_int_sta_mask = 1 << i;
1476 /* stream tag: must be non-zero and unique */
1478 azx_dev->stream_tag = i + 1;
1484 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1486 if (request_irq(chip->pci->irq, azx_interrupt,
1487 chip->msi ? 0 : IRQF_SHARED,
1488 "HDA Intel", chip)) {
1489 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1490 "disabling device\n", chip->pci->irq);
1492 snd_card_disconnect(chip->card);
1495 chip->irq = chip->pci->irq;
1496 pci_intx(chip->pci, !chip->msi);
1501 static void azx_stop_chip(struct azx *chip)
1503 if (chip->initialized)
1506 /* disable interrupts */
1507 azx_int_disable(chip);
1508 azx_int_clear(chip);
1510 /* disable CORB/RIRB */
1511 azx_free_cmd_io(chip);
1513 /* disable position buffer */
1514 azx_writel(chip, DPLBASE, 0);
1515 azx_writel(chip, DPUBASE, 0);
1517 chip->initialized = 0;
1520 #ifdef CONFIG_SND_HDA_POWER_SAVE
1521 /* power-up/down the controller */
1522 static void azx_power_notify(struct hda_codec *codec)
1524 struct azx *chip = codec->bus->private_data;
1525 struct hda_codec *c;
1528 list_for_each_entry(c, &codec->bus->codec_list, list) {
1535 azx_init_chip(chip);
1536 #ifdef HDA_POWER_SAVE_RESET_CONTROLLER
1537 else if (chip->running)
1538 azx_stop_chip(chip);
1541 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1547 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1549 struct snd_card *card = pci_get_drvdata(pci);
1550 struct azx *chip = card->private_data;
1553 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1554 for (i = 0; i < chip->pcm_devs; i++)
1555 snd_pcm_suspend_all(chip->pcm[i]);
1556 snd_hda_suspend(chip->bus, state);
1557 azx_stop_chip(chip);
1558 if (chip->irq >= 0) {
1559 synchronize_irq(chip->irq);
1560 free_irq(chip->irq, chip);
1564 pci_disable_msi(chip->pci);
1565 pci_disable_device(pci);
1566 pci_save_state(pci);
1567 pci_set_power_state(pci, pci_choose_state(pci, state));
1571 static int azx_resume(struct pci_dev *pci)
1573 struct snd_card *card = pci_get_drvdata(pci);
1574 struct azx *chip = card->private_data;
1576 pci_set_power_state(pci, PCI_D0);
1577 pci_restore_state(pci);
1578 if (pci_enable_device(pci) < 0) {
1579 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1580 "disabling device\n");
1581 snd_card_disconnect(card);
1584 pci_set_master(pci);
1586 if (pci_enable_msi(pci) < 0)
1588 if (azx_acquire_irq(chip, 1) < 0)
1591 #ifndef CONFIG_SND_HDA_POWER_SAVE
1592 /* the explicit resume is needed only when POWER_SAVE isn't set */
1593 azx_init_chip(chip);
1594 snd_hda_resume(chip->bus);
1596 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1599 #endif /* CONFIG_PM */
1605 static int azx_free(struct azx *chip)
1607 if (chip->initialized) {
1609 for (i = 0; i < chip->num_streams; i++)
1610 azx_stream_stop(chip, &chip->azx_dev[i]);
1611 azx_stop_chip(chip);
1614 if (chip->irq >= 0) {
1615 synchronize_irq(chip->irq);
1616 free_irq(chip->irq, (void*)chip);
1619 pci_disable_msi(chip->pci);
1620 if (chip->remap_addr)
1621 iounmap(chip->remap_addr);
1624 snd_dma_free_pages(&chip->bdl);
1626 snd_dma_free_pages(&chip->rb);
1627 if (chip->posbuf.area)
1628 snd_dma_free_pages(&chip->posbuf);
1629 pci_release_regions(chip->pci);
1630 pci_disable_device(chip->pci);
1631 kfree(chip->azx_dev);
1637 static int azx_dev_free(struct snd_device *device)
1639 return azx_free(device->device_data);
1643 * white/black-listing for position_fix
1645 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1646 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1650 static int __devinit check_position_fix(struct azx *chip, int fix)
1652 const struct snd_pci_quirk *q;
1654 if (fix == POS_FIX_AUTO) {
1655 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1657 snd_printdd(KERN_INFO
1658 "hda_intel: position_fix set to %d "
1659 "for device %04x:%04x\n",
1660 q->value, q->subvendor, q->subdevice);
1670 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1676 static struct snd_device_ops ops = {
1677 .dev_free = azx_dev_free,
1682 err = pci_enable_device(pci);
1686 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1688 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1689 pci_disable_device(pci);
1693 spin_lock_init(&chip->reg_lock);
1694 mutex_init(&chip->open_mutex);
1698 chip->driver_type = driver_type;
1699 chip->msi = enable_msi;
1701 chip->position_fix = check_position_fix(chip, position_fix);
1703 chip->single_cmd = single_cmd;
1705 #if BITS_PER_LONG != 64
1706 /* Fix up base address on ULI M5461 */
1707 if (chip->driver_type == AZX_DRIVER_ULI) {
1709 pci_read_config_word(pci, 0x40, &tmp3);
1710 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1711 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1715 err = pci_request_regions(pci, "ICH HD audio");
1718 pci_disable_device(pci);
1722 chip->addr = pci_resource_start(pci, 0);
1723 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1724 if (chip->remap_addr == NULL) {
1725 snd_printk(KERN_ERR SFX "ioremap error\n");
1731 if (pci_enable_msi(pci) < 0)
1734 if (azx_acquire_irq(chip, 0) < 0) {
1739 pci_set_master(pci);
1740 synchronize_irq(chip->irq);
1742 switch (chip->driver_type) {
1743 case AZX_DRIVER_ULI:
1744 chip->playback_streams = ULI_NUM_PLAYBACK;
1745 chip->capture_streams = ULI_NUM_CAPTURE;
1746 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1747 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1749 case AZX_DRIVER_ATIHDMI:
1750 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1751 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1752 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1753 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1756 chip->playback_streams = ICH6_NUM_PLAYBACK;
1757 chip->capture_streams = ICH6_NUM_CAPTURE;
1758 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1759 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1762 chip->num_streams = chip->playback_streams + chip->capture_streams;
1763 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1765 if (!chip->azx_dev) {
1766 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1770 /* allocate memory for the BDL for each stream */
1771 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1772 snd_dma_pci_data(chip->pci),
1773 BDL_SIZE, &chip->bdl);
1775 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1778 /* allocate memory for the position buffer */
1779 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1780 snd_dma_pci_data(chip->pci),
1781 chip->num_streams * 8, &chip->posbuf);
1783 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1786 /* allocate CORB/RIRB */
1787 if (!chip->single_cmd) {
1788 err = azx_alloc_cmd_io(chip);
1793 /* initialize streams */
1794 azx_init_stream(chip);
1796 /* initialize chip */
1798 azx_init_chip(chip);
1800 /* codec detection */
1801 if (!chip->codec_mask) {
1802 snd_printk(KERN_ERR SFX "no codecs found!\n");
1807 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1809 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1813 strcpy(card->driver, "HDA-Intel");
1814 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1815 sprintf(card->longname, "%s at 0x%lx irq %i",
1816 card->shortname, chip->addr, chip->irq);
1826 static void power_down_all_codecs(struct azx *chip)
1828 #ifdef CONFIG_SND_HDA_POWER_SAVE
1829 /* The codecs were powered up in snd_hda_codec_new().
1830 * Now all initialization done, so turn them down if possible
1832 struct hda_codec *codec;
1833 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1834 snd_hda_power_down(codec);
1839 static int __devinit azx_probe(struct pci_dev *pci,
1840 const struct pci_device_id *pci_id)
1842 struct snd_card *card;
1846 card = snd_card_new(index, id, THIS_MODULE, 0);
1848 snd_printk(KERN_ERR SFX "Error creating card!\n");
1852 err = azx_create(card, pci, pci_id->driver_data, &chip);
1854 snd_card_free(card);
1857 card->private_data = chip;
1859 /* create codec instances */
1860 err = azx_codec_create(chip, model);
1862 snd_card_free(card);
1866 /* create PCM streams */
1867 err = azx_pcm_create(chip);
1869 snd_card_free(card);
1873 /* create mixer controls */
1874 err = azx_mixer_create(chip);
1876 snd_card_free(card);
1880 snd_card_set_dev(card, &pci->dev);
1882 err = snd_card_register(card);
1884 snd_card_free(card);
1888 pci_set_drvdata(pci, card);
1890 power_down_all_codecs(chip);
1895 static void __devexit azx_remove(struct pci_dev *pci)
1897 snd_card_free(pci_get_drvdata(pci));
1898 pci_set_drvdata(pci, NULL);
1902 static struct pci_device_id azx_ids[] = {
1903 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1904 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1905 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
1906 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
1907 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1908 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
1909 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
1910 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
1911 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
1912 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
1913 { 0x1002, 0x960c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
1914 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
1915 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
1916 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
1917 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
1918 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
1919 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
1920 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1921 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
1922 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1923 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
1924 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1925 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
1926 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1927 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
1928 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1929 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1930 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1931 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
1934 MODULE_DEVICE_TABLE(pci, azx_ids);
1936 /* pci_driver definition */
1937 static struct pci_driver driver = {
1938 .name = "HDA Intel",
1939 .id_table = azx_ids,
1941 .remove = __devexit_p(azx_remove),
1943 .suspend = azx_suspend,
1944 .resume = azx_resume,
1948 static int __init alsa_card_azx_init(void)
1950 return pci_register_driver(&driver);
1953 static void __exit alsa_card_azx_exit(void)
1955 pci_unregister_driver(&driver);
1958 module_init(alsa_card_azx_init)
1959 module_exit(alsa_card_azx_exit)