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1 /*
2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
3  *
4  * Copyright 2008 Wolfson Microelectronics PLC.
5  *
6  *  This program is free software; you can redistribute  it and/or modify it
7  *  under  the terms of  the GNU General  Public License as published by the
8  *  Free Software Foundation;  either version 2 of the  License, or (at your
9  *  option) any later version.
10  *
11  * Notes:
12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
13  *  DAC channels and two ADC channels.
14  *
15  *  Currently only the primary audio interface is supported - S/PDIF and
16  *  the secondary audio interfaces are not.
17  */
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/pm.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/soc-dapm.h>
32 #include <sound/tlv.h>
33 #include <sound/initval.h>
34 #include <asm/div64.h>
35
36 #include "wm8580.h"
37
38 struct pll_state {
39         unsigned int in;
40         unsigned int out;
41 };
42
43 /* codec private data */
44 struct wm8580_priv {
45         struct pll_state a;
46         struct pll_state b;
47 };
48
49 /* WM8580 register space */
50 #define WM8580_PLLA1                         0x00
51 #define WM8580_PLLA2                         0x01
52 #define WM8580_PLLA3                         0x02
53 #define WM8580_PLLA4                         0x03
54 #define WM8580_PLLB1                         0x04
55 #define WM8580_PLLB2                         0x05
56 #define WM8580_PLLB3                         0x06
57 #define WM8580_PLLB4                         0x07
58 #define WM8580_CLKSEL                        0x08
59 #define WM8580_PAIF1                         0x09
60 #define WM8580_PAIF2                         0x0A
61 #define WM8580_SAIF1                         0x0B
62 #define WM8580_PAIF3                         0x0C
63 #define WM8580_PAIF4                         0x0D
64 #define WM8580_SAIF2                         0x0E
65 #define WM8580_DAC_CONTROL1                  0x0F
66 #define WM8580_DAC_CONTROL2                  0x10
67 #define WM8580_DAC_CONTROL3                  0x11
68 #define WM8580_DAC_CONTROL4                  0x12
69 #define WM8580_DAC_CONTROL5                  0x13
70 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
71 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
72 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
73 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
74 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
75 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
76 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
77 #define WM8580_ADC_CONTROL1                  0x1D
78 #define WM8580_SPDTXCHAN0                    0x1E
79 #define WM8580_SPDTXCHAN1                    0x1F
80 #define WM8580_SPDTXCHAN2                    0x20
81 #define WM8580_SPDTXCHAN3                    0x21
82 #define WM8580_SPDTXCHAN4                    0x22
83 #define WM8580_SPDTXCHAN5                    0x23
84 #define WM8580_SPDMODE                       0x24
85 #define WM8580_INTMASK                       0x25
86 #define WM8580_GPO1                          0x26
87 #define WM8580_GPO2                          0x27
88 #define WM8580_GPO3                          0x28
89 #define WM8580_GPO4                          0x29
90 #define WM8580_GPO5                          0x2A
91 #define WM8580_INTSTAT                       0x2B
92 #define WM8580_SPDRXCHAN1                    0x2C
93 #define WM8580_SPDRXCHAN2                    0x2D
94 #define WM8580_SPDRXCHAN3                    0x2E
95 #define WM8580_SPDRXCHAN4                    0x2F
96 #define WM8580_SPDRXCHAN5                    0x30
97 #define WM8580_SPDSTAT                       0x31
98 #define WM8580_PWRDN1                        0x32
99 #define WM8580_PWRDN2                        0x33
100 #define WM8580_READBACK                      0x34
101 #define WM8580_RESET                         0x35
102
103 /* PLLB4 (register 7h) */
104 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
105 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
106 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
107 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
108
109 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
110 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
111 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
112 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
113
114 /* CLKSEL (register 8h) */
115 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
116 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
117 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
118
119 /* AIF control 1 (registers 9h-bh) */
120 #define WM8580_AIF_RATE_MASK       0x7
121 #define WM8580_AIF_RATE_128        0x0
122 #define WM8580_AIF_RATE_192        0x1
123 #define WM8580_AIF_RATE_256        0x2
124 #define WM8580_AIF_RATE_384        0x3
125 #define WM8580_AIF_RATE_512        0x4
126 #define WM8580_AIF_RATE_768        0x5
127 #define WM8580_AIF_RATE_1152       0x6
128
129 #define WM8580_AIF_BCLKSEL_MASK   0x18
130 #define WM8580_AIF_BCLKSEL_64     0x00
131 #define WM8580_AIF_BCLKSEL_128    0x08
132 #define WM8580_AIF_BCLKSEL_256    0x10
133 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
134
135 #define WM8580_AIF_MS             0x20
136
137 #define WM8580_AIF_CLKSRC_MASK    0xc0
138 #define WM8580_AIF_CLKSRC_PLLA    0x40
139 #define WM8580_AIF_CLKSRC_PLLB    0x40
140 #define WM8580_AIF_CLKSRC_MCLK    0xc0
141
142 /* AIF control 2 (registers ch-eh) */
143 #define WM8580_AIF_FMT_MASK    0x03
144 #define WM8580_AIF_FMT_RIGHTJ  0x00
145 #define WM8580_AIF_FMT_LEFTJ   0x01
146 #define WM8580_AIF_FMT_I2S     0x02
147 #define WM8580_AIF_FMT_DSP     0x03
148
149 #define WM8580_AIF_LENGTH_MASK   0x0c
150 #define WM8580_AIF_LENGTH_16     0x00
151 #define WM8580_AIF_LENGTH_20     0x04
152 #define WM8580_AIF_LENGTH_24     0x08
153 #define WM8580_AIF_LENGTH_32     0x0c
154
155 #define WM8580_AIF_LRP         0x10
156 #define WM8580_AIF_BCP         0x20
157
158 /* Powerdown Register 1 (register 32h) */
159 #define WM8580_PWRDN1_PWDN     0x001
160 #define WM8580_PWRDN1_ALLDACPD 0x040
161
162 /* Powerdown Register 2 (register 33h) */
163 #define WM8580_PWRDN2_OSSCPD   0x001
164 #define WM8580_PWRDN2_PLLAPD   0x002
165 #define WM8580_PWRDN2_PLLBPD   0x004
166 #define WM8580_PWRDN2_SPDIFPD  0x008
167 #define WM8580_PWRDN2_SPDIFTXD 0x010
168 #define WM8580_PWRDN2_SPDIFRXD 0x020
169
170 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
171
172 /*
173  * wm8580 register cache
174  * We can't read the WM8580 register space when we
175  * are using 2 wire for device control, so we cache them instead.
176  */
177 static const u16 wm8580_reg[] = {
178         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
179         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
180         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
181         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
182         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
183         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
184         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
185         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
186         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
187         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
188         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
189         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
190         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
191         0x0000, 0x0000 /*R53*/
192 };
193
194 /*
195  * read wm8580 register cache
196  */
197 static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
198         unsigned int reg)
199 {
200         u16 *cache = codec->reg_cache;
201         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
202         return cache[reg];
203 }
204
205 /*
206  * write wm8580 register cache
207  */
208 static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
209         unsigned int reg, unsigned int value)
210 {
211         u16 *cache = codec->reg_cache;
212
213         cache[reg] = value;
214 }
215
216 /*
217  * write to the WM8580 register space
218  */
219 static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
220         unsigned int value)
221 {
222         u8 data[2];
223
224         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
225
226         /* Registers are 9 bits wide */
227         value &= 0x1ff;
228
229         switch (reg) {
230         case WM8580_RESET:
231                 /* Uncached */
232                 break;
233         default:
234                 if (value == wm8580_read_reg_cache(codec, reg))
235                         return 0;
236         }
237
238         /* data is
239          *   D15..D9 WM8580 register offset
240          *   D8...D0 register data
241          */
242         data[0] = (reg << 1) | ((value >> 8) & 0x0001);
243         data[1] = value & 0x00ff;
244
245         wm8580_write_reg_cache(codec, reg, value);
246         if (codec->hw_write(codec->control_data, data, 2) == 2)
247                 return 0;
248         else
249                 return -EIO;
250 }
251
252 static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
253                                        unsigned int reg)
254 {
255         switch (reg) {
256         default:
257                 return wm8580_read_reg_cache(codec, reg);
258         }
259 }
260
261 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
262
263 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
264                          struct snd_ctl_elem_value *ucontrol)
265 {
266         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
267         int reg = kcontrol->private_value & 0xff;
268         int reg2 = (kcontrol->private_value >> 24) & 0xff;
269         int ret;
270         u16 val;
271
272         /* Clear the register cache so we write without VU set */
273         wm8580_write_reg_cache(codec, reg, 0);
274         wm8580_write_reg_cache(codec, reg2, 0);
275
276         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
277         if (ret < 0)
278                 return ret;
279
280         /* Now write again with the volume update bit set */
281         val = wm8580_read_reg_cache(codec, reg);
282         wm8580_write(codec, reg, val | 0x0100);
283
284         val = wm8580_read_reg_cache(codec, reg2);
285         wm8580_write(codec, reg2, val | 0x0100);
286
287         return 0;
288 }
289
290 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \
291 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
292         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
293                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
294         .tlv.p = (tlv_array), \
295         .info = snd_soc_info_volsw_2r, \
296         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
297         .private_value = (reg_left) | ((shift) << 8)  |         \
298                 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
299
300 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
301 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
302                             WM8580_DIGITAL_ATTENUATION_DACL1,
303                             WM8580_DIGITAL_ATTENUATION_DACR1,
304                             0, 0xff, 0, dac_tlv),
305 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
306                             WM8580_DIGITAL_ATTENUATION_DACL2,
307                             WM8580_DIGITAL_ATTENUATION_DACR2,
308                             0, 0xff, 0, dac_tlv),
309 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
310                             WM8580_DIGITAL_ATTENUATION_DACL3,
311                             WM8580_DIGITAL_ATTENUATION_DACR3,
312                             0, 0xff, 0, dac_tlv),
313
314 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
315 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
316 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
317
318 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
319 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
320 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
321
322 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
323 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
324 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
325 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
326
327 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
328 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
329 };
330
331 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
332 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
333 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
334 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
335
336 SND_SOC_DAPM_OUTPUT("VOUT1L"),
337 SND_SOC_DAPM_OUTPUT("VOUT1R"),
338 SND_SOC_DAPM_OUTPUT("VOUT2L"),
339 SND_SOC_DAPM_OUTPUT("VOUT2R"),
340 SND_SOC_DAPM_OUTPUT("VOUT3L"),
341 SND_SOC_DAPM_OUTPUT("VOUT3R"),
342
343 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
344
345 SND_SOC_DAPM_INPUT("AINL"),
346 SND_SOC_DAPM_INPUT("AINR"),
347 };
348
349 static const struct snd_soc_dapm_route audio_map[] = {
350         { "VOUT1L", NULL, "DAC1" },
351         { "VOUT1R", NULL, "DAC1" },
352
353         { "VOUT2L", NULL, "DAC2" },
354         { "VOUT2R", NULL, "DAC2" },
355
356         { "VOUT3L", NULL, "DAC3" },
357         { "VOUT3R", NULL, "DAC3" },
358
359         { "ADC", NULL, "AINL" },
360         { "ADC", NULL, "AINR" },
361 };
362
363 static int wm8580_add_widgets(struct snd_soc_codec *codec)
364 {
365         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
366                                   ARRAY_SIZE(wm8580_dapm_widgets));
367
368         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
369
370         snd_soc_dapm_new_widgets(codec);
371         return 0;
372 }
373
374 /* PLL divisors */
375 struct _pll_div {
376         u32 prescale:1;
377         u32 postscale:1;
378         u32 freqmode:2;
379         u32 n:4;
380         u32 k:24;
381 };
382
383 /* The size in bits of the pll divide */
384 #define FIXED_PLL_SIZE (1 << 22)
385
386 /* PLL rate to output rate divisions */
387 static struct {
388         unsigned int div;
389         unsigned int freqmode;
390         unsigned int postscale;
391 } post_table[] = {
392         {  2,  0, 0 },
393         {  4,  0, 1 },
394         {  4,  1, 0 },
395         {  8,  1, 1 },
396         {  8,  2, 0 },
397         { 16,  2, 1 },
398         { 12,  3, 0 },
399         { 24,  3, 1 }
400 };
401
402 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
403                        unsigned int source)
404 {
405         u64 Kpart;
406         unsigned int K, Ndiv, Nmod;
407         int i;
408
409         pr_debug("wm8580: PLL %dHz->%dHz\n", source, target);
410
411         /* Scale the output frequency up; the PLL should run in the
412          * region of 90-100MHz.
413          */
414         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
415                 if (target * post_table[i].div >=  90000000 &&
416                     target * post_table[i].div <= 100000000) {
417                         pll_div->freqmode = post_table[i].freqmode;
418                         pll_div->postscale = post_table[i].postscale;
419                         target *= post_table[i].div;
420                         break;
421                 }
422         }
423
424         if (i == ARRAY_SIZE(post_table)) {
425                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
426                        "%u\n", target);
427                 return -EINVAL;
428         }
429
430         Ndiv = target / source;
431
432         if (Ndiv < 5) {
433                 source /= 2;
434                 pll_div->prescale = 1;
435                 Ndiv = target / source;
436         } else
437                 pll_div->prescale = 0;
438
439         if ((Ndiv < 5) || (Ndiv > 13)) {
440                 printk(KERN_ERR
441                         "WM8580 N=%d outside supported range\n", Ndiv);
442                 return -EINVAL;
443         }
444
445         pll_div->n = Ndiv;
446         Nmod = target % source;
447         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
448
449         do_div(Kpart, source);
450
451         K = Kpart & 0xFFFFFFFF;
452
453         pll_div->k = K;
454
455         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
456                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
457                  pll_div->postscale);
458
459         return 0;
460 }
461
462 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai,
463                 int pll_id, unsigned int freq_in, unsigned int freq_out)
464 {
465         int offset;
466         struct snd_soc_codec *codec = codec_dai->codec;
467         struct wm8580_priv *wm8580 = codec->private_data;
468         struct pll_state *state;
469         struct _pll_div pll_div;
470         unsigned int reg;
471         unsigned int pwr_mask;
472         int ret;
473
474         /* GCC isn't able to work out the ifs below for initialising/using
475          * pll_div so suppress warnings.
476          */
477         memset(&pll_div, 0, sizeof(pll_div));
478
479         switch (pll_id) {
480         case WM8580_PLLA:
481                 state = &wm8580->a;
482                 offset = 0;
483                 pwr_mask = WM8580_PWRDN2_PLLAPD;
484                 break;
485         case WM8580_PLLB:
486                 state = &wm8580->b;
487                 offset = 4;
488                 pwr_mask = WM8580_PWRDN2_PLLBPD;
489                 break;
490         default:
491                 return -ENODEV;
492         }
493
494         if (freq_in && freq_out) {
495                 ret = pll_factors(&pll_div, freq_out, freq_in);
496                 if (ret != 0)
497                         return ret;
498         }
499
500         state->in = freq_in;
501         state->out = freq_out;
502
503         /* Always disable the PLL - it is not safe to leave it running
504          * while reprogramming it.
505          */
506         reg = wm8580_read(codec, WM8580_PWRDN2);
507         wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask);
508
509         if (!freq_in || !freq_out)
510                 return 0;
511
512         wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
513         wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
514         wm8580_write(codec, WM8580_PLLA3 + offset,
515                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
516
517         reg = wm8580_read(codec, WM8580_PLLA4 + offset);
518         reg &= ~0x3f;
519         reg |= pll_div.prescale | pll_div.postscale << 1 |
520                 pll_div.freqmode << 4;
521
522         wm8580_write(codec, WM8580_PLLA4 + offset, reg);
523
524         /* All done, turn it on */
525         reg = wm8580_read(codec, WM8580_PWRDN2);
526         wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
527
528         return 0;
529 }
530
531 /*
532  * Set PCM DAI bit size and sample rate.
533  */
534 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
535                                  struct snd_pcm_hw_params *params,
536                                  struct snd_soc_dai *dai)
537 {
538         struct snd_soc_pcm_runtime *rtd = substream->private_data;
539         struct snd_soc_device *socdev = rtd->socdev;
540         struct snd_soc_codec *codec = socdev->card->codec;
541         u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->id);
542
543         paifb &= ~WM8580_AIF_LENGTH_MASK;
544         /* bit size */
545         switch (params_format(params)) {
546         case SNDRV_PCM_FORMAT_S16_LE:
547                 break;
548         case SNDRV_PCM_FORMAT_S20_3LE:
549                 paifb |= WM8580_AIF_LENGTH_20;
550                 break;
551         case SNDRV_PCM_FORMAT_S24_LE:
552                 paifb |= WM8580_AIF_LENGTH_24;
553                 break;
554         case SNDRV_PCM_FORMAT_S32_LE:
555                 paifb |= WM8580_AIF_LENGTH_24;
556                 break;
557         default:
558                 return -EINVAL;
559         }
560
561         wm8580_write(codec, WM8580_PAIF3 + dai->id, paifb);
562         return 0;
563 }
564
565 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
566                                       unsigned int fmt)
567 {
568         struct snd_soc_codec *codec = codec_dai->codec;
569         unsigned int aifa;
570         unsigned int aifb;
571         int can_invert_lrclk;
572
573         aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id);
574         aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id);
575
576         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
577
578         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
579         case SND_SOC_DAIFMT_CBS_CFS:
580                 aifa &= ~WM8580_AIF_MS;
581                 break;
582         case SND_SOC_DAIFMT_CBM_CFM:
583                 aifa |= WM8580_AIF_MS;
584                 break;
585         default:
586                 return -EINVAL;
587         }
588
589         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
590         case SND_SOC_DAIFMT_I2S:
591                 can_invert_lrclk = 1;
592                 aifb |= WM8580_AIF_FMT_I2S;
593                 break;
594         case SND_SOC_DAIFMT_RIGHT_J:
595                 can_invert_lrclk = 1;
596                 aifb |= WM8580_AIF_FMT_RIGHTJ;
597                 break;
598         case SND_SOC_DAIFMT_LEFT_J:
599                 can_invert_lrclk = 1;
600                 aifb |= WM8580_AIF_FMT_LEFTJ;
601                 break;
602         case SND_SOC_DAIFMT_DSP_A:
603                 can_invert_lrclk = 0;
604                 aifb |= WM8580_AIF_FMT_DSP;
605                 break;
606         case SND_SOC_DAIFMT_DSP_B:
607                 can_invert_lrclk = 0;
608                 aifb |= WM8580_AIF_FMT_DSP;
609                 aifb |= WM8580_AIF_LRP;
610                 break;
611         default:
612                 return -EINVAL;
613         }
614
615         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
616         case SND_SOC_DAIFMT_NB_NF:
617                 break;
618
619         case SND_SOC_DAIFMT_IB_IF:
620                 if (!can_invert_lrclk)
621                         return -EINVAL;
622                 aifb |= WM8580_AIF_BCP;
623                 aifb |= WM8580_AIF_LRP;
624                 break;
625
626         case SND_SOC_DAIFMT_IB_NF:
627                 aifb |= WM8580_AIF_BCP;
628                 break;
629
630         case SND_SOC_DAIFMT_NB_IF:
631                 if (!can_invert_lrclk)
632                         return -EINVAL;
633                 aifb |= WM8580_AIF_LRP;
634                 break;
635
636         default:
637                 return -EINVAL;
638         }
639
640         wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
641         wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
642
643         return 0;
644 }
645
646 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
647                                  int div_id, int div)
648 {
649         struct snd_soc_codec *codec = codec_dai->codec;
650         unsigned int reg;
651
652         switch (div_id) {
653         case WM8580_MCLK:
654                 reg = wm8580_read(codec, WM8580_PLLB4);
655                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
656
657                 switch (div) {
658                 case WM8580_CLKSRC_MCLK:
659                         /* Input */
660                         break;
661
662                 case WM8580_CLKSRC_PLLA:
663                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
664                         break;
665                 case WM8580_CLKSRC_PLLB:
666                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
667                         break;
668
669                 case WM8580_CLKSRC_OSC:
670                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
671                         break;
672
673                 default:
674                         return -EINVAL;
675                 }
676                 wm8580_write(codec, WM8580_PLLB4, reg);
677                 break;
678
679         case WM8580_DAC_CLKSEL:
680                 reg = wm8580_read(codec, WM8580_CLKSEL);
681                 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
682
683                 switch (div) {
684                 case WM8580_CLKSRC_MCLK:
685                         break;
686
687                 case WM8580_CLKSRC_PLLA:
688                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
689                         break;
690
691                 case WM8580_CLKSRC_PLLB:
692                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
693                         break;
694
695                 default:
696                         return -EINVAL;
697                 }
698                 wm8580_write(codec, WM8580_CLKSEL, reg);
699                 break;
700
701         case WM8580_CLKOUTSRC:
702                 reg = wm8580_read(codec, WM8580_PLLB4);
703                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
704
705                 switch (div) {
706                 case WM8580_CLKSRC_NONE:
707                         break;
708
709                 case WM8580_CLKSRC_PLLA:
710                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
711                         break;
712
713                 case WM8580_CLKSRC_PLLB:
714                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
715                         break;
716
717                 case WM8580_CLKSRC_OSC:
718                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
719                         break;
720
721                 default:
722                         return -EINVAL;
723                 }
724                 wm8580_write(codec, WM8580_PLLB4, reg);
725                 break;
726
727         default:
728                 return -EINVAL;
729         }
730
731         return 0;
732 }
733
734 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
735 {
736         struct snd_soc_codec *codec = codec_dai->codec;
737         unsigned int reg;
738
739         reg = wm8580_read(codec, WM8580_DAC_CONTROL5);
740
741         if (mute)
742                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
743         else
744                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
745
746         wm8580_write(codec, WM8580_DAC_CONTROL5, reg);
747
748         return 0;
749 }
750
751 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
752         enum snd_soc_bias_level level)
753 {
754         u16 reg;
755         switch (level) {
756         case SND_SOC_BIAS_ON:
757         case SND_SOC_BIAS_PREPARE:
758         case SND_SOC_BIAS_STANDBY:
759                 break;
760         case SND_SOC_BIAS_OFF:
761                 reg = wm8580_read(codec, WM8580_PWRDN1);
762                 wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
763                 break;
764         }
765         codec->bias_level = level;
766         return 0;
767 }
768
769 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
770                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
771
772 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
773         .hw_params      = wm8580_paif_hw_params,
774         .set_fmt        = wm8580_set_paif_dai_fmt,
775         .set_clkdiv     = wm8580_set_dai_clkdiv,
776         .set_pll        = wm8580_set_dai_pll,
777         .digital_mute   = wm8580_digital_mute,
778 };
779
780 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
781         .hw_params      = wm8580_paif_hw_params,
782         .set_fmt        = wm8580_set_paif_dai_fmt,
783         .set_clkdiv     = wm8580_set_dai_clkdiv,
784         .set_pll        = wm8580_set_dai_pll,
785 };
786
787 struct snd_soc_dai wm8580_dai[] = {
788         {
789                 .name = "WM8580 PAIFRX",
790                 .id = 0,
791                 .playback = {
792                         .stream_name = "Playback",
793                         .channels_min = 1,
794                         .channels_max = 6,
795                         .rates = SNDRV_PCM_RATE_8000_192000,
796                         .formats = WM8580_FORMATS,
797                 },
798                 .ops = &wm8580_dai_ops_playback,
799         },
800         {
801                 .name = "WM8580 PAIFTX",
802                 .id = 1,
803                 .capture = {
804                         .stream_name = "Capture",
805                         .channels_min = 2,
806                         .channels_max = 2,
807                         .rates = SNDRV_PCM_RATE_8000_192000,
808                         .formats = WM8580_FORMATS,
809                 },
810                 .ops = &wm8580_dai_ops_capture,
811         },
812 };
813 EXPORT_SYMBOL_GPL(wm8580_dai);
814
815 /*
816  * initialise the WM8580 driver
817  * register the mixer and dsp interfaces with the kernel
818  */
819 static int wm8580_init(struct snd_soc_device *socdev)
820 {
821         struct snd_soc_codec *codec = socdev->card->codec;
822         int ret = 0;
823
824         codec->name = "WM8580";
825         codec->owner = THIS_MODULE;
826         codec->read = wm8580_read_reg_cache;
827         codec->write = wm8580_write;
828         codec->set_bias_level = wm8580_set_bias_level;
829         codec->dai = wm8580_dai;
830         codec->num_dai = ARRAY_SIZE(wm8580_dai);
831         codec->reg_cache_size = ARRAY_SIZE(wm8580_reg);
832         codec->reg_cache = kmemdup(wm8580_reg, sizeof(wm8580_reg),
833                                    GFP_KERNEL);
834
835         if (codec->reg_cache == NULL)
836                 return -ENOMEM;
837
838         /* Get the codec into a known state */
839         wm8580_write(codec, WM8580_RESET, 0);
840
841         /* Power up and get individual control of the DACs */
842         wm8580_write(codec, WM8580_PWRDN1, wm8580_read(codec, WM8580_PWRDN1) &
843                      ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD));
844
845         /* Make VMID high impedence */
846         wm8580_write(codec, WM8580_ADC_CONTROL1,
847                      wm8580_read(codec,  WM8580_ADC_CONTROL1) & ~0x100);
848
849         /* register pcms */
850         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1,
851                                SNDRV_DEFAULT_STR1);
852         if (ret < 0) {
853                 printk(KERN_ERR "wm8580: failed to create pcms\n");
854                 goto pcm_err;
855         }
856
857         snd_soc_add_controls(codec, wm8580_snd_controls,
858                                 ARRAY_SIZE(wm8580_snd_controls));
859         wm8580_add_widgets(codec);
860
861         ret = snd_soc_init_card(socdev);
862         if (ret < 0) {
863                 printk(KERN_ERR "wm8580: failed to register card\n");
864                 goto card_err;
865         }
866         return ret;
867
868 card_err:
869         snd_soc_free_pcms(socdev);
870         snd_soc_dapm_free(socdev);
871 pcm_err:
872         kfree(codec->reg_cache);
873         return ret;
874 }
875
876 /* If the i2c layer weren't so broken, we could pass this kind of data
877    around */
878 static struct snd_soc_device *wm8580_socdev;
879
880 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
881
882 /*
883  * WM8580 2 wire address is determined by GPIO5
884  * state during powerup.
885  *    low  = 0x1a
886  *    high = 0x1b
887  */
888
889 static int wm8580_i2c_probe(struct i2c_client *i2c,
890                             const struct i2c_device_id *id)
891 {
892         struct snd_soc_device *socdev = wm8580_socdev;
893         struct snd_soc_codec *codec = socdev->card->codec;
894         int ret;
895
896         i2c_set_clientdata(i2c, codec);
897         codec->control_data = i2c;
898
899         ret = wm8580_init(socdev);
900         if (ret < 0)
901                 dev_err(&i2c->dev, "failed to initialise WM8580\n");
902         return ret;
903 }
904
905 static int wm8580_i2c_remove(struct i2c_client *client)
906 {
907         struct snd_soc_codec *codec = i2c_get_clientdata(client);
908         kfree(codec->reg_cache);
909         return 0;
910 }
911
912 static const struct i2c_device_id wm8580_i2c_id[] = {
913         { "wm8580", 0 },
914         { }
915 };
916 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
917
918 static struct i2c_driver wm8580_i2c_driver = {
919         .driver = {
920                 .name = "WM8580 I2C Codec",
921                 .owner = THIS_MODULE,
922         },
923         .probe =    wm8580_i2c_probe,
924         .remove =   wm8580_i2c_remove,
925         .id_table = wm8580_i2c_id,
926 };
927
928 static int wm8580_add_i2c_device(struct platform_device *pdev,
929                                  const struct wm8580_setup_data *setup)
930 {
931         struct i2c_board_info info;
932         struct i2c_adapter *adapter;
933         struct i2c_client *client;
934         int ret;
935
936         ret = i2c_add_driver(&wm8580_i2c_driver);
937         if (ret != 0) {
938                 dev_err(&pdev->dev, "can't add i2c driver\n");
939                 return ret;
940         }
941
942         memset(&info, 0, sizeof(struct i2c_board_info));
943         info.addr = setup->i2c_address;
944         strlcpy(info.type, "wm8580", I2C_NAME_SIZE);
945
946         adapter = i2c_get_adapter(setup->i2c_bus);
947         if (!adapter) {
948                 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
949                         setup->i2c_bus);
950                 goto err_driver;
951         }
952
953         client = i2c_new_device(adapter, &info);
954         i2c_put_adapter(adapter);
955         if (!client) {
956                 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
957                         (unsigned int)info.addr);
958                 goto err_driver;
959         }
960
961         return 0;
962
963 err_driver:
964         i2c_del_driver(&wm8580_i2c_driver);
965         return -ENODEV;
966 }
967 #endif
968
969 static int wm8580_probe(struct platform_device *pdev)
970 {
971         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
972         struct wm8580_setup_data *setup;
973         struct snd_soc_codec *codec;
974         struct wm8580_priv *wm8580;
975         int ret = 0;
976
977         setup = socdev->codec_data;
978         codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
979         if (codec == NULL)
980                 return -ENOMEM;
981
982         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
983         if (wm8580 == NULL) {
984                 kfree(codec);
985                 return -ENOMEM;
986         }
987
988         codec->private_data = wm8580;
989         socdev->card->codec = codec;
990         mutex_init(&codec->mutex);
991         INIT_LIST_HEAD(&codec->dapm_widgets);
992         INIT_LIST_HEAD(&codec->dapm_paths);
993         wm8580_socdev = socdev;
994
995 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
996         if (setup->i2c_address) {
997                 codec->hw_write = (hw_write_t)i2c_master_send;
998                 ret = wm8580_add_i2c_device(pdev, setup);
999         }
1000 #else
1001                 /* Add other interfaces here */
1002 #endif
1003         return ret;
1004 }
1005
1006 /* power down chip */
1007 static int wm8580_remove(struct platform_device *pdev)
1008 {
1009         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1010         struct snd_soc_codec *codec = socdev->card->codec;
1011
1012         if (codec->control_data)
1013                 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
1014         snd_soc_free_pcms(socdev);
1015         snd_soc_dapm_free(socdev);
1016 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1017         i2c_unregister_device(codec->control_data);
1018         i2c_del_driver(&wm8580_i2c_driver);
1019 #endif
1020         kfree(codec->private_data);
1021         kfree(codec);
1022
1023         return 0;
1024 }
1025
1026 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
1027         .probe =        wm8580_probe,
1028         .remove =       wm8580_remove,
1029 };
1030 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
1031
1032 static int __init wm8580_modinit(void)
1033 {
1034         return snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
1035 }
1036 module_init(wm8580_modinit);
1037
1038 static void __exit wm8580_exit(void)
1039 {
1040         snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
1041 }
1042 module_exit(wm8580_exit);
1043
1044 MODULE_DESCRIPTION("ASoC WM8580 driver");
1045 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1046 MODULE_LICENSE("GPL");