sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <sound/core.h>
  28 #include <sound/pcm.h>
  29 #include <sound/pcm_params.h>
  30 #include <sound/soc.h>
  31 #include <sound/soc-dapm.h>
  32 #include <sound/tlv.h>
  33 #include <sound/initval.h>
  34 #include <asm/div64.h>
  35
  36 #include "wm8580.h"
  37
  38 /* WM8580 register space */
  39 #define WM8580_PLLA1                         0x00
  40 #define WM8580_PLLA2                         0x01
  41 #define WM8580_PLLA3                         0x02
  42 #define WM8580_PLLA4                         0x03
  43 #define WM8580_PLLB1                         0x04
  44 #define WM8580_PLLB2                         0x05
  45 #define WM8580_PLLB3                         0x06
  46 #define WM8580_PLLB4                         0x07
  47 #define WM8580_CLKSEL                        0x08
  48 #define WM8580_PAIF1                         0x09
  49 #define WM8580_PAIF2                         0x0A
  50 #define WM8580_SAIF1                         0x0B
  51 #define WM8580_PAIF3                         0x0C
  52 #define WM8580_PAIF4                         0x0D
  53 #define WM8580_SAIF2                         0x0E
  54 #define WM8580_DAC_CONTROL1                  0x0F
  55 #define WM8580_DAC_CONTROL2                  0x10
  56 #define WM8580_DAC_CONTROL3                  0x11
  57 #define WM8580_DAC_CONTROL4                  0x12
  58 #define WM8580_DAC_CONTROL5                  0x13
  59 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  60 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  61 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  62 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  63 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  64 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  65 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  66 #define WM8580_ADC_CONTROL1                  0x1D
  67 #define WM8580_SPDTXCHAN0                    0x1E
  68 #define WM8580_SPDTXCHAN1                    0x1F
  69 #define WM8580_SPDTXCHAN2                    0x20
  70 #define WM8580_SPDTXCHAN3                    0x21
  71 #define WM8580_SPDTXCHAN4                    0x22
  72 #define WM8580_SPDTXCHAN5                    0x23
  73 #define WM8580_SPDMODE                       0x24
  74 #define WM8580_INTMASK                       0x25
  75 #define WM8580_GPO1                          0x26
  76 #define WM8580_GPO2                          0x27
  77 #define WM8580_GPO3                          0x28
  78 #define WM8580_GPO4                          0x29
  79 #define WM8580_GPO5                          0x2A
  80 #define WM8580_INTSTAT                       0x2B
  81 #define WM8580_SPDRXCHAN1                    0x2C
  82 #define WM8580_SPDRXCHAN2                    0x2D
  83 #define WM8580_SPDRXCHAN3                    0x2E
  84 #define WM8580_SPDRXCHAN4                    0x2F
  85 #define WM8580_SPDRXCHAN5                    0x30
  86 #define WM8580_SPDSTAT                       0x31
  87 #define WM8580_PWRDN1                        0x32
  88 #define WM8580_PWRDN2                        0x33
  89 #define WM8580_READBACK                      0x34
  90 #define WM8580_RESET                         0x35
  91
  92 #define WM8580_MAX_REGISTER                  0x35
  93
  94 /* PLLB4 (register 7h) */
  95 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
  96 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
  97 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
  98 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
  99
 100 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 101 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 102 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 103 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 104
 105 /* CLKSEL (register 8h) */
 106 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 107 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 108 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 109
 110 /* AIF control 1 (registers 9h-bh) */
 111 #define WM8580_AIF_RATE_MASK       0x7
 112 #define WM8580_AIF_RATE_128        0x0
 113 #define WM8580_AIF_RATE_192        0x1
 114 #define WM8580_AIF_RATE_256        0x2
 115 #define WM8580_AIF_RATE_384        0x3
 116 #define WM8580_AIF_RATE_512        0x4
 117 #define WM8580_AIF_RATE_768        0x5
 118 #define WM8580_AIF_RATE_1152       0x6
 119
 120 #define WM8580_AIF_BCLKSEL_MASK   0x18
 121 #define WM8580_AIF_BCLKSEL_64     0x00
 122 #define WM8580_AIF_BCLKSEL_128    0x08
 123 #define WM8580_AIF_BCLKSEL_256    0x10
 124 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
 125
 126 #define WM8580_AIF_MS             0x20
 127
 128 #define WM8580_AIF_CLKSRC_MASK    0xc0
 129 #define WM8580_AIF_CLKSRC_PLLA    0x40
 130 #define WM8580_AIF_CLKSRC_PLLB    0x40
 131 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 132
 133 /* AIF control 2 (registers ch-eh) */
 134 #define WM8580_AIF_FMT_MASK    0x03
 135 #define WM8580_AIF_FMT_RIGHTJ  0x00
 136 #define WM8580_AIF_FMT_LEFTJ   0x01
 137 #define WM8580_AIF_FMT_I2S     0x02
 138 #define WM8580_AIF_FMT_DSP     0x03
 139
 140 #define WM8580_AIF_LENGTH_MASK   0x0c
 141 #define WM8580_AIF_LENGTH_16     0x00
 142 #define WM8580_AIF_LENGTH_20     0x04
 143 #define WM8580_AIF_LENGTH_24     0x08
 144 #define WM8580_AIF_LENGTH_32     0x0c
 145
 146 #define WM8580_AIF_LRP         0x10
 147 #define WM8580_AIF_BCP         0x20
 148
 149 /* Powerdown Register 1 (register 32h) */
 150 #define WM8580_PWRDN1_PWDN     0x001
 151 #define WM8580_PWRDN1_ALLDACPD 0x040
 152
 153 /* Powerdown Register 2 (register 33h) */
 154 #define WM8580_PWRDN2_OSSCPD   0x001
 155 #define WM8580_PWRDN2_PLLAPD   0x002
 156 #define WM8580_PWRDN2_PLLBPD   0x004
 157 #define WM8580_PWRDN2_SPDIFPD  0x008
 158 #define WM8580_PWRDN2_SPDIFTXD 0x010
 159 #define WM8580_PWRDN2_SPDIFRXD 0x020
 160
 161 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 162
 163 /*
 164  * wm8580 register cache
 165  * We can't read the WM8580 register space when we
 166  * are using 2 wire for device control, so we cache them instead.
 167  */
 168 static const u16 wm8580_reg[] = {
 169         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 170         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 171         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 172         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 173         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 174         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 175         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 176         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 177         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 178         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 179         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 180         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 181         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 182         0x0000, 0x0000 /*R53*/
 183 };
 184
 185 struct pll_state {
 186         unsigned int in;
 187         unsigned int out;
 188 };
 189
 190 /* codec private data */
 191 struct wm8580_priv {
 192         struct snd_soc_codec codec;
 193         u16 reg_cache[WM8580_MAX_REGISTER + 1];
 194         struct pll_state a;
 195         struct pll_state b;
 196 };
 197
 198
 199 /*
 200  * read wm8580 register cache
 201  */
 202 static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
 203         unsigned int reg)
 204 {
 205         u16 *cache = codec->reg_cache;
 206         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
 207         return cache[reg];
 208 }
 209
 210 /*
 211  * write wm8580 register cache
 212  */
 213 static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
 214         unsigned int reg, unsigned int value)
 215 {
 216         u16 *cache = codec->reg_cache;
 217
 218         cache[reg] = value;
 219 }
 220
 221 /*
 222  * write to the WM8580 register space
 223  */
 224 static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
 225         unsigned int value)
 226 {
 227         u8 data[2];
 228
 229         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
 230
 231         /* Registers are 9 bits wide */
 232         value &= 0x1ff;
 233
 234         switch (reg) {
 235         case WM8580_RESET:
 236                 /* Uncached */
 237                 break;
 238         default:
 239                 if (value == wm8580_read_reg_cache(codec, reg))
 240                         return 0;
 241         }
 242
 243         /* data is
 244          *   D15..D9 WM8580 register offset
 245          *   D8...D0 register data
 246          */
 247         data[0] = (reg << 1) | ((value >> 8) & 0x0001);
 248         data[1] = value & 0x00ff;
 249
 250         wm8580_write_reg_cache(codec, reg, value);
 251         if (codec->hw_write(codec->control_data, data, 2) == 2)
 252                 return 0;
 253         else
 254                 return -EIO;
 255 }
 256
 257 static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
 258                                        unsigned int reg)
 259 {
 260         switch (reg) {
 261         default:
 262                 return wm8580_read_reg_cache(codec, reg);
 263         }
 264 }
 265
 266 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 267
 268 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 269                          struct snd_ctl_elem_value *ucontrol)
 270 {
 271         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 272         int reg = kcontrol->private_value & 0xff;
 273         int reg2 = (kcontrol->private_value >> 24) & 0xff;
 274         int ret;
 275         u16 val;
 276
 277         /* Clear the register cache so we write without VU set */
 278         wm8580_write_reg_cache(codec, reg, 0);
 279         wm8580_write_reg_cache(codec, reg2, 0);
 280
 281         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 282         if (ret < 0)
 283                 return ret;
 284
 285         /* Now write again with the volume update bit set */
 286         val = wm8580_read_reg_cache(codec, reg);
 287         wm8580_write(codec, reg, val | 0x0100);
 288
 289         val = wm8580_read_reg_cache(codec, reg2);
 290         wm8580_write(codec, reg2, val | 0x0100);
 291
 292         return 0;
 293 }
 294
 295 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \
 296 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 297         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 298                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 299         .tlv.p = (tlv_array), \
 300         .info = snd_soc_info_volsw_2r, \
 301         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 302         .private_value = (reg_left) | ((shift) << 8)  |         \
 303                 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
 304
 305 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 306 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 307                             WM8580_DIGITAL_ATTENUATION_DACL1,
 308                             WM8580_DIGITAL_ATTENUATION_DACR1,
 309                             0, 0xff, 0, dac_tlv),
 310 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 311                             WM8580_DIGITAL_ATTENUATION_DACL2,
 312                             WM8580_DIGITAL_ATTENUATION_DACR2,
 313                             0, 0xff, 0, dac_tlv),
 314 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 315                             WM8580_DIGITAL_ATTENUATION_DACL3,
 316                             WM8580_DIGITAL_ATTENUATION_DACR3,
 317                             0, 0xff, 0, dac_tlv),
 318
 319 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 320 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 321 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 322
 323 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 324 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 325 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 326
 327 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 328 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
 329 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
 330 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
 331
 332 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
 333 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 334 };
 335
 336 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 337 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 338 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 339 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 340
 341 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 342 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 343 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 344 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 345 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 346 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 347
 348 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 349
 350 SND_SOC_DAPM_INPUT("AINL"),
 351 SND_SOC_DAPM_INPUT("AINR"),
 352 };
 353
 354 static const struct snd_soc_dapm_route audio_map[] = {
 355         { "VOUT1L", NULL, "DAC1" },
 356         { "VOUT1R", NULL, "DAC1" },
 357
 358         { "VOUT2L", NULL, "DAC2" },
 359         { "VOUT2R", NULL, "DAC2" },
 360
 361         { "VOUT3L", NULL, "DAC3" },
 362         { "VOUT3R", NULL, "DAC3" },
 363
 364         { "ADC", NULL, "AINL" },
 365         { "ADC", NULL, "AINR" },
 366 };
 367
 368 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 369 {
 370         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 371                                   ARRAY_SIZE(wm8580_dapm_widgets));
 372
 373         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 374
 375         snd_soc_dapm_new_widgets(codec);
 376         return 0;
 377 }
 378
 379 /* PLL divisors */
 380 struct _pll_div {
 381         u32 prescale:1;
 382         u32 postscale:1;
 383         u32 freqmode:2;
 384         u32 n:4;
 385         u32 k:24;
 386 };
 387
 388 /* The size in bits of the pll divide */
 389 #define FIXED_PLL_SIZE (1 << 22)
 390
 391 /* PLL rate to output rate divisions */
 392 static struct {
 393         unsigned int div;
 394         unsigned int freqmode;
 395         unsigned int postscale;
 396 } post_table[] = {
 397         {  2,  0, 0 },
 398         {  4,  0, 1 },
 399         {  4,  1, 0 },
 400         {  8,  1, 1 },
 401         {  8,  2, 0 },
 402         { 16,  2, 1 },
 403         { 12,  3, 0 },
 404         { 24,  3, 1 }
 405 };
 406
 407 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 408                        unsigned int source)
 409 {
 410         u64 Kpart;
 411         unsigned int K, Ndiv, Nmod;
 412         int i;
 413
 414         pr_debug("wm8580: PLL %dHz->%dHz\n", source, target);
 415
 416         /* Scale the output frequency up; the PLL should run in the
 417          * region of 90-100MHz.
 418          */
 419         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 420                 if (target * post_table[i].div >=  90000000 &&
 421                     target * post_table[i].div <= 100000000) {
 422                         pll_div->freqmode = post_table[i].freqmode;
 423                         pll_div->postscale = post_table[i].postscale;
 424                         target *= post_table[i].div;
 425                         break;
 426                 }
 427         }
 428
 429         if (i == ARRAY_SIZE(post_table)) {
 430                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 431                        "%u\n", target);
 432                 return -EINVAL;
 433         }
 434
 435         Ndiv = target / source;
 436
 437         if (Ndiv < 5) {
 438                 source /= 2;
 439                 pll_div->prescale = 1;
 440                 Ndiv = target / source;
 441         } else
 442                 pll_div->prescale = 0;
 443
 444         if ((Ndiv < 5) || (Ndiv > 13)) {
 445                 printk(KERN_ERR
 446                         "WM8580 N=%d outside supported range\n", Ndiv);
 447                 return -EINVAL;
 448         }
 449
 450         pll_div->n = Ndiv;
 451         Nmod = target % source;
 452         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 453
 454         do_div(Kpart, source);
 455
 456         K = Kpart & 0xFFFFFFFF;
 457
 458         pll_div->k = K;
 459
 460         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 461                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 462                  pll_div->postscale);
 463
 464         return 0;
 465 }
 466
 467 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai,
 468                 int pll_id, unsigned int freq_in, unsigned int freq_out)
 469 {
 470         int offset;
 471         struct snd_soc_codec *codec = codec_dai->codec;
 472         struct wm8580_priv *wm8580 = codec->private_data;
 473         struct pll_state *state;
 474         struct _pll_div pll_div;
 475         unsigned int reg;
 476         unsigned int pwr_mask;
 477         int ret;
 478
 479         /* GCC isn't able to work out the ifs below for initialising/using
 480          * pll_div so suppress warnings.
 481          */
 482         memset(&pll_div, 0, sizeof(pll_div));
 483
 484         switch (pll_id) {
 485         case WM8580_PLLA:
 486                 state = &wm8580->a;
 487                 offset = 0;
 488                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 489                 break;
 490         case WM8580_PLLB:
 491                 state = &wm8580->b;
 492                 offset = 4;
 493                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 494                 break;
 495         default:
 496                 return -ENODEV;
 497         }
 498
 499         if (freq_in && freq_out) {
 500                 ret = pll_factors(&pll_div, freq_out, freq_in);
 501                 if (ret != 0)
 502                         return ret;
 503         }
 504
 505         state->in = freq_in;
 506         state->out = freq_out;
 507
 508         /* Always disable the PLL - it is not safe to leave it running
 509          * while reprogramming it.
 510          */
 511         reg = wm8580_read(codec, WM8580_PWRDN2);
 512         wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 513
 514         if (!freq_in || !freq_out)
 515                 return 0;
 516
 517         wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 518         wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
 519         wm8580_write(codec, WM8580_PLLA3 + offset,
 520                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 521
 522         reg = wm8580_read(codec, WM8580_PLLA4 + offset);
 523         reg &= ~0x3f;
 524         reg |= pll_div.prescale | pll_div.postscale << 1 |
 525                 pll_div.freqmode << 4;
 526
 527         wm8580_write(codec, WM8580_PLLA4 + offset, reg);
 528
 529         /* All done, turn it on */
 530         reg = wm8580_read(codec, WM8580_PWRDN2);
 531         wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 532
 533         return 0;
 534 }
 535
 536 /*
 537  * Set PCM DAI bit size and sample rate.
 538  */
 539 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 540                                  struct snd_pcm_hw_params *params,
 541                                  struct snd_soc_dai *dai)
 542 {
 543         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 544         struct snd_soc_device *socdev = rtd->socdev;
 545         struct snd_soc_codec *codec = socdev->card->codec;
 546         u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->id);
 547
 548         paifb &= ~WM8580_AIF_LENGTH_MASK;
 549         /* bit size */
 550         switch (params_format(params)) {
 551         case SNDRV_PCM_FORMAT_S16_LE:
 552                 break;
 553         case SNDRV_PCM_FORMAT_S20_3LE:
 554                 paifb |= WM8580_AIF_LENGTH_20;
 555                 break;
 556         case SNDRV_PCM_FORMAT_S24_LE:
 557                 paifb |= WM8580_AIF_LENGTH_24;
 558                 break;
 559         case SNDRV_PCM_FORMAT_S32_LE:
 560                 paifb |= WM8580_AIF_LENGTH_24;
 561                 break;
 562         default:
 563                 return -EINVAL;
 564         }
 565
 566         wm8580_write(codec, WM8580_PAIF3 + dai->id, paifb);
 567         return 0;
 568 }
 569
 570 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 571                                       unsigned int fmt)
 572 {
 573         struct snd_soc_codec *codec = codec_dai->codec;
 574         unsigned int aifa;
 575         unsigned int aifb;
 576         int can_invert_lrclk;
 577
 578         aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id);
 579         aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id);
 580
 581         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 582
 583         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 584         case SND_SOC_DAIFMT_CBS_CFS:
 585                 aifa &= ~WM8580_AIF_MS;
 586                 break;
 587         case SND_SOC_DAIFMT_CBM_CFM:
 588                 aifa |= WM8580_AIF_MS;
 589                 break;
 590         default:
 591                 return -EINVAL;
 592         }
 593
 594         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 595         case SND_SOC_DAIFMT_I2S:
 596                 can_invert_lrclk = 1;
 597                 aifb |= WM8580_AIF_FMT_I2S;
 598                 break;
 599         case SND_SOC_DAIFMT_RIGHT_J:
 600                 can_invert_lrclk = 1;
 601                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 602                 break;
 603         case SND_SOC_DAIFMT_LEFT_J:
 604                 can_invert_lrclk = 1;
 605                 aifb |= WM8580_AIF_FMT_LEFTJ;
 606                 break;
 607         case SND_SOC_DAIFMT_DSP_A:
 608                 can_invert_lrclk = 0;
 609                 aifb |= WM8580_AIF_FMT_DSP;
 610                 break;
 611         case SND_SOC_DAIFMT_DSP_B:
 612                 can_invert_lrclk = 0;
 613                 aifb |= WM8580_AIF_FMT_DSP;
 614                 aifb |= WM8580_AIF_LRP;
 615                 break;
 616         default:
 617                 return -EINVAL;
 618         }
 619
 620         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 621         case SND_SOC_DAIFMT_NB_NF:
 622                 break;
 623
 624         case SND_SOC_DAIFMT_IB_IF:
 625                 if (!can_invert_lrclk)
 626                         return -EINVAL;
 627                 aifb |= WM8580_AIF_BCP;
 628                 aifb |= WM8580_AIF_LRP;
 629                 break;
 630
 631         case SND_SOC_DAIFMT_IB_NF:
 632                 aifb |= WM8580_AIF_BCP;
 633                 break;
 634
 635         case SND_SOC_DAIFMT_NB_IF:
 636                 if (!can_invert_lrclk)
 637                         return -EINVAL;
 638                 aifb |= WM8580_AIF_LRP;
 639                 break;
 640
 641         default:
 642                 return -EINVAL;
 643         }
 644
 645         wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
 646         wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
 647
 648         return 0;
 649 }
 650
 651 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 652                                  int div_id, int div)
 653 {
 654         struct snd_soc_codec *codec = codec_dai->codec;
 655         unsigned int reg;
 656
 657         switch (div_id) {
 658         case WM8580_MCLK:
 659                 reg = wm8580_read(codec, WM8580_PLLB4);
 660                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 661
 662                 switch (div) {
 663                 case WM8580_CLKSRC_MCLK:
 664                         /* Input */
 665                         break;
 666
 667                 case WM8580_CLKSRC_PLLA:
 668                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 669                         break;
 670                 case WM8580_CLKSRC_PLLB:
 671                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 672                         break;
 673
 674                 case WM8580_CLKSRC_OSC:
 675                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 676                         break;
 677
 678                 default:
 679                         return -EINVAL;
 680                 }
 681                 wm8580_write(codec, WM8580_PLLB4, reg);
 682                 break;
 683
 684         case WM8580_DAC_CLKSEL:
 685                 reg = wm8580_read(codec, WM8580_CLKSEL);
 686                 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
 687
 688                 switch (div) {
 689                 case WM8580_CLKSRC_MCLK:
 690                         break;
 691
 692                 case WM8580_CLKSRC_PLLA:
 693                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
 694                         break;
 695
 696                 case WM8580_CLKSRC_PLLB:
 697                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
 698                         break;
 699
 700                 default:
 701                         return -EINVAL;
 702                 }
 703                 wm8580_write(codec, WM8580_CLKSEL, reg);
 704                 break;
 705
 706         case WM8580_CLKOUTSRC:
 707                 reg = wm8580_read(codec, WM8580_PLLB4);
 708                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 709
 710                 switch (div) {
 711                 case WM8580_CLKSRC_NONE:
 712                         break;
 713
 714                 case WM8580_CLKSRC_PLLA:
 715                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 716                         break;
 717
 718                 case WM8580_CLKSRC_PLLB:
 719                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 720                         break;
 721
 722                 case WM8580_CLKSRC_OSC:
 723                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 724                         break;
 725
 726                 default:
 727                         return -EINVAL;
 728                 }
 729                 wm8580_write(codec, WM8580_PLLB4, reg);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 740 {
 741         struct snd_soc_codec *codec = codec_dai->codec;
 742         unsigned int reg;
 743
 744         reg = wm8580_read(codec, WM8580_DAC_CONTROL5);
 745
 746         if (mute)
 747                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 748         else
 749                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 750
 751         wm8580_write(codec, WM8580_DAC_CONTROL5, reg);
 752
 753         return 0;
 754 }
 755
 756 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 757         enum snd_soc_bias_level level)
 758 {
 759         u16 reg;
 760         switch (level) {
 761         case SND_SOC_BIAS_ON:
 762         case SND_SOC_BIAS_PREPARE:
 763                 break;
 764
 765         case SND_SOC_BIAS_STANDBY:
 766                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 767                         /* Power up and get individual control of the DACs */
 768                         reg = wm8580_read(codec, WM8580_PWRDN1);
 769                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
 770                         wm8580_write(codec, WM8580_PWRDN1, reg);
 771
 772                         /* Make VMID high impedence */
 773                         reg = wm8580_read(codec,  WM8580_ADC_CONTROL1);
 774                         reg &= ~0x100;
 775                         wm8580_write(codec, WM8580_ADC_CONTROL1, reg);
 776                 }
 777                 break;
 778
 779         case SND_SOC_BIAS_OFF:
 780                 reg = wm8580_read(codec, WM8580_PWRDN1);
 781                 wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 782                 break;
 783         }
 784         codec->bias_level = level;
 785         return 0;
 786 }
 787
 788 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 789                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 790
 791 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 792         .hw_params      = wm8580_paif_hw_params,
 793         .set_fmt        = wm8580_set_paif_dai_fmt,
 794         .set_clkdiv     = wm8580_set_dai_clkdiv,
 795         .set_pll        = wm8580_set_dai_pll,
 796         .digital_mute   = wm8580_digital_mute,
 797 };
 798
 799 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 800         .hw_params      = wm8580_paif_hw_params,
 801         .set_fmt        = wm8580_set_paif_dai_fmt,
 802         .set_clkdiv     = wm8580_set_dai_clkdiv,
 803         .set_pll        = wm8580_set_dai_pll,
 804 };
 805
 806 struct snd_soc_dai wm8580_dai[] = {
 807         {
 808                 .name = "WM8580 PAIFRX",
 809                 .id = 0,
 810                 .playback = {
 811                         .stream_name = "Playback",
 812                         .channels_min = 1,
 813                         .channels_max = 6,
 814                         .rates = SNDRV_PCM_RATE_8000_192000,
 815                         .formats = WM8580_FORMATS,
 816                 },
 817                 .ops = &wm8580_dai_ops_playback,
 818         },
 819         {
 820                 .name = "WM8580 PAIFTX",
 821                 .id = 1,
 822                 .capture = {
 823                         .stream_name = "Capture",
 824                         .channels_min = 2,
 825                         .channels_max = 2,
 826                         .rates = SNDRV_PCM_RATE_8000_192000,
 827                         .formats = WM8580_FORMATS,
 828                 },
 829                 .ops = &wm8580_dai_ops_capture,
 830         },
 831 };
 832 EXPORT_SYMBOL_GPL(wm8580_dai);
 833
 834 static struct snd_soc_codec *wm8580_codec;
 835
 836 static int wm8580_probe(struct platform_device *pdev)
 837 {
 838         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 839         struct snd_soc_codec *codec;
 840         int ret = 0;
 841
 842         if (wm8580_codec == NULL) {
 843                 dev_err(&pdev->dev, "Codec device not registered\n");
 844                 return -ENODEV;
 845         }
 846
 847         socdev->card->codec = wm8580_codec;
 848         codec = wm8580_codec;
 849
 850         /* register pcms */
 851         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
 852         if (ret < 0) {
 853                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
 854                 goto pcm_err;
 855         }
 856
 857         snd_soc_add_controls(codec, wm8580_snd_controls,
 858                              ARRAY_SIZE(wm8580_snd_controls));
 859         wm8580_add_widgets(codec);
 860         ret = snd_soc_init_card(socdev);
 861         if (ret < 0) {
 862                 dev_err(codec->dev, "failed to register card: %d\n", ret);
 863                 goto card_err;
 864         }
 865
 866         return ret;
 867
 868 card_err:
 869         snd_soc_free_pcms(socdev);
 870         snd_soc_dapm_free(socdev);
 871 pcm_err:
 872         return ret;
 873 }
 874
 875 /* power down chip */
 876 static int wm8580_remove(struct platform_device *pdev)
 877 {
 878         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 879
 880         snd_soc_free_pcms(socdev);
 881         snd_soc_dapm_free(socdev);
 882
 883         return 0;
 884 }
 885
 886 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
 887         .probe =        wm8580_probe,
 888         .remove =       wm8580_remove,
 889 };
 890 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
 891
 892 static int wm8580_register(struct wm8580_priv *wm8580)
 893 {
 894         int ret, i;
 895         struct snd_soc_codec *codec = &wm8580->codec;
 896
 897         if (wm8580_codec) {
 898                 dev_err(codec->dev, "Another WM8580 is registered\n");
 899                 ret = -EINVAL;
 900                 goto err;
 901         }
 902
 903         mutex_init(&codec->mutex);
 904         INIT_LIST_HEAD(&codec->dapm_widgets);
 905         INIT_LIST_HEAD(&codec->dapm_paths);
 906
 907         codec->private_data = wm8580;
 908         codec->name = "WM8580";
 909         codec->owner = THIS_MODULE;
 910         codec->read = wm8580_read_reg_cache;
 911         codec->write = wm8580_write;
 912         codec->bias_level = SND_SOC_BIAS_OFF;
 913         codec->set_bias_level = wm8580_set_bias_level;
 914         codec->dai = wm8580_dai;
 915         codec->num_dai = ARRAY_SIZE(wm8580_dai);
 916         codec->reg_cache_size = ARRAY_SIZE(wm8580->reg_cache);
 917         codec->reg_cache = &wm8580->reg_cache;
 918
 919         memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg));
 920
 921         /* Get the codec into a known state */
 922         ret = wm8580_write(codec, WM8580_RESET, 0);
 923         if (ret != 0) {
 924                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 925                 goto err;
 926         }
 927
 928         for (i = 0; i < ARRAY_SIZE(wm8580_dai); i++)
 929                 wm8580_dai[i].dev = codec->dev;
 930
 931         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 932
 933         wm8580_codec = codec;
 934
 935         ret = snd_soc_register_codec(codec);
 936         if (ret != 0) {
 937                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
 938                 goto err;
 939         }
 940
 941         ret = snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
 942         if (ret != 0) {
 943                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
 944                 goto err_codec;
 945         }
 946
 947         return 0;
 948
 949 err_codec:
 950         snd_soc_unregister_codec(codec);
 951 err:
 952         kfree(wm8580);
 953         return ret;
 954 }
 955
 956 static void wm8580_unregister(struct wm8580_priv *wm8580)
 957 {
 958         wm8580_set_bias_level(&wm8580->codec, SND_SOC_BIAS_OFF);
 959         snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
 960         snd_soc_unregister_codec(&wm8580->codec);
 961         kfree(wm8580);
 962         wm8580_codec = NULL;
 963 }
 964
 965 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 966 static int wm8580_i2c_probe(struct i2c_client *i2c,
 967                             const struct i2c_device_id *id)
 968 {
 969         struct wm8580_priv *wm8580;
 970         struct snd_soc_codec *codec;
 971
 972         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 973         if (wm8580 == NULL)
 974                 return -ENOMEM;
 975
 976         codec = &wm8580->codec;
 977         codec->hw_write = (hw_write_t)i2c_master_send;
 978
 979         i2c_set_clientdata(i2c, wm8580);
 980         codec->control_data = i2c;
 981
 982         codec->dev = &i2c->dev;
 983
 984         return wm8580_register(wm8580);
 985 }
 986
 987 static int wm8580_i2c_remove(struct i2c_client *client)
 988 {
 989         struct wm8580_priv *wm8580 = i2c_get_clientdata(client);
 990         wm8580_unregister(wm8580);
 991         return 0;
 992 }
 993
 994 static const struct i2c_device_id wm8580_i2c_id[] = {
 995         { "wm8580", 0 },
 996         { }
 997 };
 998 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 999
1000 static struct i2c_driver wm8580_i2c_driver = {
1001         .driver = {
1002                 .name = "wm8580",
1003                 .owner = THIS_MODULE,
1004         },
1005         .probe =    wm8580_i2c_probe,
1006         .remove =   wm8580_i2c_remove,
1007         .id_table = wm8580_i2c_id,
1008 };
1009 #endif
1010
1011 static int __init wm8580_modinit(void)
1012 {
1013         int ret;
1014
1015 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1016         ret = i2c_add_driver(&wm8580_i2c_driver);
1017         if (ret != 0) {
1018                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
1019         }
1020 #endif
1021
1022         return 0;
1023 }
1024 module_init(wm8580_modinit);
1025
1026 static void __exit wm8580_exit(void)
1027 {
1028 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1029         i2c_del_driver(&wm8580_i2c_driver);
1030 #endif
1031 }
1032 module_exit(wm8580_exit);
1033
1034 MODULE_DESCRIPTION("ASoC WM8580 driver");
1035 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1036 MODULE_LICENSE("GPL");