2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
11 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCstation 10, 20, LX and Voyager models.
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formarly AT&T microelectronics) home
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, nr 0-15) or between two serial
31 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and nr of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) timemultiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the onboard
44 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
49 * I've tried to stick to the following function naming conventions:
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
56 #include <sound/driver.h>
57 #include <linux/interrupt.h>
58 #include <linux/delay.h>
60 #include <sound/core.h>
61 #include <sound/pcm.h>
62 #include <sound/pcm_params.h>
63 #include <sound/info.h>
64 #include <sound/control.h>
65 #include <sound/initval.h>
70 #include <asm/atomic.h>
72 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
73 MODULE_DESCRIPTION("Sun DBRI");
74 MODULE_LICENSE("GPL");
75 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
77 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
78 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
79 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
81 module_param_array(index, int, NULL, 0444);
82 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
83 module_param_array(id, charp, NULL, 0444);
84 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
85 module_param_array(enable, bool, NULL, 0444);
86 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
97 static int dbri_debug;
98 module_param(dbri_debug, int, 0644);
99 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
102 static char *cmds[] = {
103 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
104 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
107 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
110 #define dprintk(a, x...)
112 #endif /* DBRI_DEBUG */
114 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
118 /***************************************************************************
119 CS4215 specific definitions and structures
120 ****************************************************************************/
123 __u8 data[4]; /* Data mode: Time slots 5-8 */
124 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
126 __u8 offset; /* Bit offset from frame sync to time slot 1 */
127 volatile __u32 status;
128 volatile __u32 version;
129 __u8 precision; /* In bits, either 8 or 16 */
130 __u8 channels; /* 1 or 2 */
137 /* Time Slot 1, Status register */
138 #define CS4215_CLB (1<<2) /* Control Latch Bit */
139 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
140 /* 0: line: 2.8V, speaker 8V */
141 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
142 #define CS4215_RSRVD_1 (1<<5)
144 /* Time Slot 2, Data Format Register */
145 #define CS4215_DFR_LINEAR16 0
146 #define CS4215_DFR_ULAW 1
147 #define CS4215_DFR_ALAW 2
148 #define CS4215_DFR_LINEAR8 3
149 #define CS4215_DFR_STEREO (1<<2)
155 { 8000, (1 << 4), (0 << 3) },
156 { 16000, (1 << 4), (1 << 3) },
157 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
158 { 32000, (1 << 4), (3 << 3) },
159 /* { NA, (1 << 4), (4 << 3) }, */
160 /* { NA, (1 << 4), (5 << 3) }, */
161 { 48000, (1 << 4), (6 << 3) },
162 { 9600, (1 << 4), (7 << 3) },
163 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
164 { 11025, (2 << 4), (1 << 3) },
165 { 18900, (2 << 4), (2 << 3) },
166 { 22050, (2 << 4), (3 << 3) },
167 { 37800, (2 << 4), (4 << 3) },
168 { 44100, (2 << 4), (5 << 3) },
169 { 33075, (2 << 4), (6 << 3) },
170 { 6615, (2 << 4), (7 << 3) },
174 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
176 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
178 /* Time Slot 3, Serial Port Control register */
179 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
180 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
181 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
182 #define CS4215_BSEL_128 (1<<2)
183 #define CS4215_BSEL_256 (2<<2)
184 #define CS4215_MCK_MAST (0<<4) /* Master clock */
185 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
186 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
187 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
188 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
190 /* Time Slot 4, Test Register */
191 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
192 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
194 /* Time Slot 5, Parallel Port Register */
195 /* Read only here and the same as the in data mode */
197 /* Time Slot 6, Reserved */
199 /* Time Slot 7, Version Register */
200 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
202 /* Time Slot 8, Reserved */
207 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
209 /* Time Slot 5, Output Setting */
210 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
211 #define CS4215_LE (1<<6) /* Line Out Enable */
212 #define CS4215_HE (1<<7) /* Headphone Enable */
214 /* Time Slot 6, Output Setting */
215 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
216 #define CS4215_SE (1<<6) /* Speaker Enable */
217 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
219 /* Time Slot 7, Input Setting */
220 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
221 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
222 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
223 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
224 #define CS4215_PIO1 (1<<7)
226 /* Time Slot 8, Input Setting */
227 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
228 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
230 /***************************************************************************
231 DBRI specific definitions and structures
232 ****************************************************************************/
234 /* DBRI main registers */
235 #define REG0 0x00UL /* Status and Control */
236 #define REG1 0x04UL /* Mode and Interrupt */
237 #define REG2 0x08UL /* Parallel IO */
238 #define REG3 0x0cUL /* Test */
239 #define REG8 0x20UL /* Command Queue Pointer */
240 #define REG9 0x24UL /* Interrupt Queue Pointer */
242 #define DBRI_NO_CMDS 64
243 #define DBRI_INT_BLK 64
244 #define DBRI_NO_DESCS 64
245 #define DBRI_NO_PIPES 32
246 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
250 #define DBRI_NO_STREAMS 2
252 /* One transmit/receive descriptor */
253 /* When ba != 0 descriptor is used */
255 volatile __u32 word1;
256 __u32 ba; /* Transmit/Receive Buffer Address */
257 __u32 nda; /* Next Descriptor Address */
258 volatile __u32 word4;
261 /* This structure is in a DMA region where it can accessed by both
262 * the CPU and the DBRI
265 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
266 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
267 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
270 #define dbri_dma_off(member, elem) \
271 ((u32)(unsigned long) \
272 (&(((struct dbri_dma *)0)->member[elem])))
274 enum in_or_out { PIPEinput, PIPEoutput };
277 u32 sdp; /* SDP command word */
278 int nextpipe; /* Next pipe in linked list */
279 int length; /* Length of timeslot (bits) */
280 int first_desc; /* Index of first descriptor */
281 int desc; /* Index of active descriptor */
282 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
285 /* Per stream (playback or record) information */
286 struct dbri_streaminfo {
287 struct snd_pcm_substream *substream;
288 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
289 int size; /* Size of DMA buffer */
290 size_t offset; /* offset in user buffer */
291 int pipe; /* Data pipe used */
292 int left_gain; /* mixer elements */
296 /* This structure holds the information for both chips (DBRI & CS4215) */
298 struct snd_card *card; /* ALSA card */
300 int regs_size, irq; /* Needed for unload */
301 struct sbus_dev *sdev; /* SBUS device info */
304 struct dbri_dma *dma; /* Pointer to our DMA block */
305 u32 dma_dvma; /* DBRI visible DMA address */
307 void __iomem *regs; /* dbri HW regs */
308 int dbri_irqp; /* intr queue pointer */
310 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
311 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
312 spinlock_t cmdlock; /* Protects cmd queue accesses */
313 s32 *cmdptr; /* Pointer to the last queued cmd */
317 struct cs4215 mm; /* mmcodec special info */
318 /* per stream (playback/record) info */
319 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
321 struct snd_dbri *next;
324 #define DBRI_MAX_VOLUME 63 /* Output volume */
325 #define DBRI_MAX_GAIN 15 /* Input gain */
327 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
328 #define D_P (1<<15) /* Program command & queue pointer valid */
329 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
330 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
331 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
332 #define D_X (1<<7) /* Sanity Timer Disable */
333 #define D_T (1<<6) /* Permit activation of the TE interface */
334 #define D_N (1<<5) /* Permit activation of the NT interface */
335 #define D_C (1<<4) /* Permit activation of the CHI interface */
336 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
337 #define D_D (1<<2) /* Disable Master Mode */
338 #define D_H (1<<1) /* Halt for Analysis */
339 #define D_R (1<<0) /* Soft Reset */
341 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
342 #define D_LITTLE_END (1<<8) /* Byte Order */
343 #define D_BIG_END (0<<8) /* Byte Order */
344 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
345 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
346 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
347 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
348 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
350 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
351 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
352 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
353 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
354 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
355 #define D_ENPIO (0xf0) /* Enable all the pins */
356 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
357 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
358 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
359 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
361 /* DBRI Commands (Page 20) */
362 #define D_WAIT 0x0 /* Stop execution */
363 #define D_PAUSE 0x1 /* Flush long pipes */
364 #define D_JUMP 0x2 /* New command queue */
365 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
366 #define D_REX 0x4 /* Report command execution via interrupt */
367 #define D_SDP 0x5 /* Setup Data Pipe */
368 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
369 #define D_DTS 0x7 /* Define Time Slot */
370 #define D_SSP 0x8 /* Set short Data Pipe */
371 #define D_CHI 0x9 /* Set CHI Global Mode */
372 #define D_NT 0xa /* NT Command */
373 #define D_TE 0xb /* TE Command */
374 #define D_CDEC 0xc /* Codec setup */
375 #define D_TEST 0xd /* No comment */
376 #define D_CDM 0xe /* CHI Data mode command */
378 /* Special bits for some commands */
379 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
381 /* Setup Data Pipe */
383 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
384 #define D_SDP_CHANGE (2<<18) /* Report any changes */
385 #define D_SDP_EVERY (3<<18) /* Report any changes */
386 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
387 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
390 #define D_SDP_MEM (0<<13) /* To/from memory */
391 #define D_SDP_HDLC (2<<13)
392 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
393 #define D_SDP_SER (4<<13) /* Serial to serial */
394 #define D_SDP_FIXED (6<<13) /* Short only */
395 #define D_SDP_MODE(v) ((v)&(7<<13))
397 #define D_SDP_TO_SER (1<<12) /* Direction */
398 #define D_SDP_FROM_SER (0<<12) /* Direction */
399 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
400 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
401 #define D_SDP_P (1<<10) /* Pointer Valid */
402 #define D_SDP_A (1<<8) /* Abort */
403 #define D_SDP_C (1<<7) /* Clear */
405 /* Define Time Slot */
406 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
407 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
408 #define D_DTS_INS (1<<15) /* Insert Time Slot */
409 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
410 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
411 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
413 /* Time Slot defines */
414 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
415 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
416 #define D_TS_DI (1<<13) /* Data Invert */
417 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
418 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
419 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
420 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
421 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
422 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
424 /* Concentration Highway Interface Modes */
425 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
426 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
427 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
428 #define D_CHI_OD (1<<13) /* Open Drain Enable */
429 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
430 #define D_CHI_FD (1<<11) /* Frame Drive */
431 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
433 /* NT: These are here for completeness */
434 #define D_NT_FBIT (1<<17) /* Frame Bit */
435 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
436 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
437 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
438 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
439 #define D_NT_FT (1<<12) /* Fixed Timing */
440 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
441 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
442 #define D_NT_ACT (1<<9) /* Activate Interface */
443 #define D_NT_MFE (1<<8) /* Multiframe Enable */
444 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
445 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
446 #define D_NT_FACT (1<<1) /* Force Activation */
447 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
450 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
451 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
452 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
455 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
456 #define D_TEST_SIZE(v) ((v)<<11) /* */
457 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
458 #define D_TEST_PROC 0x6 /* MicroProcessor test */
459 #define D_TEST_SER 0x7 /* Serial-Controller test */
460 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
461 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
462 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
463 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
464 #define D_TEST_DUMP 0xe /* ROM Dump */
467 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
468 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
469 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
470 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
471 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
472 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
475 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
476 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
477 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
478 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
479 #define D_INTR_EOL 5 /* End of List */
480 #define D_INTR_CMDI 6 /* Command has bean read */
481 #define D_INTR_XCMP 8 /* Transmission of frame complete */
482 #define D_INTR_SBRI 9 /* BRI status change info */
483 #define D_INTR_FXDT 10 /* Fixed data change */
484 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
485 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
486 #define D_INTR_DBYT 12 /* Dropped by frame slip */
487 #define D_INTR_RBYT 13 /* Repeated by frame slip */
488 #define D_INTR_LINT 14 /* Lost Interrupt */
489 #define D_INTR_UNDR 15 /* DMA underrun */
493 #define D_INTR_CHI 36
494 #define D_INTR_CMD 38
496 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
497 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
498 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
499 #define D_INTR_GETVAL(v) ((v) & 0xffff)
500 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
502 #define D_P_0 0 /* TE receive anchor */
503 #define D_P_1 1 /* TE transmit anchor */
504 #define D_P_2 2 /* NT transmit anchor */
505 #define D_P_3 3 /* NT receive anchor */
506 #define D_P_4 4 /* CHI send data */
507 #define D_P_5 5 /* CHI receive data */
508 #define D_P_6 6 /* */
509 #define D_P_7 7 /* */
510 #define D_P_8 8 /* */
511 #define D_P_9 9 /* */
512 #define D_P_10 10 /* */
513 #define D_P_11 11 /* */
514 #define D_P_12 12 /* */
515 #define D_P_13 13 /* */
516 #define D_P_14 14 /* */
517 #define D_P_15 15 /* */
518 #define D_P_16 16 /* CHI anchor pipe */
519 #define D_P_17 17 /* CHI send */
520 #define D_P_18 18 /* CHI receive */
521 #define D_P_19 19 /* CHI receive */
522 #define D_P_20 20 /* CHI receive */
523 #define D_P_21 21 /* */
524 #define D_P_22 22 /* */
525 #define D_P_23 23 /* */
526 #define D_P_24 24 /* */
527 #define D_P_25 25 /* */
528 #define D_P_26 26 /* */
529 #define D_P_27 27 /* */
530 #define D_P_28 28 /* */
531 #define D_P_29 29 /* */
532 #define D_P_30 30 /* */
533 #define D_P_31 31 /* */
535 /* Transmit descriptor defines */
536 #define DBRI_TD_F (1<<31) /* End of Frame */
537 #define DBRI_TD_D (1<<30) /* Do not append CRC */
538 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
539 #define DBRI_TD_B (1<<15) /* Final interrupt */
540 #define DBRI_TD_M (1<<14) /* Marker interrupt */
541 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
542 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
543 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
544 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
545 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
546 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
547 /* Maximum buffer size per TD: almost 8Kb */
548 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
550 /* Receive descriptor defines */
551 #define DBRI_RD_F (1<<31) /* End of Frame */
552 #define DBRI_RD_C (1<<30) /* Completed buffer */
553 #define DBRI_RD_B (1<<15) /* Final interrupt */
554 #define DBRI_RD_M (1<<14) /* Marker interrupt */
555 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
556 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
557 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
558 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
559 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
560 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
561 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
563 /* stream_info[] access */
564 /* Translate the ALSA direction into the array index */
565 #define DBRI_STREAMNO(substream) \
566 (substream->stream == \
567 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
569 /* Return a pointer to dbri_streaminfo */
570 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
572 static struct snd_dbri *dbri_list; /* All DBRI devices */
575 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
576 * So we have to reverse the bits. Note: not all bit lengths are supported
578 static __u32 reverse_bytes(__u32 b, int len)
582 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
584 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
586 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
588 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
590 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
595 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
602 ****************************************************************************
603 ************** DBRI initialization and command synchronization *************
604 ****************************************************************************
606 Commands are sent to the DBRI by building a list of them in memory,
607 then writing the address of the first list item to DBRI register 8.
608 The list is terminated with a WAIT command, which generates a
609 CPU interrupt to signal completion.
611 Since the DBRI can run in parallel with the CPU, several means of
612 synchronization present themselves. The method implemented here is only
613 to use the dbri_cmdwait() to wait for execution of batch of sent commands.
615 A circular command buffer is used here. A new command is being added
616 while other can be executed. The scheme works by adding two WAIT commands
617 after each sent batch of commands. When the next batch is prepared it is
618 added after the WAIT commands then the WAITs are replaced with single JUMP
619 command to the new batch. The the DBRI is forced to reread the last WAIT
620 command (replaced by the JUMP by then). If the DBRI is still executing
621 previous commands the request to reread the WAIT command is ignored.
623 Every time a routine wants to write commands to the DBRI, it must
624 first call dbri_cmdlock() and get pointer to a free space in
625 dbri->dma->cmd buffer. After this, the commands can be written to
626 the buffer, and dbri_cmdsend() is called with the final pointer value
627 to send them to the DBRI.
633 * Wait for the current command string to execute
635 static void dbri_cmdwait(struct snd_dbri *dbri)
637 int maxloops = MAXLOOPS;
639 /* Delay if previous commands are still being processed */
640 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P))
641 msleep_interruptible(1);
644 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
646 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
647 MAXLOOPS - maxloops - 1);
651 * Lock the command queue and returns pointer to a space for len cmd words
652 * It locks the cmdlock spinlock.
654 static s32 *dbri_cmdlock(struct snd_dbri * dbri, int len)
656 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
658 spin_lock(&dbri->cmdlock);
659 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
660 return dbri->cmdptr + 2;
661 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
662 return dbri->dma->cmd;
664 printk(KERN_ERR "DBRI: no space for commands.");
670 * Send prepared cmd string. It works by writting a JUMP cmd into
671 * the last WAIT cmd and force DBRI to reread the cmd.
672 * The JUMP cmd points to the new cmd string.
673 * It also releases the cmdlock spinlock.
675 static void dbri_cmdsend(struct snd_dbri * dbri, s32 * cmd,int len)
679 static int wait_id = 0;
682 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
683 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
684 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
686 /* Replace the last command with JUMP */
687 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
688 *(dbri->cmdptr+1) = addr;
689 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
692 if (cmd > dbri->cmdptr) {
695 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++) {
696 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
699 s32 *ptr = dbri->cmdptr;
701 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
703 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
704 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++) {
705 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
710 spin_lock_irqsave(&dbri->lock, flags);
711 /* Reread the last command */
712 tmp = sbus_readl(dbri->regs + REG0);
714 sbus_writel(tmp, dbri->regs + REG0);
715 spin_unlock_irqrestore(&dbri->lock, flags);
718 spin_unlock(&dbri->cmdlock);
721 /* Lock must be held when calling this */
722 static void dbri_reset(struct snd_dbri * dbri)
727 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
728 sbus_readl(dbri->regs + REG0),
729 sbus_readl(dbri->regs + REG2),
730 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
732 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
733 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
736 /* A brute approach - DBRI falls back to working burst size by itself
737 * On SS20 D_S does not work, so do not try so high. */
738 tmp = sbus_readl(dbri->regs + REG0);
741 sbus_writel(tmp, dbri->regs + REG0);
744 /* Lock must not be held before calling this */
745 static void dbri_initialize(struct snd_dbri * dbri)
752 spin_lock_irqsave(&dbri->lock, flags);
756 /* Initialize pipes */
757 for (n = 0; n < DBRI_NO_PIPES; n++)
758 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
760 spin_lock_init(&dbri->cmdlock);
762 * Initialize the interrupt ringbuffer.
764 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
765 dbri->dma->intr[0] = dma_addr;
768 * Set up the interrupt queue
770 spin_lock(&dbri->cmdlock);
771 cmd = dbri->cmdptr = dbri->dma->cmd;
772 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
774 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
776 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
777 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
778 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
779 sbus_writel(dma_addr, dbri->regs + REG8);
780 spin_unlock(&dbri->cmdlock);
783 spin_unlock_irqrestore(&dbri->lock, flags);
787 ****************************************************************************
788 ************************** DBRI data pipe management ***********************
789 ****************************************************************************
791 While DBRI control functions use the command and interrupt buffers, the
792 main data path takes the form of data pipes, which can be short (command
793 and interrupt driven), or long (attached to DMA buffers). These functions
794 provide a rudimentary means of setting up and managing the DBRI's pipes,
795 but the calling functions have to make sure they respect the pipes' linked
796 list ordering, among other things. The transmit and receive functions
797 here interface closely with the transmit and receive interrupt code.
800 static int pipe_active(struct snd_dbri * dbri, int pipe)
802 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
805 /* reset_pipe(dbri, pipe)
807 * Called on an in-use pipe to clear anything being transmitted or received
808 * Lock must be held before calling this.
810 static void reset_pipe(struct snd_dbri * dbri, int pipe)
816 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
817 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
821 sdp = dbri->pipes[pipe].sdp;
823 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
827 cmd = dbri_cmdlock(dbri, 3);
828 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
830 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
831 dbri_cmdsend(dbri, cmd, 3);
833 desc = dbri->pipes[pipe].first_desc;
836 dbri->dma->desc[desc].nda = dbri->dma->desc[desc].ba = 0;
837 desc = dbri->next_desc[desc];
838 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
840 dbri->pipes[pipe].desc = -1;
841 dbri->pipes[pipe].first_desc = -1;
844 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
846 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
847 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
851 if ((sdp & 0xf800) != sdp) {
852 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
856 /* If this is a fixed receive pipe, arrange for an interrupt
857 * every time its data changes
859 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
863 dbri->pipes[pipe].sdp = sdp;
864 dbri->pipes[pipe].desc = -1;
865 dbri->pipes[pipe].first_desc = -1;
867 reset_pipe(dbri, pipe);
870 static void link_time_slot(struct snd_dbri * dbri, int pipe,
871 int prevpipe, int nextpipe,
872 int length, int cycle)
877 if (pipe < 0 || pipe > DBRI_MAX_PIPE
878 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
879 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
881 "DBRI: link_time_slot called with illegal pipe number\n");
885 if (dbri->pipes[pipe].sdp == 0
886 || dbri->pipes[prevpipe].sdp == 0
887 || dbri->pipes[nextpipe].sdp == 0) {
888 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
892 dbri->pipes[prevpipe].nextpipe = pipe;
893 dbri->pipes[pipe].nextpipe = nextpipe;
894 dbri->pipes[pipe].length = length;
896 cmd = dbri_cmdlock(dbri, 4);
898 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
899 /* Deal with CHI special case:
900 * "If transmission on edges 0 or 1 is desired, then cycle n
901 * (where n = # of bit times per frame...) must be used."
902 * - DBRI data sheet, page 11
904 if (prevpipe == 16 && cycle == 0)
905 cycle = dbri->chi_bpf;
907 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
908 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
911 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
913 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
914 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
916 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
919 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
921 dbri_cmdsend(dbri, cmd, 4);
924 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
925 enum in_or_out direction, int prevpipe,
931 if (pipe < 0 || pipe > DBRI_MAX_PIPE
932 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
933 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
935 "DBRI: unlink_time_slot called with illegal pipe number\n");
939 cmd = dbri_cmdlock(dbri, 4);
941 if (direction == PIPEinput) {
942 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
943 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
944 *(cmd++) = D_TS_NEXT(nextpipe);
947 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
948 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
950 *(cmd++) = D_TS_NEXT(nextpipe);
952 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
954 dbri_cmdsend(dbri, cmd, 4);
957 /* xmit_fixed() / recv_fixed()
959 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
960 * expected to change much, and which we don't need to buffer.
961 * The DBRI only interrupts us when the data changes (receive pipes),
962 * or only changes the data when this function is called (transmit pipes).
963 * Only short pipes (numbers 16-31) can be used in fixed data mode.
965 * These function operate on a 32-bit field, no matter how large
966 * the actual time slot is. The interrupt handler takes care of bit
967 * ordering and alignment. An 8-bit time slot will always end up
968 * in the low-order 8 bits, filled either MSB-first or LSB-first,
969 * depending on the settings passed to setup_pipe()
971 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
975 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
976 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
980 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
981 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
985 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
986 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
990 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
991 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
995 /* DBRI short pipes always transmit LSB first */
997 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
998 data = reverse_bytes(data, dbri->pipes[pipe].length);
1000 cmd = dbri_cmdlock(dbri, 3);
1002 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1004 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1006 dbri_cmdsend(dbri, cmd, 3);
1010 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1012 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1013 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1017 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1018 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1022 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1023 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1027 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1032 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1033 * with a DMA buffer.
1035 * Only pipe numbers 0-15 can be used in this mode.
1037 * This function takes a stream number pointing to a data buffer,
1038 * and work by building chains of descriptors which identify the
1039 * data buffers. Buffers too large for a single descriptor will
1040 * be spread across multiple descriptors.
1042 * All descriptors create a ring buffer.
1044 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1046 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1050 int first_desc = -1;
1053 if (info->pipe < 0 || info->pipe > 15) {
1054 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1058 if (dbri->pipes[info->pipe].sdp == 0) {
1059 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1064 dvma_buffer = info->dvma_buffer;
1067 if (streamno == DBRI_PLAY) {
1068 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1069 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1074 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1076 "DBRI: setup_descs: Called on transmit pipe %d\n",
1080 /* Should be able to queue multiple buffers to receive on a pipe */
1081 if (pipe_active(dbri, info->pipe)) {
1082 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1087 /* Make sure buffer size is multiple of four */
1094 for (; desc < DBRI_NO_DESCS; desc++) {
1095 if (!dbri->dma->desc[desc].ba)
1098 if (desc == DBRI_NO_DESCS) {
1099 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1103 if (len > DBRI_TD_MAXCNT)
1104 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1111 dbri->next_desc[desc] = -1;
1112 dbri->dma->desc[desc].ba = dvma_buffer;
1113 dbri->dma->desc[desc].nda = 0;
1115 if (streamno == DBRI_PLAY) {
1116 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1117 dbri->dma->desc[desc].word4 = 0;
1118 dbri->dma->desc[desc].word1 |=
1119 DBRI_TD_F | DBRI_TD_B;
1121 dbri->dma->desc[desc].word1 = 0;
1122 dbri->dma->desc[desc].word4 =
1123 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1126 if (first_desc == -1)
1129 dbri->next_desc[last_desc] = desc;
1130 dbri->dma->desc[last_desc].nda =
1131 dbri->dma_dvma + dbri_dma_off(desc, desc);
1135 dvma_buffer += mylen;
1139 if (first_desc == -1 || last_desc == -1) {
1140 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1144 if (streamno == DBRI_PLAY) {
1145 dbri->dma->desc[last_desc].word1 |=
1146 DBRI_TD_F | DBRI_TD_B;
1147 dbri->dma->desc[last_desc].nda =
1148 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1149 dbri->next_desc[last_desc] = first_desc;
1151 dbri->pipes[info->pipe].first_desc = first_desc;
1152 dbri->pipes[info->pipe].desc = first_desc;
1155 for (desc = first_desc; desc != -1; ) {
1156 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1158 dbri->dma->desc[desc].word1,
1159 dbri->dma->desc[desc].ba,
1160 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1161 desc = dbri->next_desc[desc];
1162 if ( desc == first_desc )
1170 ****************************************************************************
1171 ************************** DBRI - CHI interface ****************************
1172 ****************************************************************************
1174 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1175 multiplexed serial interface which the DBRI can operate in either master
1176 (give clock/frame sync) or slave (take clock/frame sync) mode.
1180 enum master_or_slave { CHImaster, CHIslave };
1182 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1188 /* Set CHI Anchor: Pipe 16 */
1190 cmd = dbri_cmdlock(dbri, 4);
1191 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1192 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1193 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1194 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1195 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1196 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1197 dbri_cmdsend(dbri, cmd, 4);
1199 dbri->pipes[16].sdp = 1;
1200 dbri->pipes[16].nextpipe = 16;
1202 cmd = dbri_cmdlock(dbri, 4);
1204 if (master_or_slave == CHIslave) {
1205 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1207 * CHICM = 0 (slave mode, 8 kHz frame rate)
1208 * IR = give immediate CHI status interrupt
1209 * EN = give CHI status interrupt upon change
1211 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1213 /* Setup DBRI for CHI Master - generate clock, FS
1215 * BPF = bits per 8 kHz frame
1216 * 12.288 MHz / CHICM_divisor = clock rate
1217 * FD = 1 - drive CHIFS on rising edge of CHICK
1219 int clockrate = bits_per_frame * 8;
1220 int divisor = 12288 / clockrate;
1222 if (divisor > 255 || divisor * clockrate != 12288)
1223 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1225 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1226 | D_CHI_BPF(bits_per_frame));
1229 dbri->chi_bpf = bits_per_frame;
1233 * RCE = 0 - receive on falling edge of CHICK
1234 * XCE = 1 - transmit on rising edge of CHICK
1235 * XEN = 1 - enable transmitter
1236 * REN = 1 - enable receiver
1239 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1240 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1241 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1243 dbri_cmdsend(dbri, cmd, 4);
1247 ****************************************************************************
1248 *********************** CS4215 audio codec management **********************
1249 ****************************************************************************
1251 In the standard SPARC audio configuration, the CS4215 codec is attached
1252 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1255 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1259 * Pipe 4: Send timeslots 1-4 (audio data)
1260 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1261 * Pipe 6: Receive timeslots 1-4 (audio data)
1262 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1263 * interrupt, and the rest of the data (slot 5 and 8) is
1264 * not relevant for us (only for doublechecking).
1267 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1268 * Pipe 18: Receive timeslot 1 (clb).
1269 * Pipe 19: Receive timeslot 7 (version).
1272 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1273 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1274 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1275 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1277 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1278 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1279 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1284 static int cs4215_init_data(struct cs4215 *mm)
1287 * No action, memory resetting only.
1289 * Data Time Slot 5-8
1290 * Speaker,Line and Headphone enable. Gain set to the half.
1293 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1294 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1295 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1296 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1299 * Control Time Slot 1-4
1300 * 0: Default I/O voltage scale
1301 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1302 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1305 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1306 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1307 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1312 mm->precision = 8; /* For ULAW */
1318 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1321 dbri->mm.data[0] |= 63;
1322 dbri->mm.data[1] |= 63;
1323 dbri->mm.data[2] &= ~15;
1324 dbri->mm.data[3] &= ~15;
1326 /* Start by setting the playback attenuation. */
1327 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1328 int left_gain = info->left_gain & 0x3f;
1329 int right_gain = info->right_gain & 0x3f;
1331 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1332 dbri->mm.data[1] &= ~0x3f;
1333 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1334 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1336 /* Now set the recording gain. */
1337 info = &dbri->stream_info[DBRI_REC];
1338 left_gain = info->left_gain & 0xf;
1339 right_gain = info->right_gain & 0xf;
1340 dbri->mm.data[2] |= CS4215_LG(left_gain);
1341 dbri->mm.data[3] |= CS4215_RG(right_gain);
1344 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1348 * Set the CS4215 to data mode.
1350 static void cs4215_open(struct snd_dbri * dbri)
1355 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1356 dbri->mm.channels, dbri->mm.precision);
1358 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1359 * to make sure this takes. This avoids clicking noises.
1362 cs4215_setdata(dbri, 1);
1367 * Pipe 4: Send timeslots 1-4 (audio data)
1368 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1369 * Pipe 6: Receive timeslots 1-4 (audio data)
1370 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1371 * interrupt, and the rest of the data (slot 5 and 8) is
1372 * not relevant for us (only for doublechecking).
1374 * Just like in control mode, the time slots are all offset by eight
1375 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1376 * even if it's the CHI master. Don't ask me...
1378 tmp = sbus_readl(dbri->regs + REG0);
1379 tmp &= ~(D_C); /* Disable CHI */
1380 sbus_writel(tmp, dbri->regs + REG0);
1382 /* Switch CS4215 to data mode - set PIO3 to 1 */
1383 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1384 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1386 reset_chi(dbri, CHIslave, 128);
1388 /* Note: this next doesn't work for 8-bit stereo, because the two
1389 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1390 * (See CS4215 datasheet Fig 15)
1392 * DBRI non-contiguous mode would be required to make this work.
1394 data_width = dbri->mm.channels * dbri->mm.precision;
1396 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1397 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1398 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1399 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1401 /* FIXME: enable CHI after _setdata? */
1402 tmp = sbus_readl(dbri->regs + REG0);
1403 tmp |= D_C; /* Enable CHI */
1404 sbus_writel(tmp, dbri->regs + REG0);
1406 cs4215_setdata(dbri, 0);
1410 * Send the control information (i.e. audio format)
1412 static int cs4215_setctrl(struct snd_dbri * dbri)
1417 /* FIXME - let the CPU do something useful during these delays */
1419 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1420 * to make sure this takes. This avoids clicking noises.
1422 cs4215_setdata(dbri, 1);
1426 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1427 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1429 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1430 sbus_writel(val, dbri->regs + REG2);
1431 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1434 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1435 * operate as CHI master, supplying clocking and frame synchronization.
1437 * In Data mode, however, the CS4215 must be CHI master to insure
1438 * that its data stream is synchronous with its codec.
1440 * The upshot of all this? We start by putting the DBRI into master
1441 * mode, program the CS4215 in Control mode, then switch the CS4215
1442 * into Data mode and put the DBRI into slave mode. Various timing
1443 * requirements must be observed along the way.
1445 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1446 * others?), the addressing of the CS4215's time slots is
1447 * offset by eight bits, so we add eight to all the "cycle"
1448 * values in the Define Time Slot (DTS) commands. This is
1449 * done in hardware by a TI 248 that delays the DBRI->4215
1450 * frame sync signal by eight clock cycles. Anybody know why?
1452 tmp = sbus_readl(dbri->regs + REG0);
1453 tmp &= ~D_C; /* Disable CHI */
1454 sbus_writel(tmp, dbri->regs + REG0);
1456 reset_chi(dbri, CHImaster, 128);
1460 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1461 * Pipe 18: Receive timeslot 1 (clb).
1462 * Pipe 19: Receive timeslot 7 (version).
1465 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1466 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1467 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1469 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1470 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1471 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1473 tmp = sbus_readl(dbri->regs + REG0);
1474 tmp |= D_C; /* Enable CHI */
1475 sbus_writel(tmp, dbri->regs + REG0);
1477 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1478 msleep_interruptible(1);
1481 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1486 /* Disable changes to our copy of the version number, as we are about
1487 * to leave control mode.
1489 recv_fixed(dbri, 19, NULL);
1491 /* Terminate CS4215 control mode - data sheet says
1492 * "Set CLB=1 and send two more frames of valid control info"
1494 dbri->mm.ctrl[0] |= CS4215_CLB;
1495 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1497 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1500 cs4215_setdata(dbri, 0);
1506 * Setup the codec with the sampling rate, audio format and number of
1508 * As part of the process we resend the settings for the data
1509 * timeslots as well.
1511 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1512 snd_pcm_format_t format, unsigned int channels)
1517 /* Lookup index for this rate */
1518 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1519 if (CS4215_FREQ[freq_idx].freq == rate)
1522 if (CS4215_FREQ[freq_idx].freq != rate) {
1523 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1528 case SNDRV_PCM_FORMAT_MU_LAW:
1529 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1530 dbri->mm.precision = 8;
1532 case SNDRV_PCM_FORMAT_A_LAW:
1533 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1534 dbri->mm.precision = 8;
1536 case SNDRV_PCM_FORMAT_U8:
1537 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1538 dbri->mm.precision = 8;
1540 case SNDRV_PCM_FORMAT_S16_BE:
1541 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1542 dbri->mm.precision = 16;
1545 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1549 /* Add rate parameters */
1550 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1551 dbri->mm.ctrl[2] = CS4215_XCLK |
1552 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1554 dbri->mm.channels = channels;
1556 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1558 ret = cs4215_setctrl(dbri);
1560 cs4215_open(dbri); /* set codec to data mode */
1568 static int cs4215_init(struct snd_dbri * dbri)
1570 u32 reg2 = sbus_readl(dbri->regs + REG2);
1571 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1573 /* Look for the cs4215 chips */
1574 if (reg2 & D_PIO2) {
1575 dprintk(D_MM, "Onboard CS4215 detected\n");
1576 dbri->mm.onboard = 1;
1578 if (reg2 & D_PIO0) {
1579 dprintk(D_MM, "Speakerbox detected\n");
1580 dbri->mm.onboard = 0;
1582 if (reg2 & D_PIO2) {
1583 printk(KERN_INFO "DBRI: Using speakerbox / "
1584 "ignoring onboard mmcodec.\n");
1585 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1589 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1590 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1594 cs4215_setup_pipes(dbri);
1595 cs4215_init_data(&dbri->mm);
1597 /* Enable capture of the status & version timeslots. */
1598 recv_fixed(dbri, 18, &dbri->mm.status);
1599 recv_fixed(dbri, 19, &dbri->mm.version);
1601 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1602 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1603 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1607 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1613 ****************************************************************************
1614 *************************** DBRI interrupt handler *************************
1615 ****************************************************************************
1617 The DBRI communicates with the CPU mainly via a circular interrupt
1618 buffer. When an interrupt is signaled, the CPU walks through the
1619 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1620 Complicated interrupts are handled by dedicated functions (which
1621 appear first in this file). Any pending interrupts can be serviced by
1622 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1623 interrupts are disabled.
1629 * Starts transmiting the current TD's for recording/playing.
1630 * For playback, ALSA has filled the DMA memory with new data (we hope).
1632 static void xmit_descs(struct snd_dbri *dbri)
1634 struct dbri_streaminfo *info;
1636 unsigned long flags;
1640 return; /* Disabled */
1642 /* First check the recording stream for buffer overflow */
1643 info = &dbri->stream_info[DBRI_REC];
1644 spin_lock_irqsave(&dbri->lock, flags);
1646 if (info->pipe >= 0) {
1647 first_td = dbri->pipes[info->pipe].first_desc;
1649 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1651 /* Stream could be closed by the time we run. */
1656 cmd = dbri_cmdlock(dbri, 2);
1657 *(cmd++) = DBRI_CMD(D_SDP, 0,
1658 dbri->pipes[info->pipe].sdp
1659 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1660 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1661 dbri_cmdsend(dbri, cmd, 2);
1663 /* Reset our admin of the pipe & bytes read. */
1664 dbri->pipes[info->pipe].desc = first_td;
1668 spin_unlock_irqrestore(&dbri->lock, flags);
1670 /* Now check the playback stream for buffer underflow */
1671 info = &dbri->stream_info[DBRI_PLAY];
1672 spin_lock_irqsave(&dbri->lock, flags);
1674 if (info->pipe >= 0) {
1675 first_td = dbri->pipes[info->pipe].first_desc;
1677 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1679 /* Stream could be closed by the time we run. */
1680 if (first_td >= 0) {
1681 cmd = dbri_cmdlock(dbri, 2);
1682 *(cmd++) = DBRI_CMD(D_SDP, 0,
1683 dbri->pipes[info->pipe].sdp
1684 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1685 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1686 dbri_cmdsend(dbri, cmd, 2);
1688 /* Reset our admin of the pipe & bytes written. */
1689 dbri->pipes[info->pipe].desc = first_td;
1692 spin_unlock_irqrestore(&dbri->lock, flags);
1695 /* transmission_complete_intr()
1697 * Called by main interrupt handler when DBRI signals transmission complete
1698 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1700 * Walks through the pipe's list of transmit buffer descriptors and marks
1701 * them as available. Stops when the first descriptor is found without
1702 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1704 * The DMA buffers are not released. They form a ring buffer and
1705 * they are filled by ALSA while others are transmitted by DMA.
1709 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1711 struct dbri_streaminfo *info;
1715 info = &dbri->stream_info[DBRI_PLAY];
1717 td = dbri->pipes[pipe].desc;
1719 if (td >= DBRI_NO_DESCS) {
1720 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1724 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1725 if (!(status & DBRI_TD_TBC)) {
1729 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1731 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1732 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1734 td = dbri->next_desc[td];
1735 dbri->pipes[pipe].desc = td;
1739 if (spin_is_locked(&dbri->lock)) {
1740 spin_unlock(&dbri->lock);
1741 snd_pcm_period_elapsed(info->substream);
1742 spin_lock(&dbri->lock);
1744 snd_pcm_period_elapsed(info->substream);
1747 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1749 struct dbri_streaminfo *info;
1750 int rd = dbri->pipes[pipe].desc;
1753 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1754 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1758 dbri->dma->desc[rd].ba = 0;
1759 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1760 status = dbri->dma->desc[rd].word1;
1761 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1763 info = &dbri->stream_info[DBRI_REC];
1764 info->offset += DBRI_RD_CNT(status);
1766 /* FIXME: Check status */
1768 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1769 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1771 /* On the last TD, transmit them all again. */
1773 if (dbri->next_desc[rd] == -1) {
1774 if (info->left > info->size) {
1776 "%d bytes recorded in %d size buffer.\n",
1777 info->left, info->size);
1779 tasklet_schedule(&xmit_descs_task);
1784 if (spin_is_locked(&dbri->lock)) {
1785 spin_unlock(&dbri->lock);
1786 snd_pcm_period_elapsed(info->substream);
1787 spin_lock(&dbri->lock);
1789 snd_pcm_period_elapsed(info->substream);
1792 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1794 int val = D_INTR_GETVAL(x);
1795 int channel = D_INTR_GETCHAN(x);
1796 int command = D_INTR_GETCMD(x);
1797 int code = D_INTR_GETCODE(x);
1799 int rval = D_INTR_GETRVAL(x);
1802 if (channel == D_INTR_CMD) {
1803 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1804 cmds[command], val);
1806 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1807 channel, code, rval);
1812 if (command != D_WAIT)
1813 printk(KERN_ERR "DBRI: Command read interrupt\n");
1816 reception_complete_intr(dbri, channel);
1820 transmission_complete_intr(dbri, channel);
1823 /* UNDR - Transmission underrun
1824 * resend SDP command with clear pipe bit (C) set
1827 /* FIXME: do something useful in case of underrun */
1828 printk(KERN_ERR "DBRI: Underrun error\n");
1832 int td = dbri->pipes[pipe].desc;
1834 dbri->dma->desc[td].word4 = 0;
1835 cmd = dbri_cmdlock(dbri, NoGetLock);
1836 *(cmd++) = DBRI_CMD(D_SDP, 0,
1837 dbri->pipes[pipe].sdp
1838 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1839 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1840 dbri_cmdsend(dbri, cmd);
1845 /* FXDT - Fixed data change */
1846 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1847 val = reverse_bytes(val, dbri->pipes[channel].length);
1849 if (dbri->pipes[channel].recv_fixed_ptr)
1850 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1853 if (channel != D_INTR_CMD)
1855 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1859 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1860 * buffer until it finds a zero word (indicating nothing more to do
1861 * right now). Non-zero words require processing and are handed off
1862 * to dbri_process_one_interrupt AFTER advancing the pointer.
1864 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1868 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1869 dbri->dma->intr[dbri->dbri_irqp] = 0;
1871 if (dbri->dbri_irqp == DBRI_INT_BLK)
1872 dbri->dbri_irqp = 1;
1874 dbri_process_one_interrupt(dbri, x);
1878 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1879 struct pt_regs *regs)
1881 struct snd_dbri *dbri = dev_id;
1882 static int errcnt = 0;
1887 spin_lock(&dbri->lock);
1890 * Read it, so the interrupt goes away.
1892 x = sbus_readl(dbri->regs + REG1);
1894 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1899 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1903 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1907 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1910 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1912 /* Some of these SBus errors cause the chip's SBus circuitry
1913 * to be disabled, so just re-enable and try to keep going.
1915 * The only one I've seen is MRR, which will be triggered
1916 * if you let a transmit pipe underrun, then try to CDP it.
1918 * If these things persist, we reset the chip.
1920 if ((++errcnt) % 10 == 0) {
1921 dprintk(D_INT, "Interrupt errors exceeded.\n");
1924 tmp = sbus_readl(dbri->regs + REG0);
1926 sbus_writel(tmp, dbri->regs + REG0);
1930 dbri_process_interrupt_buffer(dbri);
1932 spin_unlock(&dbri->lock);
1937 /****************************************************************************
1939 ****************************************************************************/
1940 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1941 .info = (SNDRV_PCM_INFO_MMAP |
1942 SNDRV_PCM_INFO_INTERLEAVED |
1943 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1944 SNDRV_PCM_INFO_MMAP_VALID),
1945 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1946 SNDRV_PCM_FMTBIT_A_LAW |
1947 SNDRV_PCM_FMTBIT_U8 |
1948 SNDRV_PCM_FMTBIT_S16_BE,
1949 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1954 .buffer_bytes_max = (64 * 1024),
1955 .period_bytes_min = 1,
1956 .period_bytes_max = DBRI_TD_MAXCNT,
1958 .periods_max = 1024,
1961 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1962 struct snd_pcm_hw_rule *rule)
1964 struct snd_interval *c = hw_param_interval(params,
1965 SNDRV_PCM_HW_PARAM_CHANNELS);
1966 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1967 struct snd_mask fmt;
1971 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
1972 return snd_mask_refine(f, &fmt);
1977 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
1978 struct snd_pcm_hw_rule *rule)
1980 struct snd_interval *c = hw_param_interval(params,
1981 SNDRV_PCM_HW_PARAM_CHANNELS);
1982 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1983 struct snd_interval ch;
1985 snd_interval_any(&ch);
1986 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
1987 ch.min = ch.max = 1;
1989 return snd_interval_refine(c, &ch);
1994 static int snd_dbri_open(struct snd_pcm_substream *substream)
1996 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
1997 struct snd_pcm_runtime *runtime = substream->runtime;
1998 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
1999 unsigned long flags;
2001 dprintk(D_USR, "open audio output.\n");
2002 runtime->hw = snd_dbri_pcm_hw;
2004 spin_lock_irqsave(&dbri->lock, flags);
2005 info->substream = substream;
2007 info->dvma_buffer = 0;
2009 spin_unlock_irqrestore(&dbri->lock, flags);
2011 snd_pcm_hw_rule_add(runtime,0,SNDRV_PCM_HW_PARAM_CHANNELS,
2012 snd_hw_rule_format, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2014 snd_pcm_hw_rule_add(runtime,0,SNDRV_PCM_HW_PARAM_FORMAT,
2015 snd_hw_rule_channels, 0,
2016 SNDRV_PCM_HW_PARAM_CHANNELS,
2024 static int snd_dbri_close(struct snd_pcm_substream *substream)
2026 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2027 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2029 dprintk(D_USR, "close audio output.\n");
2030 info->substream = NULL;
2036 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2037 struct snd_pcm_hw_params *hw_params)
2039 struct snd_pcm_runtime *runtime = substream->runtime;
2040 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2041 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2045 /* set sampling rate, audio format and number of channels */
2046 ret = cs4215_prepare(dbri, params_rate(hw_params),
2047 params_format(hw_params),
2048 params_channels(hw_params));
2052 if ((ret = snd_pcm_lib_malloc_pages(substream,
2053 params_buffer_bytes(hw_params))) < 0) {
2054 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2058 /* hw_params can get called multiple times. Only map the DMA once.
2060 if (info->dvma_buffer == 0) {
2061 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2062 direction = SBUS_DMA_TODEVICE;
2064 direction = SBUS_DMA_FROMDEVICE;
2066 info->dvma_buffer = sbus_map_single(dbri->sdev,
2068 params_buffer_bytes(hw_params),
2072 direction = params_buffer_bytes(hw_params);
2073 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2074 direction, info->dvma_buffer);
2078 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2080 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2081 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2083 dprintk(D_USR, "hw_free.\n");
2085 /* hw_free can get called multiple times. Only unmap the DMA once.
2087 if (info->dvma_buffer) {
2088 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2089 direction = SBUS_DMA_TODEVICE;
2091 direction = SBUS_DMA_FROMDEVICE;
2093 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2094 substream->runtime->buffer_size, direction);
2095 info->dvma_buffer = 0;
2099 return snd_pcm_lib_free_pages(substream);
2102 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2104 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2105 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2106 struct snd_pcm_runtime *runtime = substream->runtime;
2109 info->size = snd_pcm_lib_buffer_bytes(substream);
2110 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2111 info->pipe = 4; /* Send pipe */
2113 info->pipe = 6; /* Receive pipe */
2115 spin_lock_irq(&dbri->lock);
2117 /* Setup the all the transmit/receive desciptors to cover the
2120 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2121 snd_pcm_lib_period_bytes(substream));
2123 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
2125 spin_unlock_irq(&dbri->lock);
2127 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2131 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2133 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2134 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2138 case SNDRV_PCM_TRIGGER_START:
2139 dprintk(D_USR, "start audio, period is %d bytes\n",
2140 (int)snd_pcm_lib_period_bytes(substream));
2141 /* Re-submit the TDs. */
2144 case SNDRV_PCM_TRIGGER_STOP:
2145 dprintk(D_USR, "stop audio.\n");
2146 reset_pipe(dbri, info->pipe);
2155 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2157 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2158 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2159 snd_pcm_uframes_t ret;
2161 ret = bytes_to_frames(substream->runtime, info->offset)
2162 % substream->runtime->buffer_size;
2163 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2164 ret, substream->runtime->buffer_size);
2168 static struct snd_pcm_ops snd_dbri_ops = {
2169 .open = snd_dbri_open,
2170 .close = snd_dbri_close,
2171 .ioctl = snd_pcm_lib_ioctl,
2172 .hw_params = snd_dbri_hw_params,
2173 .hw_free = snd_dbri_hw_free,
2174 .prepare = snd_dbri_prepare,
2175 .trigger = snd_dbri_trigger,
2176 .pointer = snd_dbri_pointer,
2179 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2181 struct snd_pcm *pcm;
2184 if ((err = snd_pcm_new(dbri->card,
2185 /* ID */ "sun_dbri",
2187 /* playback count */ 1,
2188 /* capture count */ 1, &pcm)) < 0)
2190 snd_assert(pcm != NULL, return -EINVAL);
2192 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2193 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2195 pcm->private_data = dbri;
2196 pcm->info_flags = 0;
2197 strcpy(pcm->name, dbri->card->shortname);
2199 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2200 SNDRV_DMA_TYPE_CONTINUOUS,
2201 snd_dma_continuous_data(GFP_KERNEL),
2202 64 * 1024, 64 * 1024)) < 0) {
2209 /*****************************************************************************
2211 *****************************************************************************/
2213 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2214 struct snd_ctl_elem_info *uinfo)
2216 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2218 uinfo->value.integer.min = 0;
2219 if (kcontrol->private_value == DBRI_PLAY) {
2220 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2222 uinfo->value.integer.max = DBRI_MAX_GAIN;
2227 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2228 struct snd_ctl_elem_value *ucontrol)
2230 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2231 struct dbri_streaminfo *info;
2232 snd_assert(dbri != NULL, return -EINVAL);
2233 info = &dbri->stream_info[kcontrol->private_value];
2234 snd_assert(info != NULL, return -EINVAL);
2236 ucontrol->value.integer.value[0] = info->left_gain;
2237 ucontrol->value.integer.value[1] = info->right_gain;
2241 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2242 struct snd_ctl_elem_value *ucontrol)
2244 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2245 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2246 unsigned long flags;
2249 if (info->left_gain != ucontrol->value.integer.value[0]) {
2250 info->left_gain = ucontrol->value.integer.value[0];
2253 if (info->right_gain != ucontrol->value.integer.value[1]) {
2254 info->right_gain = ucontrol->value.integer.value[1];
2258 /* First mute outputs, and wait 1/8000 sec (125 us)
2259 * to make sure this takes. This avoids clicking noises.
2261 spin_lock_irqsave(&dbri->lock, flags);
2263 cs4215_setdata(dbri, 1);
2265 cs4215_setdata(dbri, 0);
2267 spin_unlock_irqrestore(&dbri->lock, flags);
2272 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2273 struct snd_ctl_elem_info *uinfo)
2275 int mask = (kcontrol->private_value >> 16) & 0xff;
2277 uinfo->type = (mask == 1) ?
2278 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2280 uinfo->value.integer.min = 0;
2281 uinfo->value.integer.max = mask;
2285 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2286 struct snd_ctl_elem_value *ucontrol)
2288 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2289 int elem = kcontrol->private_value & 0xff;
2290 int shift = (kcontrol->private_value >> 8) & 0xff;
2291 int mask = (kcontrol->private_value >> 16) & 0xff;
2292 int invert = (kcontrol->private_value >> 24) & 1;
2293 snd_assert(dbri != NULL, return -EINVAL);
2296 ucontrol->value.integer.value[0] =
2297 (dbri->mm.data[elem] >> shift) & mask;
2299 ucontrol->value.integer.value[0] =
2300 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2304 ucontrol->value.integer.value[0] =
2305 mask - ucontrol->value.integer.value[0];
2310 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2311 struct snd_ctl_elem_value *ucontrol)
2313 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2314 unsigned long flags;
2315 int elem = kcontrol->private_value & 0xff;
2316 int shift = (kcontrol->private_value >> 8) & 0xff;
2317 int mask = (kcontrol->private_value >> 16) & 0xff;
2318 int invert = (kcontrol->private_value >> 24) & 1;
2321 snd_assert(dbri != NULL, return -EINVAL);
2323 val = (ucontrol->value.integer.value[0] & mask);
2329 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2330 ~(mask << shift)) | val;
2331 changed = (val != dbri->mm.data[elem]);
2333 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2334 ~(mask << shift)) | val;
2335 changed = (val != dbri->mm.ctrl[elem - 4]);
2338 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2339 "mixer-value=%ld, mm-value=0x%x\n",
2340 mask, changed, ucontrol->value.integer.value[0],
2341 dbri->mm.data[elem & 3]);
2344 /* First mute outputs, and wait 1/8000 sec (125 us)
2345 * to make sure this takes. This avoids clicking noises.
2347 spin_lock_irqsave(&dbri->lock, flags);
2349 cs4215_setdata(dbri, 1);
2351 cs4215_setdata(dbri, 0);
2353 spin_unlock_irqrestore(&dbri->lock, flags);
2358 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2359 timeslots. Shift is the bit offset in the timeslot, mask defines the
2360 number of bits. invert is a boolean for use with attenuation.
2362 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2363 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2364 .info = snd_cs4215_info_single, \
2365 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2366 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2368 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2370 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2371 .name = "Playback Volume",
2372 .info = snd_cs4215_info_volume,
2373 .get = snd_cs4215_get_volume,
2374 .put = snd_cs4215_put_volume,
2375 .private_value = DBRI_PLAY,
2377 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2378 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2379 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2381 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2382 .name = "Capture Volume",
2383 .info = snd_cs4215_info_volume,
2384 .get = snd_cs4215_get_volume,
2385 .put = snd_cs4215_put_volume,
2386 .private_value = DBRI_REC,
2388 /* FIXME: mic/line switch */
2389 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2390 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2391 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2392 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2395 #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
2397 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2399 struct snd_card *card;
2402 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2405 strcpy(card->mixername, card->shortname);
2407 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2408 if ((err = snd_ctl_add(card,
2409 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2413 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2414 dbri->stream_info[idx].left_gain = 0;
2415 dbri->stream_info[idx].right_gain = 0;
2421 /****************************************************************************
2423 ****************************************************************************/
2424 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2426 struct snd_dbri *dbri = entry->private_data;
2428 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2429 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2430 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2431 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2435 static void dbri_debug_read(struct snd_info_entry * entry,
2436 struct snd_info_buffer *buffer)
2438 struct snd_dbri *dbri = entry->private_data;
2440 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2442 for (pipe = 0; pipe < 32; pipe++) {
2443 if (pipe_active(dbri, pipe)) {
2444 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2446 "Pipe %d: %s SDP=0x%x desc=%d, "
2449 ((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
2450 pptr->sdp, pptr->desc,
2451 pptr->length, pptr->nextpipe);
2457 void snd_dbri_proc(struct snd_dbri * dbri)
2459 struct snd_info_entry *entry;
2461 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2462 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2465 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2466 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2467 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2473 ****************************************************************************
2474 **************************** Initialization ********************************
2475 ****************************************************************************
2477 static void snd_dbri_free(struct snd_dbri * dbri);
2479 static int __init snd_dbri_create(struct snd_card *card,
2480 struct sbus_dev *sdev,
2481 struct linux_prom_irqs *irq, int dev)
2483 struct snd_dbri *dbri = card->private_data;
2486 spin_lock_init(&dbri->lock);
2489 dbri->irq = irq->pri;
2491 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2493 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2495 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2496 dbri->dma, dbri->dma_dvma);
2498 /* Map the registers into memory. */
2499 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2500 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2501 dbri->regs_size, "DBRI Registers");
2503 printk(KERN_ERR "DBRI: could not allocate registers\n");
2504 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2505 (void *)dbri->dma, dbri->dma_dvma);
2509 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2510 "DBRI audio", dbri);
2512 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2513 sbus_iounmap(dbri->regs, dbri->regs_size);
2514 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2515 (void *)dbri->dma, dbri->dma_dvma);
2519 /* Do low level initialization of the DBRI and CS4215 chips */
2520 dbri_initialize(dbri);
2521 err = cs4215_init(dbri);
2523 snd_dbri_free(dbri);
2527 dbri->next = dbri_list;
2533 static void snd_dbri_free(struct snd_dbri * dbri)
2535 dprintk(D_GEN, "snd_dbri_free\n");
2539 free_irq(dbri->irq, dbri);
2542 sbus_iounmap(dbri->regs, dbri->regs_size);
2545 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2546 (void *)dbri->dma, dbri->dma_dvma);
2549 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2551 struct snd_dbri *dbri;
2552 struct linux_prom_irqs irq;
2553 struct resource *rp;
2554 struct snd_card *card;
2558 if (sdev->prom_name[9] < 'e') {
2559 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2560 sdev->prom_name[9]);
2564 if (dev >= SNDRV_CARDS)
2571 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2573 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2577 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2578 sizeof(struct snd_dbri));
2582 strcpy(card->driver, "DBRI");
2583 strcpy(card->shortname, "Sun DBRI");
2584 rp = &sdev->resource[0];
2585 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2587 rp->flags & 0xffL, (unsigned long long)rp->start, irq.pri);
2589 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2590 snd_card_free(card);
2594 dbri = card->private_data;
2595 if ((err = snd_dbri_pcm(dbri)) < 0)
2598 if ((err = snd_dbri_mixer(dbri)) < 0)
2601 /* /proc file handling */
2602 snd_dbri_proc(dbri);
2604 if ((err = snd_card_register(card)) < 0)
2607 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2609 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2615 snd_dbri_free(dbri);
2616 snd_card_free(card);
2620 /* Probe for the dbri chip and then attach the driver. */
2621 static int __init dbri_init(void)
2623 struct sbus_bus *sbus;
2624 struct sbus_dev *sdev;
2627 /* Probe each SBUS for the DBRI chip(s). */
2628 for_all_sbusdev(sdev, sbus) {
2630 * The version is coded in the last character
2632 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2633 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2634 sdev->prom_name, sdev->slot);
2636 if (dbri_attach(sdev->prom_node, sdev) == 0)
2641 return (found > 0) ? 0 : -EIO;
2644 static void __exit dbri_exit(void)
2646 struct snd_dbri *this = dbri_list;
2648 while (this != NULL) {
2649 struct snd_dbri *next = this->next;
2650 struct snd_card *card = this->card;
2652 snd_dbri_free(this);
2653 snd_card_free(card);
2659 module_init(dbri_init);
2660 module_exit(dbri_exit);