+/* DMA Clocks */
+static struct clk clk_m2p0 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00020000,
+};
+static struct clk clk_m2p1 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00010000,
+};
+static struct clk clk_m2p2 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00080000,
+};
+static struct clk clk_m2p3 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00040000,
+};
+static struct clk clk_m2p4 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00200000,
+};
+static struct clk clk_m2p5 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00100000,
+};
+static struct clk clk_m2p6 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00800000,
+};
+static struct clk clk_m2p7 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x00400000,
+};
+static struct clk clk_m2p8 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x02000000,
+};
+static struct clk clk_m2p9 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x01000000,
+};
+static struct clk clk_m2m0 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x04000000,
+};
+static struct clk clk_m2m1 = {
+ .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
+ .enable_mask = 0x08000000,
+};
+