Merge branch 'for-2.6.28' of git://linux-nfs.org/~bfields/linux

[linux-2.6-omap-h63xx.git] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 4154ff1101fa1aa53f9f4941941e3f7b47f01064..29e71ed6b8a7fb9c5e4b8381244a4c3d5b1d47db 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -64,8 +64,11 @@ config HARDWARE_PM
        depends on OPROFILE
 
 source "init/Kconfig"
        depends on OPROFILE
 
 source "init/Kconfig"

+

 source "kernel/Kconfig.preempt"
 
 source "kernel/Kconfig.preempt"
 

+source "kernel/Kconfig.freezer"
+

 menu "Blackfin Processor Options"
 
 comment "Processor and Board Settings"
 menu "Blackfin Processor Options"
 
 comment "Processor and Board Settings"


@@ -162,16 +165,28 @@ config BF549
 config BF561
        bool "BF561"
        help
 config BF561
        bool "BF561"
        help

-         Not Supported Yet - Work in progress - BF561 Processor Support.
+         BF561 Processor Support.

 
 endchoice
 
 
 endchoice
 

+config BF_REV_MIN
+       int
+       default 0 if (BF52x || BF54x)
+       default 2 if (BF537 || BF536 || BF534)
+       default 3 if (BF561 ||BF533 || BF532 || BF531)
+
+config BF_REV_MAX
+       int
+       default 2 if (BF52x || BF54x)
+       default 3 if (BF537 || BF536 || BF534)
+       default 5 if (BF561)
+       default 6 if (BF533 || BF532 || BF531)
+

 choice
        prompt "Silicon Rev"
 choice
        prompt "Silicon Rev"

-       default BF_REV_0_1 if BF527
-       default BF_REV_0_2 if BF537
-       default BF_REV_0_3 if BF533
-       default BF_REV_0_0 if BF549
+       default BF_REV_0_1 if (BF52x || BF54x)
+       default BF_REV_0_2 if (BF534 || BF536 || BF537)
+       default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)

 
 config BF_REV_0_0
        bool "0.0"
 
 config BF_REV_0_0
        bool "0.0"


@@ -183,7 +198,7 @@ config BF_REV_0_1
 
 config BF_REV_0_2
        bool "0.2"
 
 config BF_REV_0_2
        bool "0.2"

-       depends on (BF537 || BF536 || BF534)
+       depends on (BF52x || BF537 || BF536 || BF534 || BF54x)

 
 config BF_REV_0_3
        bool "0.3"
 
 config BF_REV_0_3
        bool "0.3"


@@ -197,6 +212,10 @@ config BF_REV_0_5
        bool "0.5"
        depends on (BF561 || BF533 || BF532 || BF531)
 
        bool "0.5"
        depends on (BF561 || BF533 || BF532 || BF531)
 

+config BF_REV_0_6
+       bool "0.6"
+       depends on (BF533 || BF532 || BF531)
+

 config BF_REV_ANY
        bool "any"
 
 config BF_REV_ANY
        bool "any"
 


@@ -249,7 +268,7 @@ config MEM_MT48LC8M32B2B5_7
 
 config MEM_MT48LC32M16A2TG_75
        bool
 
 config MEM_MT48LC32M16A2TG_75
        bool

-       depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
+       depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)

        default y
 
 source "arch/blackfin/mach-bf527/Kconfig"
        default y
 
 source "arch/blackfin/mach-bf527/Kconfig"


@@ -286,13 +305,20 @@ config BOOT_LOAD
          memory region is used to capture NULL pointer references as well
          as some core kernel functions.
 
          memory region is used to capture NULL pointer references as well
          as some core kernel functions.
 

+config ROM_BASE
+       hex "Kernel ROM Base"
+       default "0x20040000"
+       range 0x20000000 0x20400000 if !(BF54x || BF561)
+       range 0x20000000 0x30000000 if (BF54x || BF561)
+       help
+

 comment "Clock/PLL Setup"
 
 config CLKIN_HZ
        int "Frequency of the crystal on the board in Hz"
        default "11059200" if BFIN533_STAMP
        default "27000000" if BFIN533_EZKIT
 comment "Clock/PLL Setup"
 
 config CLKIN_HZ
        int "Frequency of the crystal on the board in Hz"
        default "11059200" if BFIN533_STAMP
        default "27000000" if BFIN533_EZKIT

-       default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP)
+       default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)

        default "30000000" if BFIN561_EZKIT
        default "24576000" if PNAV10
        default "10000000" if BFIN532_IP0X
        default "30000000" if BFIN561_EZKIT
        default "24576000" if PNAV10
        default "10000000" if BFIN532_IP0X


@@ -332,7 +358,7 @@ config VCO_MULT
        default "22" if BFIN533_BLUETECHNIX_CM
        default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
        default "20" if BFIN561_EZKIT
        default "22" if BFIN533_BLUETECHNIX_CM
        default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
        default "20" if BFIN561_EZKIT

-       default "16" if (H8606_HVSISTEMAS || BLACKSTAMP)
+       default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)

        help
          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
          PLL Frequency = (Crystal Frequency) * (this setting)
        help
          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
          PLL Frequency = (Crystal Frequency) * (this setting)


@@ -368,14 +394,6 @@ config SCLK_DIV
          This can be between 1 and 15
          System Clock = (PLL frequency) / (this setting)
 
          This can be between 1 and 15
          System Clock = (PLL frequency) / (this setting)
 

-config MAX_MEM_SIZE
-       int "Max SDRAM Memory Size in MBytes"
-       depends on !MPU
-       default 512
-       help
-         This is the max memory size that the kernel will create CPLB
-         tables for.  Your system will not be able to handle any more.
-

 choice
        prompt "DDR SDRAM Chip Type"
        depends on BFIN_KERNEL_CLOCK
 choice
        prompt "DDR SDRAM Chip Type"
        depends on BFIN_KERNEL_CLOCK


@@ -389,6 +407,14 @@ config MEM_MT46V32M16_5B
        bool "MT46V32M16_5B"
 endchoice
 
        bool "MT46V32M16_5B"
 endchoice
 

+config MAX_MEM_SIZE
+       int "Max SDRAM Memory Size in MBytes"
+       depends on !MPU
+       default 512
+       help
+         This is the max memory size that the kernel will create CPLB
+         tables for.  Your system will not be able to handle any more.
+

 #
 # Max & Min Speeds for various Chips
 #
 #
 # Max & Min Speeds for various Chips
 #


@@ -455,8 +481,6 @@ config CYCLES_CLOCKSOURCE
 
 source kernel/time/Kconfig
 
 
 source kernel/time/Kconfig
 

-comment "Memory Setup"
-

 comment "Misc"
 
 choice
 comment "Misc"
 
 choice


@@ -622,6 +646,15 @@ config CPLB_SWITCH_TAB_L1
          If enabled, the CPLB Switch Tables are linked
          into L1 data memory. (less latency)
 
          If enabled, the CPLB Switch Tables are linked
          into L1 data memory. (less latency)
 

+config APP_STACK_L1
+       bool "Support locating application stack in L1 Scratch Memory"
+       default y
+       help
+         If enabled the application stack can be located in L1
+         scratch memory (less latency).
+
+         Currently only works with FLAT binaries.
+

 comment "Speed Optimizations"
 config BFIN_INS_LOWOVERHEAD
        bool "ins[bwl] low overhead, higher interrupt latency"
 comment "Speed Optimizations"
 config BFIN_INS_LOWOVERHEAD
        bool "ins[bwl] low overhead, higher interrupt latency"


@@ -755,6 +788,13 @@ config BFIN_WT
 
 endchoice
 
 
 endchoice
 

+config BFIN_L2_CACHEABLE
+       bool "Cache L2 SRAM"
+       depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
+       default n
+       help
+         Select to make L2 SRAM cacheable in L1 data and instruction cache.
+

 config MPU
        bool "Enable the memory protection unit (EXPERIMENTAL)"
        default n
 config MPU
        bool "Enable the memory protection unit (EXPERIMENTAL)"
        default n