+#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
+static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
+{
+ unsigned int fcr_val = 0;
+ unsigned short data;
+
+ if (cflag & CRTSCTS) {
+ /* enable RTS/CTS */
+ if (port->mapbase == 0xa4430000) { /* SCIF0 */
+ /* Clear PTCR bit 9-2; enable all scif pins but sck */
+ data = ctrl_inw(PORT_PTCR);
+ ctrl_outw((data & 0xfc03), PORT_PTCR);
+ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
+ /* Clear PVCR bit 9-2 */
+ data = ctrl_inw(PORT_PVCR);
+ ctrl_outw((data & 0xfc03), PORT_PVCR);
+ }
+ fcr_val |= SCFCR_MCE;
+ } else {
+ if (port->mapbase == 0xa4430000) { /* SCIF0 */
+ /* Clear PTCR bit 5-2; enable only tx and rx */
+ data = ctrl_inw(PORT_PTCR);
+ ctrl_outw((data & 0xffc3), PORT_PTCR);
+ } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
+ /* Clear PVCR bit 5-2 */
+ data = ctrl_inw(PORT_PVCR);
+ ctrl_outw((data & 0xffc3), PORT_PVCR);
+ }
+ }
+ sci_out(port, SCFCR, fcr_val);
+}
+