-#define mtc0_tlbw_hazard() \
- __asm__ __volatile__( \
- " .set mips32 \n" \
- " _ssnop \n" \
- " _ssnop \n" \
- " _ssnop \n" \
- " _ssnop \n" \
- " .set mips0 \n")
-
-#define tlbw_use_hazard() \
- __asm__ __volatile__( \
- " .set mips32 \n" \
- " _ssnop \n" \
- " _ssnop \n" \
- " _ssnop \n" \
- " _ssnop \n" \
- " .set mips0 \n")
-
-#else
-
-/*
- * Overkill warning ...
- */
-#define mtc0_tlbw_hazard() \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " .set reorder \n")
-
-#define tlbw_use_hazard() \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " nop \n" \
- " .set reorder \n")
-
-#endif
-
-/*
- * Interrupt enable/disable hazards
- * Some processors have hazards when modifying
- * the status register to change the interrupt state
- */
-
-#ifdef CONFIG_CPU_MIPSR2
-
-__asm__(" .macro irq_enable_hazard \n"
- " _ehb \n"
- " .endm \n"
- " \n"
- " .macro irq_disable_hazard \n"
- " _ehb \n"
- " .endm \n");
+ASMMACRO(mtc0_tlbw_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(tlbw_use_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(tlb_probe_hazard,
+ _ssnop; _ssnop; _ssnop; _ssnop
+ )
+ASMMACRO(irq_enable_hazard,
+ )
+ASMMACRO(irq_disable_hazard,
+ )
+ASMMACRO(back_to_back_c0_hazard,
+ )
+#define instruction_hazard() do { } while (0)