[ARM] add ARMv5TEJ aware cache flush method to compressed/head.S

[linux-2.6-omap-h63xx.git] / arch / arm / boot / compressed / head.S

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b9b03eda70e5a370b02b3c276cd9db69405af3d7..2073bf0805234a49e1a2b34d9b625311561ce63c 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -31,7 +31,7 @@
                .macro  loadsp, rb
                .endm
                .macro  writeb, ch, rb
-               mcr     p14, 0, \ch, c0, c1, 0
+               mcr     p14, 0, \ch, c1, c0, 0
                .endm
 #endif
 
@@ -641,7 +641,7 @@ proc_types:
                .word   0x000f0000
                b       __armv4_mmu_cache_on
                b       __armv4_mmu_cache_off
-               b       __armv4_mmu_cache_flush
+               b       __armv5tej_mmu_cache_flush
 
                .word   0x0007b000              @ ARMv6
                .word   0x000ff000
@@ -821,6 +821,13 @@ iflush:
                mcr     p15, 0, r10, c7, c10, 4 @ drain WB
                mov     pc, lr
 
+__armv5tej_mmu_cache_flush:
+1:             mrc     p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
+               bne     1b
+               mcr     p15, 0, r0, c7, c5, 0   @ flush I cache
+               mcr     p15, 0, r0, c7, c10, 4  @ drain WB
+               mov     pc, lr
+
 __armv4_mmu_cache_flush:
                mov     r2, #64*1024            @ default: 32K dcache size (*2)
                mov     r11, #32                @ default: 32 byte line size