Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

[linux-2.6-omap-h63xx.git] / arch / arm / boot / compressed / head.S

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 84a1e0496a3c6ffb7b1adbfa38182341ca943c27..b371fba1b954ce73bb9a881bde9575407b1d0669 100644 (file)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -27,6 +27,12 @@
                .macro  writeb, ch, rb
                mcr     p14, 0, \ch, c0, c5, 0
                .endm
+#elif defined(CONFIG_CPU_XSCALE)
+               .macro  loadsp, rb
+               .endm
+               .macro  writeb, ch, rb
+               mcr     p14, 0, \ch, c8, c0, 0
+               .endm
 #else
                .macro  loadsp, rb
                .endm
@@ -459,6 +465,20 @@ __armv7_mmu_cache_on:
                mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mov     pc, r12
 
+__fa526_cache_on:
+               mov     r12, lr
+               bl      __setup_mmu
+               mov     r0, #0
+               mcr     p15, 0, r0, c7, c7, 0   @ Invalidate whole cache
+               mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
+               mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+               mrc     p15, 0, r0, c1, c0, 0   @ read control reg
+               orr     r0, r0, #0x1000         @ I-cache enable
+               bl      __common_mmu_cache_on
+               mov     r0, #0
+               mcr     p15, 0, r0, c8, c7, 0   @ flush UTLB
+               mov     pc, r12
+
 __arm6_mmu_cache_on:
                mov     r12, lr
                bl      __setup_mmu
@@ -624,12 +644,36 @@ proc_types:
                b       __armv4_mmu_cache_off
                b       __armv4_mmu_cache_flush
 
+               .word   0x56056930
+               .word   0xff0ffff0              @ PXA935
+               b       __armv4_mmu_cache_on
+               b       __armv4_mmu_cache_off
+               b       __armv4_mmu_cache_flush
+
+               .word   0x56158000              @ PXA168
+               .word   0xfffff000
+               b __armv4_mmu_cache_on
+               b __armv4_mmu_cache_off
+               b __armv5tej_mmu_cache_flush
+
+               .word   0x56056930
+               .word   0xff0ffff0              @ PXA935
+               b       __armv4_mmu_cache_on
+               b       __armv4_mmu_cache_off
+               b       __armv4_mmu_cache_flush
+
                .word   0x56050000              @ Feroceon
                .word   0xff0f0000
                b       __armv4_mmu_cache_on
                b       __armv4_mmu_cache_off
                b       __armv5tej_mmu_cache_flush
 
+               .word   0x66015261              @ FA526
+               .word   0xff01fff1
+               b       __fa526_cache_on
+               b       __armv4_mmu_cache_off
+               b       __fa526_cache_flush
+
                @ These match on the architecture ID
 
                .word   0x00020000              @ ARMv4T
@@ -717,6 +761,9 @@ __armv7_mmu_cache_off:
                bl      __armv7_mmu_cache_flush
                mov     r0, #0
                mcr     p15, 0, r0, c8, c7, 0   @ invalidate whole TLB
+               mcr     p15, 0, r0, c7, c5, 6   @ invalidate BTC
+               mcr     p15, 0, r0, c7, c10, 4  @ DSB
+               mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mov     pc, r12
 
 __arm6_mmu_cache_off:
@@ -766,6 +813,12 @@ __armv4_mpu_cache_flush:
                mcr     p15, 0, ip, c7, c10, 4  @ drain WB
                mov     pc, lr
                
+__fa526_cache_flush:
+               mov     r1, #0
+               mcr     p15, 0, r1, c7, c14, 0  @ clean and invalidate D cache
+               mcr     p15, 0, r1, c7, c5, 0   @ flush I cache
+               mcr     p15, 0, r1, c7, c10, 4  @ drain WB
+               mov     pc, lr
 
 __armv6_mmu_cache_flush:
                mov     r1, #0
@@ -778,12 +831,13 @@ __armv6_mmu_cache_flush:
 __armv7_mmu_cache_flush:
                mrc     p15, 0, r10, c0, c1, 5  @ read ID_MMFR1
                tst     r10, #0xf << 16         @ hierarchical cache (ARMv7)
-               beq     hierarchical
                mov     r10, #0
+               beq     hierarchical
                mcr     p15, 0, r10, c7, c14, 0 @ clean+invalidate D
                b       iflush
 hierarchical:
-               stmfd   sp!, {r0-r5, r7, r9-r11}
+               mcr     p15, 0, r10, c7, c10, 5 @ DMB
+               stmfd   sp!, {r0-r5, r7, r9, r11}
                mrc     p15, 1, r0, c0, c0, 1   @ read clidr
                ands    r3, r0, #0x7000000      @ extract loc from clidr
                mov     r3, r3, lsr #23         @ left align loc bit field
@@ -820,12 +874,14 @@ skip:
                cmp     r3, r10
                bgt     loop1
 finished:
+               ldmfd   sp!, {r0-r5, r7, r9, r11}
                mov     r10, #0                 @ swith back to cache level 0
                mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
-               ldmfd   sp!, {r0-r5, r7, r9-r11}
 iflush:
+               mcr     p15, 0, r10, c7, c10, 4 @ DSB
                mcr     p15, 0, r10, c7, c5, 0  @ invalidate I+BTB
-               mcr     p15, 0, r10, c7, c10, 4 @ drain WB
+               mcr     p15, 0, r10, c7, c10, 4 @ DSB
+               mcr     p15, 0, r10, c7, c5, 4  @ ISB
                mov     pc, lr
 
 __armv5tej_mmu_cache_flush: