[ARM] pxa: add default config for littleton

[linux-2.6-omap-h63xx.git] / arch / arm / mach-at91 / clock.c

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 27e7279b5b39bdd933aaa07f7d31a368414a0a15..57c3b647ce834f06a790f04f48d18b11e7fd5d65 100644 (file)
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -351,7 +351,7 @@ static void init_programmable_clock(struct clk *clk)
        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
        parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
        clk->parent = parent;
-       clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
+       clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 }
 
 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -364,19 +364,14 @@ static int at91_clk_show(struct seq_file *s, void *unused)
 {
        u32             scsr, pcsr, sr;
        struct clk      *clk;
-       unsigned        i;
 
        seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
        seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
-
        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
        seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-
        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
-       for (i = 0; i < 4; i++)
-               seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 
        seq_printf(s, "\n");
@@ -407,7 +402,7 @@ static int at91_clk_open(struct inode *inode, struct file *file)
        return single_open(file, at91_clk_show, NULL);
 }
 
-static struct file_operations at91_clk_operations = {
+static const struct file_operations at91_clk_operations = {
        .open           = at91_clk_open,
        .read           = seq_read,
        .llseek         = seq_lseek,
@@ -525,27 +520,6 @@ fail:
        return 0;
 }
 
-/*
- * Several unused clocks may be active.  Turn them off.
- */
-static void __init at91_periphclk_reset(void)
-{
-       unsigned long reg;
-       struct clk *clk;
-
-       reg = at91_sys_read(AT91_PMC_PCSR);
-
-       list_for_each_entry(clk, &clocks, node) {
-               if (clk->mode != pmc_periph_mode)
-                       continue;
-
-               if (clk->users > 0)
-                       reg &= ~clk->pmc_mask;
-       }
-
-       at91_sys_write(AT91_PMC_PCDR, reg);
-}
-
 static struct clk *const standard_pmc_clocks[] __initdata = {
        /* four primary clocks */
        &clk32k,
@@ -586,7 +560,7 @@ int __init at91_clock_init(unsigned long main_clock)
                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 
        /*
-        * USB clock init:  choose 48 MHz PLLB value, turn all clocks off,
+        * USB clock init:  choose 48 MHz PLLB value,
         * disable 48MHz clock during usb peripheral suspend.
         *
         * REVISIT:  assumes MCK doesn't derive from PLLB!
@@ -596,16 +570,10 @@ int __init at91_clock_init(unsigned long main_clock)
        if (cpu_is_at91rm9200()) {
                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                udpck.pmc_mask = AT91RM9200_PMC_UDP;
-               at91_sys_write(AT91_PMC_SCDR, AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP);
                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-       } else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) {
+       } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-               at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP);
-       } else if (cpu_is_at91sam9261()) {
-               uhpck.pmc_mask = (AT91SAM926x_PMC_UHP | AT91_PMC_HCK0);
-               udpck.pmc_mask = AT91SAM926x_PMC_UDP;
-               at91_sys_write(AT91_PMC_SCDR, AT91SAM926x_PMC_UHP | AT91_PMC_HCK0 | AT91SAM926x_PMC_UDP);
        }
        at91_sys_write(AT91_CKGR_PLLBR, 0);
 
@@ -619,8 +587,11 @@ int __init at91_clock_init(unsigned long main_clock)
        mckr = at91_sys_read(AT91_PMC_MCKR);
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
-       freq /= (1 << ((mckr >> 2) & 3));               /* prescale */
-       mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));   /* mdiv */
+       freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
+       if (cpu_is_at91rm9200())
+               mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
+       else
+               mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 
        /* Register the PMC's standard clocks */
        for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
@@ -634,11 +605,34 @@ int __init at91_clock_init(unsigned long main_clock)
                (unsigned) main_clock / 1000000,
                ((unsigned) main_clock % 1000000) / 1000);
 
-       /* disable all programmable clocks */
-       at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK0 | AT91_PMC_PCK1 | AT91_PMC_PCK2 | AT91_PMC_PCK3);
+       return 0;
+}
+
+/*
+ * Several unused clocks may be active.  Turn them off.
+ */
+static int __init at91_clock_reset(void)
+{
+       unsigned long pcdr = 0;
+       unsigned long scdr = 0;
+       struct clk *clk;
+
+       list_for_each_entry(clk, &clocks, node) {
+               if (clk->users > 0)
+                       continue;
+
+               if (clk->mode == pmc_periph_mode)
+                       pcdr |= clk->pmc_mask;
+
+               if (clk->mode == pmc_sys_mode)
+                       scdr |= clk->pmc_mask;
+
+               pr_debug("Clocks: disable unused %s\n", clk->name);
+       }
 
-       /* disable all other unused peripheral clocks */
-       at91_periphclk_reset();
+       at91_sys_write(AT91_PMC_PCDR, pcdr);
+       at91_sys_write(AT91_PMC_SCDR, scdr);
 
        return 0;
 }
+late_initcall(at91_clock_reset);