[ARM] 4604/2: AT91: Master clock divistor on SAM9

[linux-2.6-omap-h63xx.git] / arch / arm / mach-at91 / clock.c

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 06c9a0507d0d8316137507979a62d631f2861769..57c3b647ce834f06a790f04f48d18b11e7fd5d65 100644 (file)
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -351,7 +351,7 @@ static void init_programmable_clock(struct clk *clk)
        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
        parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
        clk->parent = parent;
-       clk->rate_hz = parent->rate_hz / (1 << ((pckr >> 2) & 3));
+       clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 }
 
 #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
@@ -364,19 +364,14 @@ static int at91_clk_show(struct seq_file *s, void *unused)
 {
        u32             scsr, pcsr, sr;
        struct clk      *clk;
-       unsigned        i;
 
        seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
        seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
-
        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
        seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
-
        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
-       for (i = 0; i < 4; i++)
-               seq_printf(s, "PCK%d = %8x\n", i, at91_sys_read(AT91_PMC_PCKR(i)));
        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 
        seq_printf(s, "\n");
@@ -592,8 +587,11 @@ int __init at91_clock_init(unsigned long main_clock)
        mckr = at91_sys_read(AT91_PMC_MCKR);
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
-       freq /= (1 << ((mckr >> 2) & 3));               /* prescale */
-       mck.rate_hz = freq / (1 + ((mckr >> 8) & 3));   /* mdiv */
+       freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
+       if (cpu_is_at91rm9200())
+               mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
+       else
+               mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
 
        /* Register the PMC's standard clocks */
        for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)