[ARM] 4933/1: AT91CAP9 UDPHS driver: generic AT91 parts.

[linux-2.6-omap-h63xx.git] / arch / arm / mach-at91 / pm.c

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 77d9669810eda5a9736acc5ac08d3acc22ee9216..aa863c1577087fa1bb0ba8ea5d26d8b37572c96b 100644 (file)
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -61,6 +61,15 @@ static inline void sdram_selfrefresh_enable(void)
 #else
 #include <asm/arch/at91sam9_sdramc.h>
 
+#ifdef CONFIG_ARCH_AT91SAM9263
+/*
+ * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
+ * handle those cases both here and in the Suspend-To-RAM support.
+ */
+#define        AT91_SDRAMC     AT91_SDRAMC0
+#warning Assuming EB1 SDRAM controller is *NOT* used
+#endif
+
 static u32 saved_lpr;
 
 static inline void sdram_selfrefresh_enable(void)
@@ -75,11 +84,79 @@ static inline void sdram_selfrefresh_enable(void)
 
 #define sdram_selfrefresh_disable()    at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
 
+#endif
+
+
 /*
- * FIXME: The AT91SAM9263 has a second EBI controller which may have
- *        additional SDRAM.  pm_slowclock.S will require a similar fix.
+ * Show the reason for the previous system reset.
  */
+#if defined(AT91_SHDWC)
 
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_shdwc.h>
+
+static void __init show_reset_status(void)
+{
+       static char reset[] __initdata = "reset";
+
+       static char general[] __initdata = "general";
+       static char wakeup[] __initdata = "wakeup";
+       static char watchdog[] __initdata = "watchdog";
+       static char software[] __initdata = "software";
+       static char user[] __initdata = "user";
+       static char unknown[] __initdata = "unknown";
+
+       static char signal[] __initdata = "signal";
+       static char rtc[] __initdata = "rtc";
+       static char rtt[] __initdata = "rtt";
+       static char restore[] __initdata = "power-restored";
+
+       char *reason, *r2 = reset;
+       u32 reset_type, wake_type;
+
+       reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
+       wake_type = at91_sys_read(AT91_SHDW_SR);
+
+       switch (reset_type) {
+       case AT91_RSTC_RSTTYP_GENERAL:
+               reason = general;
+               break;
+       case AT91_RSTC_RSTTYP_WAKEUP:
+               /* board-specific code enabled the wakeup sources */
+               reason = wakeup;
+
+               /* "wakeup signal" */
+               if (wake_type & AT91_SHDW_WAKEUP0)
+                       r2 = signal;
+               else {
+                       r2 = reason;
+                       if (wake_type & AT91_SHDW_RTTWK)        /* rtt wakeup */
+                               reason = rtt;
+                       else if (wake_type & AT91_SHDW_RTCWK)   /* rtc wakeup */
+                               reason = rtc;
+                       else if (wake_type == 0)        /* power-restored wakeup */
+                               reason = restore;
+                       else                            /* unknown wakeup */
+                               reason = unknown;
+               }
+               break;
+       case AT91_RSTC_RSTTYP_WATCHDOG:
+               reason = watchdog;
+               break;
+       case AT91_RSTC_RSTTYP_SOFTWARE:
+               reason = software;
+               break;
+       case AT91_RSTC_RSTTYP_USER:
+               reason = user;
+               break;
+       default:
+               reason = unknown;
+               break;
+       }
+       pr_info("AT91: Starting after %s %s\n", reason, r2);
+}
+#else
+static void __init show_reset_status(void) {}
 #endif
 
 
@@ -294,6 +371,7 @@ static int __init at91_pm_init(void)
 
        suspend_set_ops(&at91_pm_ops);
 
+       show_reset_status();
        return 0;
 }
 arch_initcall(at91_pm_init);